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7-segment LCD to BCD decoder ?

Started by N_Cook October 5, 2014
On Sunday, October 5, 2014 11:30:53 PM UTC-7, piglet wrote:
> On 05/10/2014 17:19, N_Cook wrote: > > > "mapping", output could be linear per digit rather than> > > When you write "linear per digit" do you mean an analog voltage like 0-9V or one-of-ten digital lines or what exactly please?
He probably mean binary, which is identical to bcd for 0-9. He got 4 digits, so 28 segments to transmit. PAL/GAL can compress it into 16 bits BCD and shift into serial data. In this case, we want 10 inputs, 1 output and 4 internal registers. For BLDC, we want 1 input and 6 outputs and 4 registers. So, we really want same chip with different packings. DIP 16 would be nice. So, let us ask lattice to bring back the PAL/GAL. // My logic goes over the limit // My logic goes over the peak // My logic goes over the limit // Oh, bring back my PAL/GAL to me, to me... // // Bring back, bring back // Bring back my PAL/GAL to me, to me // Bring back, bring back // Bring back my PAL/GAL to me
On Sun, 05 Oct 2014 10:03:18 -0700, Jim Thompson wrote:

> On Sun, 05 Oct 2014 17:19:34 +0100, N_Cook <diverse@tcp.co.uk> wrote: > >>Assuming one back-plane to consider , what would be most efficient >>component-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC >>to firstly convert the ex-oring business to proper levels and then the >>"mapping", output could be linear per digit rather than bcd. >>Starting with an off-the-shelf commercial unit where the LCD display is >>driven off a uC, to give a remotely monitorable feed > > So you want to convert LCD back to BCD? > > Are LCD signals normal... that is, active LOW? > > Map only 0 thru 9?
LCD signals are horrible from that point of view -- LCD elements need to be excited with AC -- if you put a DC voltage on them they can turn on permanently. Multiplexed LCD plates are worse -- I can't even describe it, just Google... -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
 
> > Are LCD signals normal... that is, active LOW? > > > Map only 0 thru 9? > > LCD signals are horrible from that point of view -- LCD elements need to be excited with AC -- if you put a DC voltage on them they can turn on permanently. Multiplexed LCD plates are worse -- I can't even describe it, just Google...
When a segment/common is lit, there are alternating voltage across it. However, you can simple sample the positive voltage with a diode. Of course, you have to adjust for the negative going "unknown drive signal" in software.
On 06/10/2014 18:51, edward.ming.lee@gmail.com wrote:
> When a segment/common is lit, there are alternating voltage across it. However, you can simple sample the positive voltage with a diode. Of course, you have to adjust for the negative going "unknown drive signal" in software. >
On the simpler LCDs - I guess like this one the OP has, all segments are driven with AC all the time (so the suggestion of rectifying would not be much help) but the "unlit" segment will be in-phase with the backplane and "lit" segments will be out-of-phase. The OP could recover segment data by xoring with the backplane or just latch segment data on the appropriate backplane state. piglet
On Monday, October 6, 2014 1:47:52 PM UTC-7, piglet wrote:
> On 06/10/2014 18:51, edward.ming.lee@gmail.com wrote: >=20 > > When a segment/common is lit, there are alternating voltage across it. =
However, you can simple sample the positive voltage with a diode. Of cour= se, you have to adjust for the negative going "unknown drive signal" in sof= tware.
>=20 > On the simpler LCDs - I guess like this one the OP has, all segments are =
driven with AC all the time (so the suggestion of rectifying would not be m= uch help) but the "unlit" segment will be in-phase with the backplane and "= lit" segments will be out-of-phase. The OP could recover segment data by xo= ring with the backplane or just latch segment data on the appropriate backp= lane state. OK, this should handle it. Z is the common (or backplane). ----------------------------------------------------------- NGAL ; 7 segment to bcd encoder ; Pin definition ;[18] [17] [16] [15] [14] [13] [12] [11] [10] VCC Q3 Q2 Q1 Q0 NC D9 D8 D7 ;[01] [02] [03] [04] [05] [06] [07] [08] [09] CLK D0 D1 D2 D3 D4 D5 D6 GND ; +- A -+ ; F B ; |- G -| ; E C ; +- D -+ ; ; Z A B C D E F G =20 ; D7 D6 D5 D4 D3 D2 D1 D0 Q3 Q2 Q1 Q0 ; 0: 0 1 1 1 1 1 1 0 0 0 0 0 ; 1: 0 0 1 1 0 0 0 0 0 0 0 1 ; 2: 0 1 1 0 1 1 0 1 0 0 1 0 ; 3: 0 1 1 1 1 0 0 1 0 0 1 1 ; 4: 0 0 1 1 0 0 1 1 0 1 0 0 ; 5: 0 1 0 1 1 0 1 1 0 1 0 1 ; 6: 0 1 0 1 1 1 1 1 0 1 1 0 ; 7: 0 1 1 1 0 0 0 0 0 1 1 1 ; 8: 0 1 1 1 1 1 1 1 1 0 0 0 ; 9: 0 1 1 1 1 0 1 1 1 0 0 1 ; 0: 1 0 0 0 0 0 0 1 0 0 0 0 ; 1: 1 1 0 0 1 1 1 1 0 0 0 1 ; 2: 1 0 0 1 0 0 1 0 0 0 1 0 ; 3: 1 0 0 0 0 1 1 0 0 0 1 1 ; 4: 1 1 0 0 1 1 0 0 0 1 0 0 ; 5: 1 0 1 0 0 1 0 0 0 1 0 1 ; 6: 1 0 1 0 0 0 0 0 0 1 1 0 ; 7: 1 0 0 0 1 1 1 1 0 1 1 1 ; 8: 1 0 0 0 0 0 0 0 1 0 0 0 ; 9: 1 0 0 0 0 1 0 0 1 0 0 1 ; ; D8 =3D latch, D9 =3D Shift, DA =3D SDI ; EQUATIONS _Q3 =3D _D9*_Q2=20 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 ; _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 ; _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 ; _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 ; _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 ; _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 ; _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 + _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9 ; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 ; _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 ; _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 ; _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 ; _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 ; _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 + _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 + _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9 _Q2 =3D _D9*_Q1=20 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 ; _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 ; _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 + _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 + _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 + _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 + _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9 ; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 ; _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 + _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 + _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 + _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 + _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 ; _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 ; _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 ; _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9 _Q1 =3D _D9*_Q0=20 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 ; _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 + _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 ; _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 ; _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 + _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 + _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9 ; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 + _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 + _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 ; _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 + _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 + _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 ; _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 ; _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9 _Q0 =3D _D9*_DA=20 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 + _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 ; _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 ; _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 + _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 ; _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 + _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9 ; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 + _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 ; _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 + _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 + _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 ; _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 + _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 ; _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 + _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9
On Mon, 06 Oct 2014 21:47:52 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On the simpler LCDs - I guess like this one the OP has, all segments are >driven with AC all the time (so the suggestion of rectifying would not >be much help) but the "unlit" segment will be in-phase with the >backplane and "lit" segments will be out-of-phase. The OP could recover >segment data by xoring with the backplane or just latch segment data on >the appropriate backplane state.
Exactly. No rocket science required.
On 10/7/2014 1:48 AM, pedro wrote:
> On Mon, 06 Oct 2014 21:47:52 +0100, piglet <erichpwagner@hotmail.com> > wrote: > >> On the simpler LCDs - I guess like this one the OP has, all segments are >> driven with AC all the time (so the suggestion of rectifying would not >> be much help) but the "unlit" segment will be in-phase with the >> backplane and "lit" segments will be out-of-phase. The OP could recover >> segment data by xoring with the backplane or just latch segment data on >> the appropriate backplane state. > > Exactly. No rocket science required.
There are some issues with timing as logic can work a lot faster than the edges on the LCD signals, but I think someone said that would be worked out in software on a processor somewhere... -- Rick
On 05/10/2014 20:16, Don Y wrote:
> On 10/5/2014 11:17 AM, N_Cook wrote: >> On 05/10/2014 18:24, Don Y wrote: >>> On 10/5/2014 9:19 AM, N_Cook wrote: >>>> Assuming one back-plane to consider , what would be most efficient >>>> component-count/least complex discrete/CMOS/74 route , ie not >>>> pic/Pi/uC to >>>> firstly convert the ex-oring business to proper levels and then the >>>> "mapping", >>>> output could be linear per digit rather than bcd. >>>> Starting with an off-the-shelf commercial unit where the LCD display >>>> is driven >>>> off a uC, to give a remotely monitorable feed >>> >>> First, you'd need to characterize the drive -- how much skew is >>> there between backplane drive and segment on/off drives (any skew >>> will appear as potential glitches on a static, combinatorial >>> logic decoder so you would have to *sample* the decoded outputs >>> at some epsilon after each BP clock edge). >>> >>> [epsilon can be large-ish if a MCU is "decoding in software". >>> Also, consider temperature effects on the drive] >>> >>> You would also need to look at the particular "font" that is >>> implemented: do 6's have tails? what about 9's? (sometimes >>> 6 will have but 9 won't). >>> >>> And, any "other characters" that the display might present from >>> time to time (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) >>> that might collide with some of the "don't cares" in your >>> decoder logic. >>> >>> The basic approach is simple: just build some Karnaugh maps >>> describing each segment's performance. Then, cover the most >>> appropriate ones with minterms to get your *desired* outputs >>> (subject to the above notes) >>> >>> Note that it is *really* important to understand how the display >>> is actually being driven. You can play games with the visual >>> characteristics of LCD's by driving them in unconventional (yet >>> "legal") ways. >> >> The other consideration is often there is a contrast control which >> AFAIK is >> variation of the fractional step change voltages, so more complication >> unless >> you set for one contrast setting only > > Chances are (?), you will need some sort of level translation *somewhere*. > You can accommodate some amount of variability *there*. (driving high > impedance inputs menas you might even be able to just use some resistive > dividers, etc.) > > IMO, the biggest issue will be knowing *when* to "look" at the data > (segments and/or output of your "decoder") as you may not have RELIABLE > data on how the data appears on the display pins wrt the backplane drive > (phase). Nonmultiplexed displays have a lot of latitude in how they > react (visibly) to often significant changes in drive. Your logic > (or, whatever your circuit eventually feeds) may not expect that. > > Gotta run -- off to a "reception" (which most probably will NOT be "fun")
I'll have to check out that potential snag-pit first, before moving on to sorting out how to program PAL/GAL. Somewhere I have an EPROM blower/copier ,whether GAL capable, no idea
As no fast response is required , would this work? I really don't want 
to get involved with GAL programming .
Plus perhaps some level shifting or inversions and just considering 1 digit.
A free-running all states sequencing BCD source, until inhibited.
Feeding a CMOS 4543 (BCD to 7 seg LCD) , the backplane feeding the PH 
pin of the 4543. Then compare LCD 7seg pins and matching 4543 o/p pins 
with a couple of 4081 quad-AND packs ANDed together to provide an 
inhibit back to the BCD source. Taking overall output as the BCD source 
lines when inhibited.
4081 >> 4082