I tried to create an LTspice simulation of Jim Thompson's headphone amp (5/21/14 5:16 PM post). I got the supertex models from supertex.com and the TL082 model from TI. When run it produces the error message: Fatal Error: Port(pin) count mismatch between the definition of subcircuit "tl082" and instance: "xu2" The instance has more connection terminals than the definition. What have I got wrong? Below is my netlist: R1 out N001 50k R2 N001 N004 10k R3 0 out 32 R4 V- N006 6.8 C1 N004 in 1� V1 V+ 0 6 V2 0 V- 6 V3 in 0 SINE(0 0.2 1e3) M1 V+ N002 out N003 DN2540 M2 out V- N006 N005 DN2540 XU2 0 N001 V+ V- N002 TL082.lib TL082 .model NMOS NMOS .model PMOS PMOS .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib .tran 0.1 startup uic .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib .backanno .end
Headphone amp simulation
Started by ●May 26, 2014
Reply by ●May 26, 20142014-05-26
On 05/26/2014 05:10 AM, garyr wrote:> I tried to create an LTspice simulation of Jim Thompson's headphone amp > (5/21/14 5:16 PM post). I got the supertex models from supertex.com and the > TL082 model from TI. When run it produces the error message: > > Fatal Error: Port(pin) count mismatch between the definition of subcircuit > "tl082" and instance: "xu2" > The instance has more connection terminals than the definition. > > What have I got wrong? > > Below is my netlist: > > R1 out N001 50k > R2 N001 N004 10k > R3 0 out 32 > R4 V- N006 6.8 > C1 N004 in 1� > V1 V+ 0 6 > V2 0 V- 6 > V3 in 0 SINE(0 0.2 1e3) > M1 V+ N002 out N003 DN2540 > M2 out V- N006 N005 DN2540 > XU2 0 N001 V+ V- N002 TL082.lib TL082 > .model NMOS NMOS > .model PMOS PMOS > .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos > .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib > .tran 0.1 startup uic > .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib > .backanno > .end > > >TL082.lib has fewer connections than the opamp symbol you are using? (perhaps it's behavioral and lacks supply nodes or whatever) You'll have to look at the lib file..
Reply by ●May 26, 20142014-05-26
"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message news:lludqg$vbp$1@speranza.aioe.org...> On 05/26/2014 05:10 AM, garyr wrote: >> I tried to create an LTspice simulation of Jim Thompson's headphone amp >> (5/21/14 5:16 PM post). I got the supertex models from supertex.com and >> the >> TL082 model from TI. When run it produces the error message: >> >> Fatal Error: Port(pin) count mismatch between the definition of >> subcircuit >> "tl082" and instance: "xu2" >> The instance has more connection terminals than the definition. >> >> What have I got wrong? >> >> Below is my netlist: >> >> R1 out N001 50k >> R2 N001 N004 10k >> R3 0 out 32 >> R4 V- N006 6.8 >> C1 N004 in 1� >> V1 V+ 0 6 >> V2 0 V- 6 >> V3 in 0 SINE(0 0.2 1e3) >> M1 V+ N002 out N003 DN2540 >> M2 out V- N006 N005 DN2540 >> XU2 0 N001 V+ V- N002 TL082.lib TL082 >> .model NMOS NMOS >> .model PMOS PMOS >> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >> .tran 0.1 startup uic >> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >> .backanno >> .end >> >> >> > TL082.lib has fewer connections than the opamp symbol you are using? > (perhaps it's behavioral and lacks supply nodes or whatever) > You'll have to look at the lib file.. >I finally discovered that a subcircuit is not the same as a model and needed to delete the reference to TL082.lib in the opamp instance and change .lib ...TL082.lib to .include ... TL082.lib. That solved the connection problem. Now the simulation runs briefly and generates the error message: Analysis: Time step too small; time = 2.58595e-006, timestep = 1.25e-019: trouble with u2:jx-instance j:u2:1 The netlist file is now 64 lines long. I tried to include it as a file but apparently that is not permitted. I'll post it if anyone is interested.
Reply by ●May 26, 20142014-05-26
On Mon, 26 May 2014 07:51:28 -0700, "garyr" <garyr@fidalgo.net> wrote:> >"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message >news:lludqg$vbp$1@speranza.aioe.org... >> On 05/26/2014 05:10 AM, garyr wrote: >>> I tried to create an LTspice simulation of Jim Thompson's headphone amp >>> (5/21/14 5:16 PM post). I got the supertex models from supertex.com and >>> the >>> TL082 model from TI. When run it produces the error message: >>> >>> Fatal Error: Port(pin) count mismatch between the definition of >>> subcircuit >>> "tl082" and instance: "xu2" >>> The instance has more connection terminals than the definition. >>> >>> What have I got wrong? >>> >>> Below is my netlist: >>> >>> R1 out N001 50k >>> R2 N001 N004 10k >>> R3 0 out 32 >>> R4 V- N006 6.8 >>> C1 N004 in 1� >>> V1 V+ 0 6 >>> V2 0 V- 6 >>> V3 in 0 SINE(0 0.2 1e3) >>> M1 V+ N002 out N003 DN2540 >>> M2 out V- N006 N005 DN2540 >>> XU2 0 N001 V+ V- N002 TL082.lib TL082 >>> .model NMOS NMOS >>> .model PMOS PMOS >>> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >>> .tran 0.1 startup uic >>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >>> .backanno >>> .end >>> >>> >>> >> TL082.lib has fewer connections than the opamp symbol you are using? >> (perhaps it's behavioral and lacks supply nodes or whatever) >> You'll have to look at the lib file.. >> > >I finally discovered that a subcircuit is not the same as a model and needed >to delete the reference to TL082.lib in the opamp instance and change .lib >...TL082.lib to .include ... TL082.lib. That solved the connection problem. > >Now the simulation runs briefly and generates the error message: > >Analysis: Time step too small; time = 2.58595e-006, timestep = 1.25e-019: >trouble with u2:jx-instance j:u2:1 > >The netlist file is now 64 lines long. I tried to include it as a file but >apparently that is not permitted. I'll post it if anyone is interested. >Post your latest LTspice file as you did above. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | #BringBackOurBalls
Reply by ●May 26, 20142014-05-26
"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in message news:him6o95n146kb4iuqvv26erjh11r4nahq7@4ax.com...> On Mon, 26 May 2014 07:51:28 -0700, "garyr" <garyr@fidalgo.net> wrote: > >> >>"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message >>news:lludqg$vbp$1@speranza.aioe.org... >>> On 05/26/2014 05:10 AM, garyr wrote: >>>> I tried to create an LTspice simulation of Jim Thompson's headphone amp >>>> (5/21/14 5:16 PM post). I got the supertex models from supertex.com and >>>> the >>>> TL082 model from TI. When run it produces the error message: >>>> >>>> Fatal Error: Port(pin) count mismatch between the definition of >>>> subcircuit >>>> "tl082" and instance: "xu2" >>>> The instance has more connection terminals than the definition. >>>> >>>> What have I got wrong? >>>> >>>> Below is my netlist: >>>> >>>> R1 out N001 50k >>>> R2 N001 N004 10k >>>> R3 0 out 32 >>>> R4 V- N006 6.8 >>>> C1 N004 in 1� >>>> V1 V+ 0 6 >>>> V2 0 V- 6 >>>> V3 in 0 SINE(0 0.2 1e3) >>>> M1 V+ N002 out N003 DN2540 >>>> M2 out V- N006 N005 DN2540 >>>> XU2 0 N001 V+ V- N002 TL082.lib TL082 >>>> .model NMOS NMOS >>>> .model PMOS PMOS >>>> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >>>> .tran 0.1 startup uic >>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >>>> .backanno >>>> .end >>>> >>>> >>>> >>> TL082.lib has fewer connections than the opamp symbol you are using? >>> (perhaps it's behavioral and lacks supply nodes or whatever) >>> You'll have to look at the lib file.. >>> >> >>I finally discovered that a subcircuit is not the same as a model and >>needed >>to delete the reference to TL082.lib in the opamp instance and change .lib >>...TL082.lib to .include ... TL082.lib. That solved the connection >>problem. >> >>Now the simulation runs briefly and generates the error message: >> >>Analysis: Time step too small; time = 2.58595e-006, timestep = 1.25e-019: >>trouble with u2:jx-instance j:u2:1 >> >>The netlist file is now 64 lines long. I tried to include it as a file but >>apparently that is not permitted. I'll post it if anyone is interested. >> > > Post your latest LTspice file as you did above. > > ...Jim Thompson > -- > | James E.Thompson | mens | > | Analog Innovations | et | > | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | > | San Tan Valley, AZ 85142 Skype: Contacts Only | | > | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | > | E-mail Icon at http://www.analog-innovations.com | 1962 | > > #BringBackOurBalls"ExpressPCB Netlist" "LTspice IV Version 4.18p" 1 0 0 "" "" "" "Part IDs Table" "R1" "50k" "" "R2" "10k" "" "R3" "32" "" "R4" "6.8" "" "C1" "1�" "" "V1" "6" "" "V2" "6" "" "V3" "SINE(0 0.2 1e3)" "" "M1" "DN2540" "" "M2" "DN2540" "" "U2" "TL082" "" "Net Names Table" "out" 1 "N001" 5 "N004" 8 "0" 10 "V-" 15 "N006" 19 "in" 21 "V+" 23 "N002" 26 "N003" 28 "N005" 29 "Net Connections Table" 1 1 1 2 1 3 2 3 1 9 3 4 1 10 1 0 2 1 2 6 2 2 1 7 2 11 2 0 3 2 2 9 3 5 1 0 4 3 1 11 4 6 2 12 4 7 1 13 4 8 2 14 4 11 1 0 5 4 1 16 5 7 2 17 5 10 2 18 5 11 4 0 6 4 2 20 6 10 3 0 7 5 2 22 7 8 1 0 8 6 1 24 8 9 1 25 8 11 3 0 9 9 2 27 9 11 5 0 10 9 4 0 11 10 4 0
Reply by ●May 26, 20142014-05-26
On Mon, 26 May 2014 08:44:37 -0700, "garyr" <garyr@fidalgo.net> wrote:> >"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in >message news:him6o95n146kb4iuqvv26erjh11r4nahq7@4ax.com... >> On Mon, 26 May 2014 07:51:28 -0700, "garyr" <garyr@fidalgo.net> wrote: >> >>> >>>"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message >>>news:lludqg$vbp$1@speranza.aioe.org... >>>> On 05/26/2014 05:10 AM, garyr wrote: >>>>> I tried to create an LTspice simulation of Jim Thompson's headphone amp >>>>> (5/21/14 5:16 PM post). I got the supertex models from supertex.com and >>>>> the >>>>> TL082 model from TI. When run it produces the error message: >>>>> >>>>> Fatal Error: Port(pin) count mismatch between the definition of >>>>> subcircuit >>>>> "tl082" and instance: "xu2" >>>>> The instance has more connection terminals than the definition. >>>>> >>>>> What have I got wrong? >>>>> >>>>> Below is my netlist: >>>>> >>>>> R1 out N001 50k >>>>> R2 N001 N004 10k >>>>> R3 0 out 32 >>>>> R4 V- N006 6.8 >>>>> C1 N004 in 1� >>>>> V1 V+ 0 6 >>>>> V2 0 V- 6 >>>>> V3 in 0 SINE(0 0.2 1e3) >>>>> M1 V+ N002 out N003 DN2540 >>>>> M2 out V- N006 N005 DN2540 >>>>> XU2 0 N001 V+ V- N002 TL082.lib TL082 >>>>> .model NMOS NMOS >>>>> .model PMOS PMOS >>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >>>>> .tran 0.1 startup uic >>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >>>>> .backanno >>>>> .end >>>>> >>>>> >>>>> >>>> TL082.lib has fewer connections than the opamp symbol you are using? >>>> (perhaps it's behavioral and lacks supply nodes or whatever) >>>> You'll have to look at the lib file.. >>>> >>> >>>I finally discovered that a subcircuit is not the same as a model and >>>needed >>>to delete the reference to TL082.lib in the opamp instance and change .lib >>>...TL082.lib to .include ... TL082.lib. That solved the connection >>>problem. >>> >>>Now the simulation runs briefly and generates the error message: >>> >>>Analysis: Time step too small; time = 2.58595e-006, timestep = 1.25e-019: >>>trouble with u2:jx-instance j:u2:1 >>> >>>The netlist file is now 64 lines long. I tried to include it as a file but >>>apparently that is not permitted. I'll post it if anyone is interested. >>> >> >> Post your latest LTspice file as you did above. >>[snip]> >"ExpressPCB Netlist" >"LTspice IV Version 4.18p" >1 >0 >0 >"" >"" >"" >"Part IDs Table" >"R1" "50k" "" >"R2" "10k" "" >"R3" "32" "" >"R4" "6.8" "" >"C1" "1�" "" >"V1" "6" "" >"V2" "6" "" >"V3" "SINE(0 0.2 1e3)" "" >"M1" "DN2540" "" >"M2" "DN2540" "" >"U2" "TL082" "" > >"Net Names Table" >"out" 1 >"N001" 5 >"N004" 8 >"0" 10 >"V-" 15 >"N006" 19 >"in" 21 >"V+" 23 >"N002" 26 >"N003" 28 >"N005" 29 > >"Net Connections Table" >1 1 1 2 >1 3 2 3 >1 9 3 4 >1 10 1 0 >2 1 2 6 >2 2 1 7 >2 11 2 0 >3 2 2 9 >3 5 1 0 >4 3 1 11 >4 6 2 12 >4 7 1 13 >4 8 2 14 >4 11 1 0 >5 4 1 16 >5 7 2 17 >5 10 2 18 >5 11 4 0 >6 4 2 20 >6 10 3 0 >7 5 2 22 >7 8 1 0 >8 6 1 24 >8 9 1 25 >8 11 3 0 >9 9 2 27 >9 11 5 0 >10 9 4 0 >11 10 4 0 > > >That's not an LTspice .asc listing. It's a PCB layout format. If you've drawn it in LTspice, you'll find a file *.asc... it's text... copy that text and post it here. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | #BringBackOurBalls
Reply by ●May 26, 20142014-05-26
"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in message news:inr6o99353cbta4d07iugind5pgr43o5ie@4ax.com...> On Mon, 26 May 2014 08:44:37 -0700, "garyr" <garyr@fidalgo.net> wrote: > >> >>"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote >>in >>message news:him6o95n146kb4iuqvv26erjh11r4nahq7@4ax.com... >>> On Mon, 26 May 2014 07:51:28 -0700, "garyr" <garyr@fidalgo.net> wrote: >>> >>>> >>>>"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message >>>>news:lludqg$vbp$1@speranza.aioe.org... >>>>> On 05/26/2014 05:10 AM, garyr wrote: >>>>>> I tried to create an LTspice simulation of Jim Thompson's headphone >>>>>> amp >>>>>> (5/21/14 5:16 PM post). I got the supertex models from supertex.com >>>>>> and >>>>>> the >>>>>> TL082 model from TI. When run it produces the error message: >>>>>> >>>>>> Fatal Error: Port(pin) count mismatch between the definition of >>>>>> subcircuit >>>>>> "tl082" and instance: "xu2" >>>>>> The instance has more connection terminals than the definition. >>>>>> >>>>>> What have I got wrong? >>>>>> >>>>>> Below is my netlist: >>>>>> >>>>>> R1 out N001 50k >>>>>> R2 N001 N004 10k >>>>>> R3 0 out 32 >>>>>> R4 V- N006 6.8 >>>>>> C1 N004 in 1� >>>>>> V1 V+ 0 6 >>>>>> V2 0 V- 6 >>>>>> V3 in 0 SINE(0 0.2 1e3) >>>>>> M1 V+ N002 out N003 DN2540 >>>>>> M2 out V- N006 N005 DN2540 >>>>>> XU2 0 N001 V+ V- N002 TL082.lib TL082 >>>>>> .model NMOS NMOS >>>>>> .model PMOS PMOS >>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >>>>>> .tran 0.1 startup uic >>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >>>>>> .backanno >>>>>> .end >>>>>> >>>>>> >>>>>> >>>>> TL082.lib has fewer connections than the opamp symbol you are using? >>>>> (perhaps it's behavioral and lacks supply nodes or whatever) >>>>> You'll have to look at the lib file.. >>>>> >>>> >>>>I finally discovered that a subcircuit is not the same as a model and >>>>needed >>>>to delete the reference to TL082.lib in the opamp instance and change >>>>.lib >>>>...TL082.lib to .include ... TL082.lib. That solved the connection >>>>problem. >>>> >>>>Now the simulation runs briefly and generates the error message: >>>> >>>>Analysis: Time step too small; time = 2.58595e-006, timestep = >>>>1.25e-019: >>>>trouble with u2:jx-instance j:u2:1 >>>> >>>>The netlist file is now 64 lines long. I tried to include it as a file >>>>but >>>>apparently that is not permitted. I'll post it if anyone is interested. >>>> >>> >>> Post your latest LTspice file as you did above. >>> > [snip] >> >>"ExpressPCB Netlist" >>"LTspice IV Version 4.18p"[snip]> > That's not an LTspice .asc listing. It's a PCB layout format. > > If you've drawn it in LTspice, you'll find a file *.asc... it's > text... copy that text and post it here.Version 4 SHEET 1 880 680 WIRE 0 144 -48 144 WIRE 160 160 64 160 WIRE 208 160 208 128 WIRE 0 176 -16 176 WIRE -16 208 -16 176 WIRE -512 240 -512 224 WIRE -512 240 -576 240 WIRE -576 256 -576 240 WIRE -512 288 -512 240 WIRE -240 288 -336 288 WIRE -144 288 -176 288 WIRE -48 288 -48 144 WIRE -48 288 -64 288 WIRE -16 288 -48 288 WIRE 208 288 208 176 WIRE 208 288 64 288 WIRE 368 288 208 288 WIRE -336 304 -336 288 WIRE 368 304 368 288 WIRE 208 320 208 288 WIRE 160 400 112 400 WIRE 208 400 208 368 WIRE 112 432 112 400 WIRE 208 432 208 416 FLAG -16 208 0 FLAG 368 384 0 FLAG -336 384 0 FLAG -576 256 0 FLAG -512 144 V+ FLAG 208 80 V+ FLAG 32 128 V+ FLAG -512 368 V- FLAG 32 192 V- FLAG 208 512 V- FLAG 112 432 V- FLAG 368 288 out FLAG -336 288 in SYMBOL res 80 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 50k SYMBOL res -48 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 35 66 VTop 2 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 384 400 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R3 SYMATTR Value 32 SYMBOL res 224 528 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R4 SYMATTR Value 6.8 SYMBOL cap -176 272 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1� SYMBOL voltage -512 128 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 6 SYMBOL voltage -512 272 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 6 SYMBOL voltage -336 288 R0 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 38 72 Left 2 SYMATTR Value SINE(0 0.2 1e3) SYMATTR InstName V3 SYMBOL nmos4 160 80 R0 SYMATTR InstName M1 SYMATTR Value DN2540 SYMBOL nmos4 160 320 R0 SYMATTR InstName M2 SYMATTR Value DN2540 SYMBOL Opamps\\opamp2 32 96 R0 SYMATTR InstName U2 SYMATTR Value TL082 TEXT -536 496 Left 2 !.lib C:\\Program Files\\LTC\\LTspiceIV\\lib\\mylib\\supertex.lib TEXT -536 464 Left 2 !.tran 0.1 startup uic TEXT -536 528 Left 2 !.include C:\\Program Files\\LTC\\LTspiceIV\\lib\\mylib\\TL082.lib
Reply by ●May 26, 20142014-05-26
On Mon, 26 May 2014 10:05:32 -0700, "garyr" <garyr@fidalgo.net> wrote:> >"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in >message news:inr6o99353cbta4d07iugind5pgr43o5ie@4ax.com... >> On Mon, 26 May 2014 08:44:37 -0700, "garyr" <garyr@fidalgo.net> wrote: >> >>> >>>"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote >>>in >>>message news:him6o95n146kb4iuqvv26erjh11r4nahq7@4ax.com... >>>> On Mon, 26 May 2014 07:51:28 -0700, "garyr" <garyr@fidalgo.net> wrote: >>>> >>>>> >>>>>"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message >>>>>news:lludqg$vbp$1@speranza.aioe.org... >>>>>> On 05/26/2014 05:10 AM, garyr wrote: >>>>>>> I tried to create an LTspice simulation of Jim Thompson's headphone >>>>>>> amp >>>>>>> (5/21/14 5:16 PM post). I got the supertex models from supertex.com >>>>>>> and >>>>>>> the >>>>>>> TL082 model from TI. When run it produces the error message: >>>>>>> >>>>>>> Fatal Error: Port(pin) count mismatch between the definition of >>>>>>> subcircuit >>>>>>> "tl082" and instance: "xu2" >>>>>>> The instance has more connection terminals than the definition. >>>>>>> >>>>>>> What have I got wrong? >>>>>>> >>>>>>> Below is my netlist: >>>>>>> >>>>>>> R1 out N001 50k >>>>>>> R2 N001 N004 10k >>>>>>> R3 0 out 32 >>>>>>> R4 V- N006 6.8 >>>>>>> C1 N004 in 1� >>>>>>> V1 V+ 0 6 >>>>>>> V2 0 V- 6 >>>>>>> V3 in 0 SINE(0 0.2 1e3) >>>>>>> M1 V+ N002 out N003 DN2540 >>>>>>> M2 out V- N006 N005 DN2540 >>>>>>> XU2 0 N001 V+ V- N002 TL082.lib TL082 >>>>>>> .model NMOS NMOS >>>>>>> .model PMOS PMOS >>>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >>>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >>>>>>> .tran 0.1 startup uic >>>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >>>>>>> .backanno >>>>>>> .end >>>>>>> >>>>>>> >>>>>>> >>>>>> TL082.lib has fewer connections than the opamp symbol you are using? >>>>>> (perhaps it's behavioral and lacks supply nodes or whatever) >>>>>> You'll have to look at the lib file.. >>>>>> >>>>> >>>>>I finally discovered that a subcircuit is not the same as a model and >>>>>needed >>>>>to delete the reference to TL082.lib in the opamp instance and change >>>>>.lib >>>>>...TL082.lib to .include ... TL082.lib. That solved the connection >>>>>problem. >>>>> >>>>>Now the simulation runs briefly and generates the error message: >>>>> >>>>>Analysis: Time step too small; time = 2.58595e-006, timestep = >>>>>1.25e-019: >>>>>trouble with u2:jx-instance j:u2:1 >>>>> >>>>>The netlist file is now 64 lines long. I tried to include it as a file >>>>>but >>>>>apparently that is not permitted. I'll post it if anyone is interested. >>>>> >>>> >>>> Post your latest LTspice file as you did above. >>>> >> [snip] >>> >>>"ExpressPCB Netlist" >>>"LTspice IV Version 4.18p" >[snip] >> >> That's not an LTspice .asc listing. It's a PCB layout format. >> >> If you've drawn it in LTspice, you'll find a file *.asc... it's >> text... copy that text and post it here. > >Version 4 >SHEET 1 880 680 >WIRE 0 144 -48 144 >WIRE 160 160 64 160 >WIRE 208 160 208 128 >WIRE 0 176 -16 176 >WIRE -16 208 -16 176 >WIRE -512 240 -512 224 >WIRE -512 240 -576 240 >WIRE -576 256 -576 240 >WIRE -512 288 -512 240 >WIRE -240 288 -336 288 >WIRE -144 288 -176 288 >WIRE -48 288 -48 144 >WIRE -48 288 -64 288 >WIRE -16 288 -48 288 >WIRE 208 288 208 176 >WIRE 208 288 64 288 >WIRE 368 288 208 288 >WIRE -336 304 -336 288 >WIRE 368 304 368 288 >WIRE 208 320 208 288 >WIRE 160 400 112 400 >WIRE 208 400 208 368 >WIRE 112 432 112 400 >WIRE 208 432 208 416 >FLAG -16 208 0 >FLAG 368 384 0 >FLAG -336 384 0 >FLAG -576 256 0 >FLAG -512 144 V+ >FLAG 208 80 V+ >FLAG 32 128 V+ >FLAG -512 368 V- >FLAG 32 192 V- >FLAG 208 512 V- >FLAG 112 432 V- >FLAG 368 288 out >FLAG -336 288 in >SYMBOL res 80 272 R90 >WINDOW 0 0 56 VBottom 2 >WINDOW 3 32 56 VTop 2 >SYMATTR InstName R1 >SYMATTR Value 50k >SYMBOL res -48 272 R90 >WINDOW 0 0 56 VBottom 2 >WINDOW 3 35 66 VTop 2 >SYMATTR InstName R2 >SYMATTR Value 10k >SYMBOL res 384 400 R180 >WINDOW 0 36 76 Left 2 >WINDOW 3 36 40 Left 2 >SYMATTR InstName R3 >SYMATTR Value 32 >SYMBOL res 224 528 R180 >WINDOW 0 36 76 Left 2 >WINDOW 3 36 40 Left 2 >SYMATTR InstName R4 >SYMATTR Value 6.8 >SYMBOL cap -176 272 R90 >WINDOW 0 0 32 VBottom 2 >WINDOW 3 32 32 VTop 2 >SYMATTR InstName C1 >SYMATTR Value 1� >SYMBOL voltage -512 128 R0 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR InstName V1 >SYMATTR Value 6 >SYMBOL voltage -512 272 R0 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR InstName V2 >SYMATTR Value 6 >SYMBOL voltage -336 288 R0 >WINDOW 123 24 124 Left 2 >WINDOW 39 0 0 Left 2 >WINDOW 3 38 72 Left 2 >SYMATTR Value SINE(0 0.2 1e3) >SYMATTR InstName V3 >SYMBOL nmos4 160 80 R0 >SYMATTR InstName M1 >SYMATTR Value DN2540 >SYMBOL nmos4 160 320 R0 >SYMATTR InstName M2 >SYMATTR Value DN2540 >SYMBOL Opamps\\opamp2 32 96 R0 >SYMATTR InstName U2 >SYMATTR Value TL082 >TEXT -536 496 Left 2 !.lib C:\\Program >Files\\LTC\\LTspiceIV\\lib\\mylib\\supertex.lib >TEXT -536 464 Left 2 !.tran 0.1 startup uic >TEXT -536 528 Left 2 !.include C:\\Program >Files\\LTC\\LTspiceIV\\lib\\mylib\\TL082.lib >LTspice doesn't like those last "TEXT" lines, complaining of a syntax problem. Anyone (everyone :-) more familiar with LTspice than me, how should those library calls be corrected? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | #BringBackOurBalls
Reply by ●May 26, 20142014-05-26
Den mandag den 26. maj 2014 20.32.05 UTC+2 skrev Jim Thompson:> On Mon, 26 May 2014 10:05:32 -0700, "garyr" <garyr@fidalgo.net> wrote: >=20 >=20 >=20 > > >=20 > >"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote=in=20>=20 > >message news:inr6o99353cbta4d07iugind5pgr43o5ie@4ax.com... >=20 > >> On Mon, 26 May 2014 08:44:37 -0700, "garyr" <garyr@fidalgo.net> wrote: >=20 > >> >=20 > >>> >=20 > >>>"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wro=te=20>=20 > >>>in >=20 > >>>message news:him6o95n146kb4iuqvv26erjh11r4nahq7@4ax.com... >=20 > >>>> On Mon, 26 May 2014 07:51:28 -0700, "garyr" <garyr@fidalgo.net> wrot=e:>=20 > >>>> >=20 > >>>>> >=20 > >>>>>"Johann Klammer" <klammerj@NOSPAM.a1.net> wrote in message >=20 > >>>>>news:lludqg$vbp$1@speranza.aioe.org... >=20 > >>>>>> On 05/26/2014 05:10 AM, garyr wrote: >=20 > >>>>>>> I tried to create an LTspice simulation of Jim Thompson's headpho=ne=20>=20 > >>>>>>> amp >=20 > >>>>>>> (5/21/14 5:16 PM post). I got the supertex models from supertex.c=om=20>=20 > >>>>>>> and >=20 > >>>>>>> the >=20 > >>>>>>> TL082 model from TI. When run it produces the error message: >=20 > >>>>>>> >=20 > >>>>>>> Fatal Error: Port(pin) count mismatch between the definition of >=20 > >>>>>>> subcircuit >=20 > >>>>>>> "tl082" and instance: "xu2" >=20 > >>>>>>> The instance has more connection terminals than the definition. >=20 > >>>>>>> >=20 > >>>>>>> What have I got wrong? >=20 > >>>>>>> >=20 > >>>>>>> Below is my netlist: >=20 > >>>>>>> >=20 > >>>>>>> R1 out N001 50k >=20 > >>>>>>> R2 N001 N004 10k >=20 > >>>>>>> R3 0 out 32 >=20 > >>>>>>> R4 V- N006 6.8 >=20 > >>>>>>> C1 N004 in 1=EF=BF=BD >=20 > >>>>>>> V1 V+ 0 6 >=20 > >>>>>>> V2 0 V- 6 >=20 > >>>>>>> V3 in 0 SINE(0 0.2 1e3) >=20 > >>>>>>> M1 V+ N002 out N003 DN2540 >=20 > >>>>>>> M2 out V- N006 N005 DN2540 >=20 > >>>>>>> XU2 0 N001 V+ V- N002 TL082.lib TL082 >=20 > >>>>>>> .model NMOS NMOS >=20 > >>>>>>> .model PMOS PMOS >=20 > >>>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos >=20 > >>>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\supertex.lib >=20 > >>>>>>> .tran 0.1 startup uic >=20 > >>>>>>> .lib C:\Program Files\LTC\LTspiceIV\lib\mylib\TL082.lib >=20 > >>>>>>> .backanno >=20 > >>>>>>> .end >=20 > >>>>>>> >=20 > >>>>>>> >=20 > >>>>>>> >=20 > >>>>>> TL082.lib has fewer connections than the opamp symbol you are usin=g?>=20 > >>>>>> (perhaps it's behavioral and lacks supply nodes or whatever) >=20 > >>>>>> You'll have to look at the lib file.. >=20 > >>>>>> >=20 > >>>>> >=20 > >>>>>I finally discovered that a subcircuit is not the same as a model an=d>=20 > >>>>>needed >=20 > >>>>>to delete the reference to TL082.lib in the opamp instance and chang=e=20>=20 > >>>>>.lib >=20 > >>>>>...TL082.lib to .include ... TL082.lib. That solved the connection >=20 > >>>>>problem. >=20 > >>>>> >=20 > >>>>>Now the simulation runs briefly and generates the error message: >=20 > >>>>> >=20 > >>>>>Analysis: Time step too small; time =3D 2.58595e-006, timestep =3D==20>=20 > >>>>>1.25e-019: >=20 > >>>>>trouble with u2:jx-instance j:u2:1 >=20 > >>>>> >=20 > >>>>>The netlist file is now 64 lines long. I tried to include it as a fi=le=20>=20 > >>>>>but >=20 > >>>>>apparently that is not permitted. I'll post it if anyone is interest=ed.>=20 > >>>>> >=20 > >>>> >=20 > >>>> Post your latest LTspice file as you did above. >=20 > >>>> >=20 > >> [snip] >=20 > >>> >=20 > >>>"ExpressPCB Netlist" >=20 > >>>"LTspice IV Version 4.18p" >=20 > >[snip] >=20 > >> >=20 > >> That's not an LTspice .asc listing. It's a PCB layout format. >=20 > >> >=20 > >> If you've drawn it in LTspice, you'll find a file *.asc... it's >=20 > >> text... copy that text and post it here. >=20 > > >=20 > >Version 4 >=20 > >SHEET 1 880 680 >=20 > >WIRE 0 144 -48 144 >=20 > >WIRE 160 160 64 160 >=20 > >WIRE 208 160 208 128 >=20 > >WIRE 0 176 -16 176 >=20 > >WIRE -16 208 -16 176 >=20 > >WIRE -512 240 -512 224 >=20 > >WIRE -512 240 -576 240 >=20 > >WIRE -576 256 -576 240 >=20 > >WIRE -512 288 -512 240 >=20 > >WIRE -240 288 -336 288 >=20 > >WIRE -144 288 -176 288 >=20 > >WIRE -48 288 -48 144 >=20 > >WIRE -48 288 -64 288 >=20 > >WIRE -16 288 -48 288 >=20 > >WIRE 208 288 208 176 >=20 > >WIRE 208 288 64 288 >=20 > >WIRE 368 288 208 288 >=20 > >WIRE -336 304 -336 288 >=20 > >WIRE 368 304 368 288 >=20 > >WIRE 208 320 208 288 >=20 > >WIRE 160 400 112 400 >=20 > >WIRE 208 400 208 368 >=20 > >WIRE 112 432 112 400 >=20 > >WIRE 208 432 208 416 >=20 > >FLAG -16 208 0 >=20 > >FLAG 368 384 0 >=20 > >FLAG -336 384 0 >=20 > >FLAG -576 256 0 >=20 > >FLAG -512 144 V+ >=20 > >FLAG 208 80 V+ >=20 > >FLAG 32 128 V+ >=20 > >FLAG -512 368 V- >=20 > >FLAG 32 192 V- >=20 > >FLAG 208 512 V- >=20 > >FLAG 112 432 V- >=20 > >FLAG 368 288 out >=20 > >FLAG -336 288 in >=20 > >SYMBOL res 80 272 R90 >=20 > >WINDOW 0 0 56 VBottom 2 >=20 > >WINDOW 3 32 56 VTop 2 >=20 > >SYMATTR InstName R1 >=20 > >SYMATTR Value 50k >=20 > >SYMBOL res -48 272 R90 >=20 > >WINDOW 0 0 56 VBottom 2 >=20 > >WINDOW 3 35 66 VTop 2 >=20 > >SYMATTR InstName R2 >=20 > >SYMATTR Value 10k >=20 > >SYMBOL res 384 400 R180 >=20 > >WINDOW 0 36 76 Left 2 >=20 > >WINDOW 3 36 40 Left 2 >=20 > >SYMATTR InstName R3 >=20 > >SYMATTR Value 32 >=20 > >SYMBOL res 224 528 R180 >=20 > >WINDOW 0 36 76 Left 2 >=20 > >WINDOW 3 36 40 Left 2 >=20 > >SYMATTR InstName R4 >=20 > >SYMATTR Value 6.8 >=20 > >SYMBOL cap -176 272 R90 >=20 > >WINDOW 0 0 32 VBottom 2 >=20 > >WINDOW 3 32 32 VTop 2 >=20 > >SYMATTR InstName C1 >=20 > >SYMATTR Value 1=EF=BF=BD >=20 > >SYMBOL voltage -512 128 R0 >=20 > >WINDOW 123 0 0 Left 2 >=20 > >WINDOW 39 0 0 Left 2 >=20 > >SYMATTR InstName V1 >=20 > >SYMATTR Value 6 >=20 > >SYMBOL voltage -512 272 R0 >=20 > >WINDOW 123 0 0 Left 2 >=20 > >WINDOW 39 0 0 Left 2 >=20 > >SYMATTR InstName V2 >=20 > >SYMATTR Value 6 >=20 > >SYMBOL voltage -336 288 R0 >=20 > >WINDOW 123 24 124 Left 2 >=20 > >WINDOW 39 0 0 Left 2 >=20 > >WINDOW 3 38 72 Left 2 >=20 > >SYMATTR Value SINE(0 0.2 1e3) >=20 > >SYMATTR InstName V3 >=20 > >SYMBOL nmos4 160 80 R0 >=20 > >SYMATTR InstName M1 >=20 > >SYMATTR Value DN2540 >=20 > >SYMBOL nmos4 160 320 R0 >=20 > >SYMATTR InstName M2 >=20 > >SYMATTR Value DN2540 >=20 > >SYMBOL Opamps\\opamp2 32 96 R0 >=20 > >SYMATTR InstName U2 >=20 > >SYMATTR Value TL082 >=20 > >TEXT -536 496 Left 2 !.lib C:\\Program=20 >=20 > >Files\\LTC\\LTspiceIV\\lib\\mylib\\supertex.lib >=20 > >TEXT -536 464 Left 2 !.tran 0.1 startup uic >=20 > >TEXT -536 528 Left 2 !.include C:\\Program=20 >=20 > >Files\\LTC\\LTspiceIV\\lib\\mylib\\TL082.lib >=20 > > >=20 >=20 >=20 > LTspice doesn't like those last "TEXT" lines, complaining of a syntax >=20 > problem. >=20 >=20 >=20 > Anyone (everyone :-) more familiar with LTspice than me, how should >=20 > those library calls be corrected? >=20 > =09I'm guessing that is just the line break in "Program files" make it single lines and it should work (if you have the libs in the same p= lace) -Lasse
Reply by ●May 26, 20142014-05-26
[snip]> LTspice doesn't like those last "TEXT" lines, complaining of a syntax > > problem. > > > > Anyone (everyone :-) more familiar with LTspice than me, how should > > those library calls be corrected? > >I'm guessing that is just the line break in "Program files" make it single lines and it should work (if you have the libs in the same place) -Lasse I moved the lib files and get the same error. If I change the opamp to an LT1055 and delete the .include statement the simulation runs (the 3rd harmonic is -38 dB), so it would appear that the problem is with the TL082 subcircuit. Netlist of TL082 version follows. Version 4 SHEET 1 880 680 WIRE 0 144 -48 144 WIRE 160 160 64 160 WIRE 208 160 208 128 WIRE 0 176 -16 176 WIRE -16 208 -16 176 WIRE -512 240 -512 224 WIRE -512 240 -576 240 WIRE -576 256 -576 240 WIRE -512 288 -512 240 WIRE -240 288 -336 288 WIRE -144 288 -176 288 WIRE -48 288 -48 144 WIRE -48 288 -64 288 WIRE -16 288 -48 288 WIRE 208 288 208 176 WIRE 208 288 64 288 WIRE 368 288 208 288 WIRE -336 304 -336 288 WIRE 368 304 368 288 WIRE 208 320 208 288 WIRE 160 400 112 400 WIRE 208 400 208 368 WIRE 112 432 112 400 WIRE 208 432 208 416 FLAG -16 208 0 FLAG 368 384 0 FLAG -336 384 0 FLAG -576 256 0 FLAG -512 144 V+ FLAG 208 80 V+ FLAG 32 128 V+ FLAG -512 368 V- FLAG 32 192 V- FLAG 208 512 V- FLAG 112 432 V- FLAG 368 288 out FLAG -336 288 in SYMBOL res 80 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 50k SYMBOL res -48 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 35 66 VTop 2 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 384 400 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R3 SYMATTR Value 32 SYMBOL res 224 528 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R4 SYMATTR Value 6.8 SYMBOL cap -176 272 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1� SYMBOL voltage -512 128 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 6 SYMBOL voltage -512 272 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 6 SYMBOL voltage -336 288 R0 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 38 72 Left 2 SYMATTR Value SINE(0 0.2 1e3) SYMATTR InstName V3 SYMBOL nmos4 160 80 R0 SYMATTR InstName M1 SYMATTR Value DN2540 SYMBOL nmos4 160 320 R0 SYMATTR InstName M2 SYMATTR Value DN2540 SYMBOL Opamps\\opamp2 32 96 R0 SYMATTR InstName U2 SYMATTR Value TL082 TEXT -536 496 Left 2 !.lib C:\\myLTClib\\DN2540.lib TEXT -536 464 Left 2 !.tran 0.1 startup uic TEXT -536 528 Left 2 !.include C:\\myLTClib\\TL082.lib
