Forums

another PCB

Started by John Larkin April 2, 2014
This is layout iteration 18 of a new PCB layout, almost done. It's a
VME module, 48 channels of isolated digital input with front-end BIST.

https://dl.dropboxusercontent.com/u/53724080/PCBs/V280_18.jpg

There's no uP, just some state machines in the FPGA. 

I like the way the FPGA looks like a crab, with claws reaching out to
the circuits to the left. After The Brat had it all done, we had the
PCB design review and we made her move two traces into the FPGA, a
couple of bank VREF signals that we'd forgotten. We're lucky to have
escaped with our lives.

(We have three formal reviews: PDR, CDR, PCB)

We also had a big polymer aluminum cap on the output of the LTC
switcher brick up top. Customers have a habit of shearing these caps
off, especially ones near the edges of a board, so I replaced it with
five 22uF 1206 ceramics. Less ESR ripple anyhow.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

John Larkin <jlarkin@highlandtechnology.com> wrote:
> I like the way the FPGA looks like a crab, with claws reaching out to > the circuits to the left.
Too bad Realtek doesn't make FPGAs.
> After The Brat had it all done, we had the PCB design review and we > made her move two traces into the FPGA, a couple of bank VREF signals > that we'd forgotten. We're lucky to have escaped with our lives.
That's one advantage of CAD - the layout/drafting people no longer have a ready supply of compasses, triangles, X-Acto knives, and other implements of destruction, so asking for changes is slightly less hazardous. :)
> We also had a big polymer aluminum cap on the output of the LTC > switcher brick up top. Customers have a habit of shearing these caps > off, especially ones near the edges of a board, so I replaced it with > five 22uF 1206 ceramics. Less ESR ripple anyhow.
At a previous job, we had a 6U CompactPCI board (more or less the same size as VME), designed "by others", where they had pushed the power- supply stuff to one of the short edges of the board, in the corner. There were three surface-mount inductors in a row there, each about 15 mm square by 5 mm thick. The board had the audacity to not work if one of those inductors were gone. We quickly learned that when installing those boards, they needed to be started into the chassis at 90 +/- 0.001 degrees to the backplane, or else the inductor in the corner would hit the card guide and shear off. Another trick, which is CompactPCI specific, is the plastic keying plug you can put in the board and the backplane connectors. In theory, you shouldn't be able to get the connectors to mate, or get the card latches or retaining screws started, if the keying plug is wrong. In practice, some people just use a bigger hammer. The advanced version is to remove the keying plug ahead of time, install the board in the wrong slot, and then complain when it doesn't work. Related: on small boards that mount with standoffs, some designers are better than others at actually leaving clear space around the holes. I squished a transistor with the nut driver, but it must not have been important, because that CPU board still worked OK. Matt Roberds
On Thu, 3 Apr 2014 08:55:38 +0000 (UTC), mroberds@att.net wrote:

>John Larkin <jlarkin@highlandtechnology.com> wrote: >> I like the way the FPGA looks like a crab, with claws reaching out to >> the circuits to the left. > >Too bad Realtek doesn't make FPGAs. > >> After The Brat had it all done, we had the PCB design review and we >> made her move two traces into the FPGA, a couple of bank VREF signals >> that we'd forgotten. We're lucky to have escaped with our lives. > >That's one advantage of CAD - the layout/drafting people no longer have >a ready supply of compasses, triangles, X-Acto knives, and other >implements of destruction, so asking for changes is slightly less >hazardous. :) > >> We also had a big polymer aluminum cap on the output of the LTC >> switcher brick up top. Customers have a habit of shearing these caps >> off, especially ones near the edges of a board, so I replaced it with >> five 22uF 1206 ceramics. Less ESR ripple anyhow. > >At a previous job, we had a 6U CompactPCI board (more or less the same >size as VME), designed "by others", where they had pushed the power- >supply stuff to one of the short edges of the board, in the corner. >There were three surface-mount inductors in a row there, each about >15 mm square by 5 mm thick. The board had the audacity to not work if >one of those inductors were gone. We quickly learned that when >installing those boards, they needed to be started into the chassis at >90 +/- 0.001 degrees to the backplane, or else the inductor in the >corner would hit the card guide and shear off.
That's the problem, butterfingers putting boards into guides. In VME, the front panels of adjacent cards are component guillotines (off with their heads!) when a board is being loaded or, worse, removed. There could be some sort of plastic ramps to fend things off.
> >Another trick, which is CompactPCI specific, is the plastic keying plug >you can put in the board and the backplane connectors. In theory, you >shouldn't be able to get the connectors to mate, or get the card latches >or retaining screws started, if the keying plug is wrong. In practice, >some people just use a bigger hammer. The advanced version is to remove >the keying plug ahead of time, install the board in the wrong slot, and >then complain when it doesn't work.
Creative.
> >Related: on small boards that mount with standoffs, some designers are >better than others at actually leaving clear space around the holes. I >squished a transistor with the nut driver, but it must not have been >important, because that CPU board still worked OK.
Redundant design?
> >Matt Roberds
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
> >> >> Related: on small boards that mount with standoffs, some designers are >> better than others at actually leaving clear space around the holes. I >> squished a transistor with the nut driver, but it must not have been >> important, because that CPU board still worked OK. > > Redundant design? > >> >> Matt Roberds >
and we had an 18 layer design with multi standoffs... trouble is, the PCB designer forgot to relieve the internal layers around the fixing holes.... screwed in a couple of pillars and poof, the threads shorted out several layers down the hole!
On Thu, 03 Apr 2014 21:24:07 +0100, TTman <pcw1.cad@ntlworld.com>
wrote:

> >> >>> >>> Related: on small boards that mount with standoffs, some designers are >>> better than others at actually leaving clear space around the holes. I >>> squished a transistor with the nut driver, but it must not have been >>> important, because that CPU board still worked OK. >> >> Redundant design? >> >>> >>> Matt Roberds >> > >and we had an 18 layer design with multi standoffs... trouble is, the >PCB designer forgot to relieve the internal layers around the fixing >holes.... screwed in a couple of pillars and poof, the threads shorted >out several layers down the hole!
I thought that stuff was always handled with "keep outs". This is all supplied by our mechanical people and they're standard for various hardware types. Allowing the software to do its DRC checking makes things go much more smoothly. ;-)
On Thu, 03 Apr 2014 20:50:10 -0400, krw@attt.bizz wrote:

>On Thu, 03 Apr 2014 21:24:07 +0100, TTman <pcw1.cad@ntlworld.com> >wrote: > >> >>> >>>> >>>> Related: on small boards that mount with standoffs, some designers are >>>> better than others at actually leaving clear space around the holes. I >>>> squished a transistor with the nut driver, but it must not have been >>>> important, because that CPU board still worked OK. >>> >>> Redundant design? >>> >>>> >>>> Matt Roberds >>> >> >>and we had an 18 layer design with multi standoffs... trouble is, the >>PCB designer forgot to relieve the internal layers around the fixing >>holes.... screwed in a couple of pillars and poof, the threads shorted >>out several layers down the hole!
We've done that with pressed-in PEM fasteners. Not recently!
> >I thought that stuff was always handled with "keep outs". This is all >supplied by our mechanical people and they're standard for various >hardware types. Allowing the software to do its DRC checking makes >things go much more smoothly. ;-)
It's a good idea to have decently sized annular rings on all layers of a mounting hole pad stack. Bigger on the outer layers, to keep screw heads and washers and spacers from squashing traces, and enough on inner layers to avoid the screw thread thing. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote:
> On Thu, 3 Apr 2014 08:55:38 +0000 (UTC), mroberds@att.net wrote:
> In VME, the front panels of adjacent cards are component guillotines > (off with their heads!) when a board is being loaded or, worse, > removed.
On most of the boards at that job, the front panel was a lot taller than the stuff on the boards, so this didn't come up much. (Most of the front panels were 4 thingys high, where a thingy is the horziontal version of U, about 4 mm.) There were a couple of modules with tall components that would hit the adjacent front panel, though. Some of them were next to blank panels and it was often easier to remove the blank panel first and install it last.
> There could be some sort of plastic ramps to fend things off.
One strange thing on the CompactPCI cards: on the short sides, more or less underneath the card guides, there were long straight traces with no solder mask on them. One end of the trace was NC and the other went to a couple of 100k-ish resistors in series and then to board ground. I was told this was to get rid of static when inserting the boards. Does VME have anything like that? (Curiosity more than anything; I have no idea if those traces actually helped.)
>> I squished a transistor with the nut driver, but it must not have >> been important, because that CPU board still worked OK. > > Redundant design?
I think we just weren't using that circuit. IIRC it was a full x86 PC equivalent, so there were a lot of peripherals and stuff (parallel port, etc) that we weren't using. Matt Roberds
On Fri, 4 Apr 2014 04:41:38 +0000 (UTC), mroberds@att.net wrote:

>John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote: >> On Thu, 3 Apr 2014 08:55:38 +0000 (UTC), mroberds@att.net wrote: > >> In VME, the front panels of adjacent cards are component guillotines >> (off with their heads!) when a board is being loaded or, worse, >> removed. > >On most of the boards at that job, the front panel was a lot taller than >the stuff on the boards, so this didn't come up much. (Most of the >front panels were 4 thingys high, where a thingy is the horziontal >version of U, about 4 mm.) There were a couple of modules with tall >components that would hit the adjacent front panel, though. Some of >them were next to blank panels and it was often easier to remove the >blank panel first and install it last. > >> There could be some sort of plastic ramps to fend things off. > >One strange thing on the CompactPCI cards: on the short sides, more or >less underneath the card guides, there were long straight traces with no >solder mask on them. One end of the trace was NC and the other went to >a couple of 100k-ish resistors in series and then to board ground. I >was told this was to get rid of static when inserting the boards. Does >VME have anything like that? (Curiosity more than anything; I have no >idea if those traces actually helped.)
No, VME doesn't. -- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wed, 02 Apr 2014 16:35:51 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

> >This is layout iteration 18 of a new PCB layout, almost done. It's a >VME module, 48 channels of isolated digital input with front-end BIST. > >https://dl.dropboxusercontent.com/u/53724080/PCBs/V280_18.jpg > >There's no uP, just some state machines in the FPGA. > >I like the way the FPGA looks like a crab, with claws reaching out to >the circuits to the left. After The Brat had it all done, we had the >PCB design review and we made her move two traces into the FPGA, a >couple of bank VREF signals that we'd forgotten. We're lucky to have >escaped with our lives. > >(We have three formal reviews: PDR, CDR, PCB) > >We also had a big polymer aluminum cap on the output of the LTC >switcher brick up top. Customers have a habit of shearing these caps >off, especially ones near the edges of a board, so I replaced it with >five 22uF 1206 ceramics. Less ESR ripple anyhow.
The bare boards came in today. https://dl.dropboxusercontent.com/u/53724080/PCBs/V280_PCB.JPG We always ask for a "solder sample" board with each batch, which in theory could be a board with some defects. The board houses usually disfigure that board somehow, by scribbling on it (as in this example) or by punching a big hole in it. The Brat drew boxes around the channel pairs when she was doing the layout, and liked how it looks, so she left them there. -- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin <jlarkin@highlandtechnology.com> writes:

> On Wed, 02 Apr 2014 16:35:51 -0700, John Larkin > <jlarkin@highlandtechnology.com> wrote: > >> >>This is layout iteration 18 of a new PCB layout, almost done. It's a >>VME module, 48 channels of isolated digital input with front-end BIST. >> >>https://dl.dropboxusercontent.com/u/53724080/PCBs/V280_18.jpg >> >>There's no uP, just some state machines in the FPGA. >> >>I like the way the FPGA looks like a crab, with claws reaching out to >>the circuits to the left. After The Brat had it all done, we had the >>PCB design review and we made her move two traces into the FPGA, a >>couple of bank VREF signals that we'd forgotten. We're lucky to have >>escaped with our lives. >> >>(We have three formal reviews: PDR, CDR, PCB) >> >>We also had a big polymer aluminum cap on the output of the LTC >>switcher brick up top. Customers have a habit of shearing these caps >>off, especially ones near the edges of a board, so I replaced it with >>five 22uF 1206 ceramics. Less ESR ripple anyhow. > > > The bare boards came in today. > > https://dl.dropboxusercontent.com/u/53724080/PCBs/V280_PCB.JPG > > We always ask for a "solder sample" board with each batch, which in > theory could be a board with some defects. The board houses usually > disfigure that board somehow, by scribbling on it (as in this example) > or by punching a big hole in it.
Very nice! Do I take it that she is allowed to swap the FPGA pins around to get a nice layout? All manually routed (apart from the replication)?
> The Brat drew boxes around the channel pairs when she was doing the > layout, and liked how it looks, so she left them there.
Don't like that. -- John Devereux