Forums

a little filter

Started by John Larkin February 20, 2014

We make a box that can output a lot of fiberoptic logic signals, light
on/off. One existing mode is PWM, where frequency is 125 MHz/N, and
"on" resolution is 1 ns. I have a customer who needs a remote analog
signal, 0-1 volt, that he can update in a microsecond or two. He'd
like 10 bit resolution.

So I figured that an optical/electrical converter could drive a
lowpass filter at the far end, so I built him the filter to try. We
did a test board a while back, and we tossed some extra circuits onto
the layout, including a little filter board.

https://dl.dropboxusercontent.com/u/53724080/Circuits/Filters/Daniel_Sch.JPG

https://dl.dropboxusercontent.com/u/53724080/Circuits/Filters/Daniel_Filter.JPG

https://dl.dropboxusercontent.com/u/53724080/Circuits/Filters/Daniel_Step.JPG

Seems to work. I'm running at N=32, PWM frequency 3.9 MHz, which gives
us 256 step (8 bit) resolution. I can't get a lowpass filter design to
work at 512 steps/9 bits/2 MHz.

PWM-to-DC has awful dilemmas. To get N steps of resolution, you need a
lowpass filter that will settle to 1/N volts in the time budget, and
have p-p ripple about that same magnitude. That turns out to be awful,
an n-squared dilemma at best. It needs to be a Bessel filter, or it
will ring and wreck the settling time. Bessels let a lot of PWM ripple
leak through. Higher order filters reduce ripple some but add time
delay.

A better answer is PWM with some sort of ramp and s/h instead of the
lowpass, but that's a non-trivial design and a PCB layout. Even better
would be to hack the source FPGA to transmit a burst of digital data,
and have a decoder+DAC at the far end... again, a bunch of design.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Friday, 21 February 2014 09:35:22 UTC+11, John Larkin  wrote:
> We make a box that can output a lot of fiberoptic logic signals, light > on/off. One existing mode is PWM, where frequency is 125 MHz/N, and > "on" resolution is 1 ns. I have a customer who needs a remote analog > signal, 0-1 volt, that he can update in a microsecond or two. He'd > like 10 bit resolution.
<snipped rather unsophisticated filter>
> So I figured that an optical/electrical converter could drive a > lowpass filter at the far end, so I built him the filter to try. We > did a test board a while back, and we tossed some extra circuits onto > the layout, including a little filter board.
> PWM-to-DC has awful dilemmas. To get N steps of resolution, you need a > lowpass filter that will settle to 1/N volts in the time budget, and > have p-p ripple about that same magnitude. That turns out to be awful, > an n-squared dilemma at best. It needs to be a Bessel filter, or it > will ring and wreck the settling time. Bessels let a lot of PWM ripple > leak through. Higher order filters reduce ripple some but add time > delay.
You need Williams and Taylor's "Electronic Filter Design Handbook" http://www.amazon.com/Electronic-Handbook-Edition-McGraw-Hill-Handbooks/dp/0071471715 It is isn't cheap, but everybody here who knows what they are talking about swears by it. High order Bessell filters do have up to about four times the time delay of a first order filter, but the ripple attenuation goes up much more rapidly with the order of the filter. There are also equi-ripple variants of the pure Bessel filter. One can also choose the pulse width modulation pattern to minimise the lower frequency ripple components. Sigma Delta modulators have always exploited this since they were invented. My 1996 paper spelled out a less thorough-going approach optimised for a different situation - fewer (power-dissipating) switching transitions - and not as much minimisation of the lower frequency ripple content. Sloman A.W., Buggs P., Molloy J., and Stewart D. "long title" Measurement Science and Technology, 7 1653-64 -- Bill Sloman, Sydney
On Thursday, February 20, 2014 2:35:22 PM UTC-8, John Larkin wrote:
> ... >=20 > It needs to be a Bessel filter, or it > will ring and wreck the settling time.=20 > Bessels let a lot of PWM ripple leak=20 > through. Higher order filters reduce > ripple some but add time delay. >=20 > ...
I am not sure if you are asking something. =20 You're right that filter order increases the delay, ceteris paribus, and it= Bessel or Bessel-like helps to minimize ringing. But you seem to want a = low-pass filter, which a Bessel is quite nominally (and by accident: its pu= rpose is constant delay, not low-pass). I played with something that has 1.0 ms equi-ripple delay, that could be sc= aled. Other things are possible. If you want more rejection, some TX zeros = obviously "do something." Linear phase low-pass filter Equal ripple delay passband Low frequency delay =3D 1.000000 msec Upper passband edge frequency =3D 0.001000 MHz Delay ripple =3D18.022361 usec Passband edge frequency =3D 0.001000 MHz equal minima stop band with edge frequency=3D 0.001500 MHz multiplicity of zero at infinity =3D 2 number of finite transmission zero pairs =3D 2 overall filter degree =3D 6 transmission zeros real part imaginary part 0.0000000D+00 2.0999615D+03 0.0000000D+00 1.5476704D+03 1 +---R---+ 50.000000 ohm 2 | L 8.615928 mH 3 +---C---+ 3.325297 uF | .-+. 4 | L C 15.173470 mH res.frequency | `-+' 378.558212 nF 0.002100 MHz 5 +---C---+ 18.380877 uF | .-+. 6 | L C 12.409140 mH res.frequency | `-+' 852.200167 nF 0.001548 MHz 7 +---C---+ 3.091728 uF 9 +---R---+ 50.017324 ohm
On Thu, 20 Feb 2014 16:33:49 -0800 (PST), Simon S Aysdie <gwhite@ti.com> wrote:

>On Thursday, February 20, 2014 2:35:22 PM UTC-8, John Larkin wrote: >> ... >> >> It needs to be a Bessel filter, or it >> will ring and wreck the settling time. >> Bessels let a lot of PWM ripple leak >> through. Higher order filters reduce >> ripple some but add time delay. >> >> ... > > > >I am not sure if you are asking something.
It's a discussion group.
> >You're right that filter order increases the delay, ceteris paribus, and it Bessel or Bessel-like helps to minimize ringing. But you seem to want a low-pass filter, which a Bessel is quite nominally (and by accident: its purpose is constant delay, not low-pass).
Williams calls lowpass Bessels lowpass filters, and I do too. He says (sec 7.3 of 4e) that lowpass filters, including Bessels, are not the most efficient delay lines.
> >I played with something that has 1.0 ms equi-ripple delay, that could be scaled. Other things are possible. If you want more rejection, some TX zeros obviously "do something." > > Linear phase low-pass filter > Equal ripple delay passband > Low frequency delay = 1.000000 msec > Upper passband edge frequency = 0.001000 MHz > Delay ripple =18.022361 usec > Passband edge frequency = 0.001000 MHz > equal minima stop band with edge frequency= 0.001500 MHz > multiplicity of zero at infinity = 2 > number of finite transmission zero pairs = 2 > overall filter degree = 6 > transmission zeros > real part imaginary part > 0.0000000D+00 2.0999615D+03 > 0.0000000D+00 1.5476704D+03 > > 1 +---R---+ 50.000000 ohm > 2 | L 8.615928 mH > 3 +---C---+ 3.325297 uF > | .-+. > 4 | L C 15.173470 mH res.frequency > | `-+' 378.558212 nF 0.002100 MHz > 5 +---C---+ 18.380877 uF > | .-+. > 6 | L C 12.409140 mH res.frequency > | `-+' 852.200167 nF 0.001548 MHz > 7 +---C---+ 3.091728 uF > 9 +---R---+ 50.017324 ohm
I Spiced that. It's down 3 dB at 393 Hz, so I can scale its frequency response about 1000:1 and compare it to my 350K 3-pole Bessel. Your scaled 0.1% settling time is about 3.8 us, compared to about 2.7 for the Bessel. Those added stages add delay. The big difference is of course frequency rolloff; my 3p Bessel is -60 dB at 4.8 MHz, and yours is -60 at the equivalent of 1.4 MHz. It looks like sort of a wash. Your filter could allow me to PWM at a lower frequency before the ripple gets big, improving resolution, but the added settling time compromises the improvement. The advantage of the 3p Bessel is that it's easy to make from a few available parts; higher-order filters require multiple inductor values with, often, inconvenient ratios. Like I said, PWM is awful. The more complex filter squeezes out maybe one more bit of analog signal resolution. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
On Thursday, February 20, 2014 2:35:22 PM UTC-8, John Larkin wrote:
> We make a box that can output a lot of fiberoptic logic signals, light > > on/off. One existing mode is PWM, where frequency is 125 MHz/N, and > > "on" resolution is 1 ns. I have a customer who needs a remote analog > > signal, 0-1 volt, that he can update in a microsecond or two. He'd > > like 10 bit resolution. > > ,,,
Do you have to use simple PWM? If you encode the transmitted signal with a sigma-delta modulator the ripple frequency will be much higher for most codes. There will unfortunately be some values that will still give the same ripple as PWM. kevin
On Thu, 20 Feb 2014 20:30:55 -0800 (PST), kevin93 <kevin@whitedigs.com> wrote:

>On Thursday, February 20, 2014 2:35:22 PM UTC-8, John Larkin wrote: >> We make a box that can output a lot of fiberoptic logic signals, light >> >> on/off. One existing mode is PWM, where frequency is 125 MHz/N, and >> >> "on" resolution is 1 ns. I have a customer who needs a remote analog >> >> signal, 0-1 volt, that he can update in a microsecond or two. He'd >> >> like 10 bit resolution. >> >> ,,, > >Do you have to use simple PWM? > >If you encode the transmitted signal with a sigma-delta modulator the ripple frequency will be much higher for most codes. There will unfortunately be some values that will still give the same ripple as PWM. > >kevin
I don't really understand delta-sigma dacs. The density of rising and falling edges will vary continuously, and it would take extreme rise/fall speed and symmetry to deliver an accurate average value. I suspect that real d-s dacs use some sort of charge dispensing tricks, rather than just lowpass filtering a rail-to-rail logic swing. But I certainly can't process 1 ns pulses. I wonder what d-s clock rate it would take to get, say, a 10-bit equivalent ADC that settles in a couple of microseconds. It would still have the existing filtering problem, namely good rolloff (to kill the d-s noise, similar to killing the PWM carrier) but fast step response settling. Audio dacs don't have that same problem, so can use agressive filters. The PWM facility already exists in our FPGA. If we go in and redesign things, we may as well just pump out a serial digital data stream, and use a DAC on the other end. The issue then becomes how best to encode it. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
On a sunny day (Thu, 20 Feb 2014 20:51:26 -0800) it happened John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in
<1vldg9dkk6oev3gifg7g6acad23vhkih5h@4ax.com>:

>But I certainly can't process 1 ns pulses. I wonder what d-s clock rate it would >take to get, say, a 10-bit equivalent ADC that settles in a couple of >microseconds. It would still have the existing filtering problem, namely good >rolloff (to kill the d-s noise, similar to killing the PWM carrier) but fast >step response settling. Audio dacs don't have that same problem, so can use >agressive filters. > >The PWM facility already exists in our FPGA. If we go in and redesign things, we >may as well just pump out a serial digital data stream, and use a DAC on the >other end. The issue then becomes how best to encode it.
How about a shift register with a R2R network at the other end? So end the 'byte' serially. I have done R2R on CMOS output, it works, that vertical white thing is one: http://panteltje.com/pub/z80/soundcard_top.jpg Circuit diagram, IC9 (right) is the R2R ladder: http://panteltje.com/panteltje/z80/system14/diagrams/sound-1.jpg There is a simple filter in there too.. Should work for highter frequencies than 3.5 kHz too..
On Friday, 21 February 2014 19:05:12 UTC+11, Jan Panteltje  wrote:
> On a sunny day (Thu, 20 Feb 2014 20:51:26 -0800) it happened John Larkin=
=20
> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in=20 > <1vldg9dkk6oev3gifg7g6acad23vhkih5h@4ax.com>: =20 > >But I certainly can't process 1 ns pulses. I wonder what d-s clock rate =
it =20
> >would take to get, say, a 10-bit equivalent ADC that settles in a couple=
of=20
> >microseconds. It would still have the existing filtering problem, namely=
=20
> >good rolloff (to kill the d-s noise, similar to killing the PWM carrier)=
but=20
> >fast step response settling. Audio dacs don't have that same problem, so=
=20
> >can use aggressive filters. > >=20 > >The PWM facility already exists in our FPGA. If we go in and redesign =
=20
> >things, we may as well just pump out a serial digital data stream, and u=
se =20
> >a DAC on the other end. The issue then becomes how best to encode it. > =20 > How about a shift register with a R2R network at the other end?=20 > So end the 'byte' serially. > =20 > I have done R2R on CMOS output, it works, that vertical white thing is on=
e: <snip> None of that makes much sense to me, in this context. It did set me thinking though. John Larkin's filter problem is that he want= s a complex and hard to realise fast-settling filter, at a frequency where = reactive components are far from ideal. If he used a clocked shift register as a digital delay line with a resistor= on every tap, and ran the other ends of the resistors into a summing junct= ion, he's built an FIR filter, and 0.1% resistors on the E96 grid can give = you a high-order filter characteristic with relatively little effort (and b= oard space). Finite-impulse response filters have very good transient behaviour. --=20 Bill Sloman, Sydney
> If he used a clocked shift register as a digital delay line with a resist=
or on every tap, and ran the other ends of the resistors into a summing jun= ction, he's built an FIR filter, and 0.1% resistors on the E96 grid can giv= e you a high-order filter characteristic with relatively little effort (and= board space).
>=20 >=20 >=20 > Finite-impulse response filters have very good transient behaviour. >=20 >=20 >=20 > --=20 >=20 > Bill Sloman, Sydney
As a frank newbie at this, the resistors seem to make sense...Are there eno= ugh digital output lines on the FPGA to do it directly, by switching a resi= stor network?
On a sunny day (Fri, 21 Feb 2014 03:38:43 -0800 (PST)) it happened Bill Sloman
<bill.sloman@gmail.com> wrote in
<a7de5c3b-bfa2-43d0-b0e8-6e4491875b4a@googlegroups.com>:

>On Friday, 21 February 2014 19:05:12 UTC+11, Jan Panteltje wrote: >> On a sunny day (Thu, 20 Feb 2014 20:51:26 -0800) it happened John Larkin= > >> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in >> <1vldg9dkk6oev3gifg7g6acad23vhkih5h@4ax.com>: >> >But I certainly can't process 1 ns pulses. I wonder what d-s clock rate = >it >> >would take to get, say, a 10-bit equivalent ADC that settles in a couple= > of >> >microseconds. It would still have the existing filtering problem, namely= > >> >good rolloff (to kill the d-s noise, similar to killing the PWM carrier)= > but >> >fast step response settling. Audio dacs don't have that same problem, so= > >> >can use aggressive filters. >> > >> >The PWM facility already exists in our FPGA. If we go in and redesign = > >> >things, we may as well just pump out a serial digital data stream, and u= >se >> >a DAC on the other end. The issue then becomes how best to encode it. >> >> How about a shift register with a R2R network at the other end? >> So end the 'byte' serially. >> >> I have done R2R on CMOS output, it works, that vertical white thing is on= >e: > ><snip> > >None of that makes much sense to me, in this context.
Well I should have read it better, I think just go serial some format and DAC (that could be R2R). FPGAs have these very high clock speed outputs, soo, and that is some sort of standard, but I never worked with that, Resistors work into the GHz very nicely. PWM sucks for high speeds and high accuracy. But he was talking about 'a few us', so any fast UART sort of thing, clock recovery with some flops or flips, done that, and then only filter below Niquist /2, shift register with buffer works too, 10 bits maybe, but why not. Trimpots :-) No difficult filters...
>It did set me thinking though. John Larkin's filter problem is that he want= >s a complex and hard to realise fast-settling filter, at a frequency where = >reactive components are far from ideal. > >If he used a clocked shift register as a digital delay line with a resistor= > on every tap, and ran the other ends of the resistors into a summing junct= >ion, he's built an FIR filter, and 0.1% resistors on the E96 grid can give = >you a high-order filter characteristic with relatively little effort (and b= >oard space). > >Finite-impulse response filters have very good transient behaviour.
Yea, I think I would like to hear what it is used for, or at least what sort of speeds and accuracy are needed.