Forums

FPGA temperature measurement

Started by John Larkin August 29, 2013

We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To
measure actual die temperature, we built a 19-stage ring oscillator,
followed by a divide-by-16 ripple counter, and brought that out.

The heat source is the FPGA itself: we just clocked every available
flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the
top of the BGA package, and here's what we got:

https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg


We can now use that curve (line, actually!) to evaluate various heat
sinking options, for both this chip and the entire board.

The equivalent prop delay per CLB seems to be about 350 ps. The prop
delay slope is about 0.1% per degree C.


-- 

John Larkin         Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation
On 8/29/2013 5:44 PM, John Larkin wrote:
> > > We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To > measure actual die temperature, we built a 19-stage ring oscillator, > followed by a divide-by-16 ripple counter, and brought that out. > > The heat source is the FPGA itself: we just clocked every available > flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the > top of the BGA package, and here's what we got: > > https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg > > > We can now use that curve (line, actually!) to evaluate various heat > sinking options, for both this chip and the entire board. > > The equivalent prop delay per CLB seems to be about 350 ps. The prop > delay slope is about 0.1% per degree C. > >
Cute graph. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 USA +1 845 480 2058 hobbs at electrooptical dot net http://electrooptical.net
On Thu, 29 Aug 2013 20:33:30 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 8/29/2013 5:44 PM, John Larkin wrote: >> >> >> We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To >> measure actual die temperature, we built a 19-stage ring oscillator, >> followed by a divide-by-16 ripple counter, and brought that out. >> >> The heat source is the FPGA itself: we just clocked every available >> flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the >> top of the BGA package, and here's what we got: >> >> https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg >> >> >> We can now use that curve (line, actually!) to evaluate various heat >> sinking options, for both this chip and the entire board. >> >> The equivalent prop delay per CLB seems to be about 350 ps. The prop >> delay slope is about 0.1% per degree C. >> >> >Cute graph. > >Cheers > >Phil Hobbs
I had a minion photograph my whiteboard data and type it into Excel. I don't do Excel. Being now calibrated, I stuck a short pin-fin heat sink on top of the FPGA with some grease, and the chip temp dropped 4C. A tall pin-fin dropped it 4C. A 0.7" square of 0.062 thick aluminum, greasy-stuck to the top, dropped the chip temp 4C. Neat! -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On 8/29/2013 9:14 PM, John Larkin wrote:
> On Thu, 29 Aug 2013 20:33:30 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 8/29/2013 5:44 PM, John Larkin wrote: >>> >>> >>> We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To >>> measure actual die temperature, we built a 19-stage ring oscillator, >>> followed by a divide-by-16 ripple counter, and brought that out. >>> >>> The heat source is the FPGA itself: we just clocked every available >>> flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the >>> top of the BGA package, and here's what we got: >>> >>> https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg >>> >>> >>> We can now use that curve (line, actually!) to evaluate various heat >>> sinking options, for both this chip and the entire board. >>> >>> The equivalent prop delay per CLB seems to be about 350 ps. The prop >>> delay slope is about 0.1% per degree C. >>> >>> >> Cute graph. >> >> Cheers >> >> Phil Hobbs > > I had a minion photograph my whiteboard data and type it into Excel. I > don't do Excel. > > Being now calibrated, I stuck a short pin-fin heat sink on top of the > FPGA with some grease, and the chip temp dropped 4C. A tall pin-fin > dropped it 4C. A 0.7" square of 0.062 thick aluminum, greasy-stuck to > the top, dropped the chip temp 4C. > > Neat! > >
Suggesting that the main mechanism is helping transport heat to the leads (or the more distant solder balls), rather than to the air. Pin fin heatsinks are a crock. You don't get any more surface area than a parallel-fin design, and all the discontinuities interfere with the airflow very badly. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 USA +1 845 480 2058 hobbs at electrooptical dot net http://electrooptical.net
On Thu, 29 Aug 2013 21:39:28 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 8/29/2013 9:14 PM, John Larkin wrote: >> On Thu, 29 Aug 2013 20:33:30 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 8/29/2013 5:44 PM, John Larkin wrote: >>>> >>>> >>>> We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To >>>> measure actual die temperature, we built a 19-stage ring oscillator, >>>> followed by a divide-by-16 ripple counter, and brought that out. >>>> >>>> The heat source is the FPGA itself: we just clocked every available >>>> flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the >>>> top of the BGA package, and here's what we got: >>>> >>>> https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg >>>> >>>> >>>> We can now use that curve (line, actually!) to evaluate various heat >>>> sinking options, for both this chip and the entire board. >>>> >>>> The equivalent prop delay per CLB seems to be about 350 ps. The prop >>>> delay slope is about 0.1% per degree C. >>>> >>>> >>> Cute graph. >>> >>> Cheers >>> >>> Phil Hobbs >> >> I had a minion photograph my whiteboard data and type it into Excel. I >> don't do Excel. >> >> Being now calibrated, I stuck a short pin-fin heat sink on top of the >> FPGA with some grease, and the chip temp dropped 4C. A tall pin-fin >> dropped it 4C. A 0.7" square of 0.062 thick aluminum, greasy-stuck to >> the top, dropped the chip temp 4C. >> >> Neat! >> >> > >Suggesting that the main mechanism is helping transport heat to the >leads (or the more distant solder balls), rather than to the air.
Right. It spreads the heat laterally from the hot spot in the center of the package. So, why didn't Altera do that for me?
> >Pin fin heatsinks are a crock. You don't get any more surface area than >a parallel-fin design, and all the discontinuities interfere with the >airflow very badly.
But I can buy one with a thick flat base and peel-off acrylic sticky on the bottom. The pin-fins are just for show. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On 8/29/2013 9:45 PM, John Larkin wrote:
> On Thu, 29 Aug 2013 21:39:28 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 8/29/2013 9:14 PM, John Larkin wrote: >>> On Thu, 29 Aug 2013 20:33:30 -0400, Phil Hobbs >>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>> >>>> On 8/29/2013 5:44 PM, John Larkin wrote: >>>>> >>>>> >>>>> We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To >>>>> measure actual die temperature, we built a 19-stage ring oscillator, >>>>> followed by a divide-by-16 ripple counter, and brought that out. >>>>> >>>>> The heat source is the FPGA itself: we just clocked every available >>>>> flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the >>>>> top of the BGA package, and here's what we got: >>>>> >>>>> https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg >>>>> >>>>> >>>>> We can now use that curve (line, actually!) to evaluate various heat >>>>> sinking options, for both this chip and the entire board. >>>>> >>>>> The equivalent prop delay per CLB seems to be about 350 ps. The prop >>>>> delay slope is about 0.1% per degree C. >>>>> >>>>> >>>> Cute graph. >>>> >>>> Cheers >>>> >>>> Phil Hobbs >>> >>> I had a minion photograph my whiteboard data and type it into Excel. I >>> don't do Excel. >>> >>> Being now calibrated, I stuck a short pin-fin heat sink on top of the >>> FPGA with some grease, and the chip temp dropped 4C. A tall pin-fin >>> dropped it 4C. A 0.7" square of 0.062 thick aluminum, greasy-stuck to >>> the top, dropped the chip temp 4C. >>> >>> Neat! >>> >>> >> >> Suggesting that the main mechanism is helping transport heat to the >> leads (or the more distant solder balls), rather than to the air. > > Right. It spreads the heat laterally from the hot spot in the center of the > package. So, why didn't Altera do that for me? > > >> >> Pin fin heatsinks are a crock. You don't get any more surface area than >> a parallel-fin design, and all the discontinuities interfere with the >> airflow very badly. > > But I can buy one with a thick flat base and peel-off acrylic sticky on the > bottom. The pin-fins are just for show. > >
It would be amusing to calculate how thick the aluminum has to be before the sticky stuff dominates the thermal conduction. My guess is about 10 mils. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 USA +1 845 480 2058 hobbs at electrooptical dot net http://electrooptical.net
Neato!

Say, how's the voltage coefficient on that, with respect to Vcore I 
suppose?  Would be good for calculating how much ripple it can tolerate.

Tim

-- 
Deep Friar: a very philosophical monk.
Website: http://seventransistorlabs.com

"John Larkin" <jlarkin@highlandtechnology.com> wrote in message 
news:s9fv199t3h9qtmbjrcmnkfe4dlqrv60tlm@4ax.com...
> > > We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To > measure actual die temperature, we built a 19-stage ring oscillator, > followed by a divide-by-16 ripple counter, and brought that out. > > The heat source is the FPGA itself: we just clocked every available > flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the > top of the BGA package, and here's what we got: > > https://dl.dropboxusercontent.com/u/53724080/Thermal/R2_Temp_Cal.jpg > > > We can now use that curve (line, actually!) to evaluate various heat > sinking options, for both this chip and the entire board. > > The equivalent prop delay per CLB seems to be about 350 ps. The prop > delay slope is about 0.1% per degree C. > > > -- > > John Larkin Highland Technology, Inc > > jlarkin at highlandtechnology dot com > http://www.highlandtechnology.com > > Precision electronic instrumentation > Picosecond-resolution Digital Delay and Pulse generators > Custom laser drivers and controllers > Photonics and fiberoptic TTL data links > VME thermocouple, LVDT, synchro acquisition and simulation
On Thu, 29 Aug 2013 22:47:11 -0500, "Tim Williams" <tmoranwms@charter.net>
wrote:

>Neato! > >Say, how's the voltage coefficient on that, with respect to Vcore I >suppose? Would be good for calculating how much ripple it can tolerate. > >Tim
Vcore comes from an LM1117 with the ADJ pin grounded, so it's not really easy to twiddle. I might if I'm ever feeling energetic. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Generally diode characterization is how you measure die temperature. [I 
make it a point not to look at stuff on drop box. I don't trust it.]

I can document the procedure, but I'm sure it is on the internet somewhere.
On Thu, 29 Aug 2013 23:23:46 -0700, miso <miso@sushi.com> wrote:

>Generally diode characterization is how you measure die temperature.
Not me! The ring oscillator lets us just scope-probe a connector pin to get FPGA temperature, and we can/might build a frequency counter into the design so we can remotely read chip temp on all 16 boxes in the system. [I
>make it a point not to look at stuff on drop box. I don't trust it.]
Do you refuse to view any jpeg image that's hosted by Amazon? -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators