Forums

High res PWMs

Started by Phil Hobbs August 29, 2013
Hi, all,

I've been working on an automatically-tweaked noise canceller design 
with my trusty code and layout Sherpas-in-training (my son and my 
younger daughter).

I need about 10 slow but high resolution DAC outputs for the tweaks, and 
I was thinking about using PWMs run from the LPC1769 processor.

I can close the loop on them with an on-board delta-sigma ADC (the 
AD7708 or maybe AD7718).

I'd need some level shifting and stuff to make the required voltage 
ranges in any case, so the complexity isn't that different.

Suggestions?  Pitfalls to beware of?

Cheers

Phil Hobbs


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> writes:

> Hi, all, > > I've been working on an automatically-tweaked noise canceller design > with my trusty code and layout Sherpas-in-training (my son and my > younger daughter). > > I need about 10 slow but high resolution DAC outputs for the tweaks, > and I was thinking about using PWMs run from the LPC1769 processor. > > I can close the loop on them with an on-board delta-sigma ADC (the > AD7708 or maybe AD7718). > > I'd need some level shifting and stuff to make the required voltage > ranges in any case, so the complexity isn't that different. > > Suggestions? Pitfalls to beware of?
Well, I spent far too long trying to figure out the cause of my grossly non-linear PWM, before truly comprehending the difference between a duty cycle and an on/off time ratio. :) If you do a google search for "agree that I am the superior theoretician" ...then you will find a nice thread about precision PWM! :) James Arthur had a clever arrangement for cancelling the non-linearity from synchronous supply ripple. But you get to read back the result and correct, seems like cheating really. -- John Devereux
"Phil Hobbs" <pcdhSpamMeSenseless@electrooptical.net> wrote in message 
news:kvo3bl$t0d$1@dont-email.me...
> Hi, all, > > I've been working on an automatically-tweaked noise canceller design with > my trusty code and layout Sherpas-in-training (my son and my younger > daughter). > > I need about 10 slow but high resolution DAC outputs for the tweaks, and I > was thinking about using PWMs run from the LPC1769 processor. > > I can close the loop on them with an on-board delta-sigma ADC (the AD7708 > or maybe AD7718). > > I'd need some level shifting and stuff to make the required voltage ranges > in any case, so the complexity isn't that different. > > Suggestions? Pitfalls to beware of? > > Cheers > > Phil Hobbs >
To ease the problem of output filtering when using high resolution, have you considered using pulse density modulation instead? That way you can spread the required pulse width more evenly over the whole PWM cycle time and so remove the major low frequency components before filtering. Andy
On Thu, 29 Aug 2013 13:24:57 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>Hi, all, > >I've been working on an automatically-tweaked noise canceller design >with my trusty code and layout Sherpas-in-training (my son and my >younger daughter).
Daughters doing PCB layout? Is that really a good idea?
> >I need about 10 slow but high resolution DAC outputs for the tweaks, and >I was thinking about using PWMs run from the LPC1769 processor. > >I can close the loop on them with an on-board delta-sigma ADC (the >AD7708 or maybe AD7718).
What kind of resolution and speed do you need? The bummer with PWM is that the output frequency gets really low as the resolution increases, so you need a heroic lowpass filter to take the ripple out. It's an n-squared dilemma. Closing the loop might have interesting dynamics. Coarse and fine summing might be interesting, to keep the frequency up. But that would need 20 PWM outputs. How about a few quad SPI DACs? -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
"Andy Bartlett" <abartlett@nospam.net> writes:

> "Phil Hobbs" <pcdhSpamMeSenseless@electrooptical.net> wrote in message > news:kvo3bl$t0d$1@dont-email.me... >> Hi, all, >> >> I've been working on an automatically-tweaked noise canceller design with >> my trusty code and layout Sherpas-in-training (my son and my younger >> daughter). >> >> I need about 10 slow but high resolution DAC outputs for the tweaks, and I >> was thinking about using PWMs run from the LPC1769 processor. >> >> I can close the loop on them with an on-board delta-sigma ADC (the AD7708 >> or maybe AD7718). >> >> I'd need some level shifting and stuff to make the required voltage ranges >> in any case, so the complexity isn't that different. >> >> Suggestions? Pitfalls to beware of? >> >> Cheers >> >> Phil Hobbs >> > > To ease the problem of output filtering when using high resolution, have you > considered using pulse density modulation instead? That way you can spread > the required pulse width more evenly over the whole PWM cycle time and so > remove the major low frequency components before filtering.
Our own Tim Wescot did an article about this I think: <http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-techniques-extend-DAC-resolution> Then there is the approach of merging coarse and fine PWM channels. -- John Devereux
On 8/29/2013 12:24 PM, Phil Hobbs wrote:
> Hi, all, > > I've been working on an automatically-tweaked noise canceller design > with my trusty code and layout Sherpas-in-training (my son and my > younger daughter). > > I need about 10 slow but high resolution DAC outputs for the tweaks, and > I was thinking about using PWMs run from the LPC1769 processor.
Define "slow". Define "high resolution"
> I can close the loop on them with an on-board delta-sigma ADC (the > AD7708 or maybe AD7718). > > I'd need some level shifting and stuff to make the required voltage > ranges in any case, so the complexity isn't that different. > > Suggestions? Pitfalls to beware of?
It depends. PWM has several inherent problems such as dynamic nonlinearity, direct impact of clock jitter, and inaccuracies in the switch timing. Do careful estimate of those effects before getting to schematic. Rule of thumb: PWM rate more then x20 bandwidth of the signal; then, most of nonlinear effects could be ignored up to 0.1% accuracy. Vladimir Vassilevsky DSP and Mixed Signal Designs www.abvolt.com
"John Larkin" <jlarkin@highlandtechnology.com> wrote in message 
news:0r6v19h26iajeasobeemljknia2rmc9v5f@4ax.com...
> Closing the loop might have interesting dynamics.
S-D with a different DAC -- same thing in the end. Tim -- Deep Friar: a very philosophical monk. Website: http://seventransistorlabs.com
On 8/29/2013 3:12 PM, John Larkin wrote:
> On Thu, 29 Aug 2013 13:24:57 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> Hi, all, >> >> I've been working on an automatically-tweaked noise canceller design >> with my trusty code and layout Sherpas-in-training (my son and my >> younger daughter). > > Daughters doing PCB layout? Is that really a good idea? > >> >> I need about 10 slow but high resolution DAC outputs for the tweaks, and >> I was thinking about using PWMs run from the LPC1769 processor. >> >> I can close the loop on them with an on-board delta-sigma ADC (the >> AD7708 or maybe AD7718). > > What kind of resolution and speed do you need? > > The bummer with PWM is that the output frequency gets really low as > the resolution increases, so you need a heroic lowpass filter to take > the ripple out. It's an n-squared dilemma. Closing the loop might have > interesting dynamics. > > Coarse and fine summing might be interesting, to keep the frequency > up. But that would need 20 PWM outputs. > > How about a few quad SPI DACs? > >
I'm using a 120 MHz processor, and the timers can run right off the CPU clock, so at 16 bits I'm looking at 1.8 kHz. I took Tim's suggestion about the delta-sigma last time I used a PWM, and it works great. If I run 14 bits and do a first-order delta-sigma extension by another 8 bits, that's 7.3 kHz, still reasonable for implementing the delta-sigma in the timer ISR. A two-section RC filter with 10 ms time constants will roll off the ripple by about 100 dB. The CPU board is separate because I'm trying to keep this in a 1U Eurocard sort of format, and my layout person is a beginner. I do have SPI on the analogue board, but I'm resisting using dedicated DACs because they cost a fair amount when you need 10 channels at high resolution. I'm planning to get rid of the processor VDD variation by sending the PWMs to a 74HCT04 on the analogue board, and checking the two critical adjustments (offset voltage and current) using a couple of channels of an AD7708 or 7718 delta-sigma. Version 1.0 of this box is going to _look_ very nearly all-analogue. It'll just have three photodiodes, power, two BNCs on the back, and a slide switch to go from linear mode to spectroscopy mode (fast log only)...plus this magic button that you press when you want it to adjust itself specifically to your current operating conditions. The tweaking will be done based on calibration tables that the box generates for itself on the test stand, so in the field it's mostly slow and open-loop. I've been doing a lot of thinking about how you'd put the entire calibration setup into the box, but I haven't come up with a scheme that I like. Generating modulated light for three photodiodes, that has to have adjustable ratios and still remain perfectly correlated to a part in 30000 over a wide frequency band is a fairly hard problem. Just using 3 LEDs is a non-starter. I've been trying to get samples of electrochromic glass to see if I can do it optically on the cheap, but without great success so far. Bouncing the light off a nematic LCD is another possibility, and I suppose it would be possible to do some motorized thing, but, well, blech. (My code guy wants to be able to put the display and controls in a separate box eventually. For a product that has to go in the guts of somebody's optical system, a remote interface box is pretty useful, but it's a bridge too far for V1.0.) Since this is about 50% teaching vehicle, it may or may not work the first time round. I'm also teaching myself by putting in a lot of new tweaking ideas, some of which may also not work. (They simulate well, but that doesn't tell you too much when building noise cancellers.) Fun stuff. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 USA +1 845 480 2058 hobbs at electrooptical dot net http://electrooptical.net
On 8/29/2013 2:58 PM, John Devereux wrote:
> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> writes: > >> Hi, all, >> >> I've been working on an automatically-tweaked noise canceller design >> with my trusty code and layout Sherpas-in-training (my son and my >> younger daughter). >> >> I need about 10 slow but high resolution DAC outputs for the tweaks, >> and I was thinking about using PWMs run from the LPC1769 processor. >> >> I can close the loop on them with an on-board delta-sigma ADC (the >> AD7708 or maybe AD7718). >> >> I'd need some level shifting and stuff to make the required voltage >> ranges in any case, so the complexity isn't that different. >> >> Suggestions? Pitfalls to beware of? > > Well, I spent far too long trying to figure out the cause of my grossly > non-linear PWM, before truly comprehending the difference between a duty > cycle and an on/off time ratio. :) > > If you do a google search for > > "agree that I am the superior theoretician" > > ...then you will find a nice thread about precision PWM! :) > > James Arthur had a clever arrangement for cancelling the non-linearity > from synchronous supply ripple. > > But you get to read back the result and correct, seems like cheating > really. > >
I hadn't forgotten. ;) I was mostly wondering about vaguely the sort of stuff that Vladimir was talking about, i.e. second-order sorts of things that don't exist in the frictionless spherical cow world. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 USA +1 845 480 2058 hobbs at electrooptical dot net http://electrooptical.net
On 8/29/2013 4:17 PM, Phil Hobbs wrote:
> On 8/29/2013 3:12 PM, John Larkin wrote:
> I'm using a 120 MHz processor, and the timers can run right off the CPU > clock, so at 16 bits I'm looking at 1.8 kHz.
Not quite so simple.
> If I run 14 bits and do a first-order delta-sigma extension by another 8 > bits, that's 7.3 kHz, still reasonable for implementing the delta-sigma > in the timer ISR.
Did you check the numbers? Delta sigma extension is not so straightforward for PWM. Unlike PCM, the PWM is nonlinear. Shaped noise would be smeared back into the band of interest.
> I'm planning to get rid of the processor VDD variation by > sending the PWMs to a 74HCT04 on the analogue board,
Check the numbers first. CPU clock jitter would be added into your signal also, as well as Vdd noise divided by slew rate. Vladimir Vassilevsky DSP and Mixed Signal Designs www.abvolt.com