On 4/20/2013 8:37 PM, John Larkin wrote:> My ideal computer would have one CPU that's just the OS, and a hundred or so > assignable cores, one for each device, file system, program, or thread. The OS > would be a few thousand lines of code, if that. With serious hardware > protection, it would be totally virus/trojan/crash immune.Utter nonsense. N cores means N^2 interfaces with associated version hell. As for protection, is not technical problem; it is paradigm problem. Vladimir Vassilevsky DSP and Mixed Signal Designs www.abvolt.com
What's Your Favorite Processor on an FPGA?
Started by ●April 20, 2013
Reply by ●April 21, 20132013-04-21
Reply by ●April 21, 20132013-04-21
On Sun, 21 Apr 2013 08:32:44 -0500, Vladimir Vassilevsky <nospam@nowhere.com> wrote:>On 4/20/2013 8:37 PM, John Larkin wrote: > >> My ideal computer would have one CPU that's just the OS, and a hundred or so >> assignable cores, one for each device, file system, program, or thread. The OS >> would be a few thousand lines of code, if that. With serious hardware >> protection, it would be totally virus/trojan/crash immune. > > >Utter nonsense. > >N cores means N^2 interfaces with associated version hell.Better than having all N processes in the same memory space. Much better.>As for protection, is not technical problem; it is paradigm problem.The architecture that I propose could have absolute hardware sandboxing of any process, even drivers and things that can do DMA. Each processor would have memory management - loaded by the OS - that knows the difference between code, data, and stack. The OS would be tiny, absolutely protected, known reliable. Just note all the things that Wintel did wrong, and don't do that. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Reply by ●April 21, 20132013-04-21
On Sun, 21 Apr 2013 08:23:37 -0500, Vladimir Vassilevsky <nospam@nowhere.com> wrote:>On 4/20/2013 5:42 PM, rickman wrote: >> I have been working on designs of processors for FPGAs for quite a >> while. I have looked at the uBlaze, the picoBlaze, the NIOS, two from >> Lattice and any number of open source processors. Many of the open >> source designs were stack processors since they tend to be small and >> efficient in an FPGA. J1 is one I had pretty much missed until lately. >> It is fast and small and looks like it wasn't too hard to design >> (although looks may be deceptive), I'm impressed. There is also the b16 >> from Bernd Paysan, the uCore, the ZPU and many others. >> >> Lately I have been looking at a hybrid approach which combines features >> of addressing registers in order to access parameters of a stack CPU. It >> looks interesting. >> >> Anyone else here doing processor designs on FPGAs? >> > >Soft core is fun thing to do, but otherwise I see no use. >Except for very few special applications, standalone processor is better >then FPGA soft core in every point, especially the price. > >Vladimir Vassilevsky >DSP and Mixed Signal Designs >www.abvolt.comThe annoying thing is the CPU-to-FPGA interface. It takes a lot of FPGA pins and it tends to be async and slow. It would be great to have an industry-standard LVDS-type fast serial interface, with hooks like shared memory, but transparent and easy to use. Something like ARM internal to an FPGA could have a synchronous, maybe shared memory, interface into one of those SOPC type virtual bus structures without wasting FPGA pins. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Reply by ●April 21, 20132013-04-21
On 4/21/2013 9:23 AM, Vladimir Vassilevsky wrote:> On 4/20/2013 5:42 PM, rickman wrote: >> I have been working on designs of processors for FPGAs for quite a >> while. I have looked at the uBlaze, the picoBlaze, the NIOS, two from >> Lattice and any number of open source processors. Many of the open >> source designs were stack processors since they tend to be small and >> efficient in an FPGA. J1 is one I had pretty much missed until lately. >> It is fast and small and looks like it wasn't too hard to design >> (although looks may be deceptive), I'm impressed. There is also the b16 >> from Bernd Paysan, the uCore, the ZPU and many others. >> >> Lately I have been looking at a hybrid approach which combines features >> of addressing registers in order to access parameters of a stack CPU. It >> looks interesting. >> >> Anyone else here doing processor designs on FPGAs? >> > > Soft core is fun thing to do, but otherwise I see no use. > Except for very few special applications, standalone processor is better > then FPGA soft core in every point, especially the price.Everyone is entitled to their opinion, but this is *far* from fact. The CPUs in my designs have so far been *free* in recurring price. They fit in a small part of the lowest priced device I can find. Most people think of large, complex code that requires lots of RAM and big, fast external CPUs. I think in terms of small, internal processors that run fast in a very small code space. So they fit inside an FPGA very easily, likely not much bigger than the state machines John talks about. BTW, have you looked at any of the soft cores? The J1 is pretty amazing in terms of just basic simplicity, fast too at 100 MHz. They talk about the source just being 200 lines of verilog, but I don't know how many LUTs the design is, but from the block diagram I expect it is not very big. I'm not sure I can improve on it in any significant way. -- Rick
Reply by ●April 21, 20132013-04-21
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:> On Sun, 21 Apr 2013 08:32:44 -0500, Vladimir Vassilevsky <nospam@nowhere.com> > wrote: > >> On 4/20/2013 8:37 PM, John Larkin wrote: >> >>> My ideal computer would have one CPU that's just the OS, and a hundred or so >>> assignable cores, one for each device, file system, program, or thread. The OS >>> would be a few thousand lines of code, if that. With serious hardware >>> protection, it would be totally virus/trojan/crash immune. >> >> >> Utter nonsense. >> >> N cores means N^2 interfaces with associated version hell. > > Better than having all N processes in the same memory space. Much better. > > >> As for protection, is not technical problem; it is paradigm problem. > > The architecture that I propose could have absolute hardware sandboxing of any > process, even drivers and things that can do DMA. Each processor would have > memory management - loaded by the OS - that knows the difference between code, > data, and stack. The OS would be tiny, absolutely protected, known reliable. > Just note all the things that Wintel did wrong, and don't do that. >and end up doing making new and innovative mistakes (just channeling Murphy here).
Reply by ●April 21, 20132013-04-21
On Apr 21, 6:05=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:> On Sun, 21 Apr 2013 08:23:37 -0500, Vladimir Vassilevsky <nos...@nowhere.=com>> wrote: > > > > > > > > > > >On 4/20/2013 5:42 PM, rickman wrote: > >> I have been working on designs of processors for FPGAs for quite a > >> while. =A0I have looked at the uBlaze, the picoBlaze, the NIOS, two fr=om> >> Lattice and any number of open source processors. =A0Many of the open > >> source designs were stack processors since they tend to be small and > >> efficient in an FPGA. =A0J1 is one I had pretty much missed until late=ly.> >> =A0 It is fast and small and looks like it wasn't too hard to design > >> (although looks may be deceptive), I'm impressed. =A0There is also the=b16> >> from Bernd Paysan, the uCore, the ZPU and many others. > > >> Lately I have been looking at a hybrid approach which combines feature=s> >> of addressing registers in order to access parameters of a stack CPU. =It> >> looks interesting. > > >> Anyone else here doing processor designs on FPGAs? > > >Soft core is fun thing to do, but otherwise I see no use. > >Except for very few special applications, standalone processor is better > >then FPGA soft core in every point, especially the price. > > >Vladimir Vassilevsky > >DSP and Mixed Signal Designs > >www.abvolt.com > > The annoying thing is the CPU-to-FPGA interface. It takes a lot of FPGA p=ins and> it tends to be async and slow. It would be great to have an industry-stan=dard> LVDS-type fast serial interface, with hooks like shared memory, but trans=parent> and easy to use. > > Something like ARM internal to an FPGA could have a synchronous, maybe sh=ared> memory, interface into one of those SOPC type virtual bus structures with=out> wasting FPGA pins. >xilinx Zynq, arm9 with an fpga on the side -Lasse
Reply by ●April 21, 20132013-04-21
On Sun, 21 Apr 2013 17:34:12 GMT, Ralph Barone <address_is@invalid.invalid> wrote:>John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> On Sun, 21 Apr 2013 08:32:44 -0500, Vladimir Vassilevsky <nospam@nowhere.com> >> wrote: >> >>> On 4/20/2013 8:37 PM, John Larkin wrote: >>> >>>> My ideal computer would have one CPU that's just the OS, and a hundred or so >>>> assignable cores, one for each device, file system, program, or thread. The OS >>>> would be a few thousand lines of code, if that. With serious hardware >>>> protection, it would be totally virus/trojan/crash immune. >>> >>> >>> Utter nonsense. >>> >>> N cores means N^2 interfaces with associated version hell. >> >> Better than having all N processes in the same memory space. Much better. >> >> >>> As for protection, is not technical problem; it is paradigm problem. >> >> The architecture that I propose could have absolute hardware sandboxing of any >> process, even drivers and things that can do DMA. Each processor would have >> memory management - loaded by the OS - that knows the difference between code, >> data, and stack. The OS would be tiny, absolutely protected, known reliable. >> Just note all the things that Wintel did wrong, and don't do that. >> > > >and end up doing making new and innovative mistakes (just channeling Murphy >here).DEC wrote operating systems (TOPS10, VMS, RSTS) that ran for months between power failures, time-sharing multiple, sometimes hostile, users. We are now in the dark ages of computing, overwhelmed by bloat and slop and complexity. No wonder people are buying tablets. DEC understood things that Intel and Microsoft never really got, like: don't execute data. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Reply by ●April 21, 20132013-04-21
On Sun, 21 Apr 2013 11:09:02 -0700 (PDT), "langwadt@fonz.dk" <langwadt@fonz.dk> wrote:>On Apr 21, 6:05�pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Sun, 21 Apr 2013 08:23:37 -0500, Vladimir Vassilevsky <nos...@nowhere.com> >> wrote: >> >> >> >> >> >> >> >> >> >> >On 4/20/2013 5:42 PM, rickman wrote: >> >> I have been working on designs of processors for FPGAs for quite a >> >> while. �I have looked at the uBlaze, the picoBlaze, the NIOS, two from >> >> Lattice and any number of open source processors. �Many of the open >> >> source designs were stack processors since they tend to be small and >> >> efficient in an FPGA. �J1 is one I had pretty much missed until lately. >> >> � It is fast and small and looks like it wasn't too hard to design >> >> (although looks may be deceptive), I'm impressed. �There is also the b16 >> >> from Bernd Paysan, the uCore, the ZPU and many others. >> >> >> Lately I have been looking at a hybrid approach which combines features >> >> of addressing registers in order to access parameters of a stack CPU. It >> >> looks interesting. >> >> >> Anyone else here doing processor designs on FPGAs? >> >> >Soft core is fun thing to do, but otherwise I see no use. >> >Except for very few special applications, standalone processor is better >> >then FPGA soft core in every point, especially the price. >> >> >Vladimir Vassilevsky >> >DSP and Mixed Signal Designs >> >www.abvolt.com >> >> The annoying thing is the CPU-to-FPGA interface. It takes a lot of FPGA pins and >> it tends to be async and slow. It would be great to have an industry-standard >> LVDS-type fast serial interface, with hooks like shared memory, but transparent >> and easy to use. >> >> Something like ARM internal to an FPGA could have a synchronous, maybe shared >> memory, interface into one of those SOPC type virtual bus structures without >> wasting FPGA pins. >> > >xilinx Zynq, arm9 with an fpga on the side > >-LasseWe gave up on Xilinx a few yeas ago: great silicon, horrendous software tools. Altera is somewhat less horrendous. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Reply by ●April 21, 20132013-04-21
On 4/21/2013 4:22 PM, John Larkin wrote:> On Sun, 21 Apr 2013 17:34:12 GMT, Ralph Barone<address_is@invalid.invalid> > wrote: >> >> and end up doing making new and innovative mistakes (just channeling Murphy >> here). > > DEC wrote operating systems (TOPS10, VMS, RSTS) that ran for months between > power failures, time-sharing multiple, sometimes hostile, users. We are now in > the dark ages of computing, overwhelmed by bloat and slop and complexity. No > wonder people are buying tablets. DEC understood things that Intel and Microsoft > never really got, like: don't execute data.You really should stick to things you understand. Every Intel processor since the 8086 has included protection mechanism to prevent the execution of data. But they have to be used properly... Blame Microsoft and all the other software vendors, but don't blame Intel. Actually, this is an issue just like so many that are determined by the market place. When users put value on these features and spend their money accordingly, the market will respond. So don't buy Windows anymore if you don't like it. Microsoft will either respond or go out of business. But that's not going to happen. People just like to complain about MS while they continue giving them their money. -- Rick
Reply by ●April 21, 20132013-04-21
On Sun, 21 Apr 2013 13:22:12 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:> >DEC wrote operating systems (TOPS10, VMS, RSTS) that ran for months between >power failures, time-sharing multiple, sometimes hostile, users.I was responsible for some VMS-11 systems and I forgot to boot the system every summer, when no-one was around. Booting the system the system next year and everyone were happy :-).>We are now in >the dark ages of computing, overwhelmed by bloat and slop and complexity. No >wonder people are buying tablets. DEC understood things that Intel and Microsoft >never really got, like: don't execute data.PDP-11/RSX-11M+ (early 1970's) had separate I/D spaces, VAX/VMS (mid 70's) had executable program sections.
