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Altera FPGA pseudoinstruction, RAM configuration

Started by Bruce Varley March 25, 2013
Does anyone know the Verilog command within the Altera Quartus II IDE for 
forcing 2-d boolean arrays to be implemented using internal RAM hardware, 
rather than as linked logic elements?
 


On Mon, 25 Mar 2013 16:31:35 +0800, Bruce Varley wrote:

> Does anyone know the Verilog command within the Altera Quartus II IDE > for forcing 2-d boolean arrays to be implemented using internal RAM > hardware, > rather than as linked logic elements?
Write your Verilog to match the Altera ram inference template and it should be compiled into ram without needing to give the tools any extra hints. Do it right and it will also compile in other vendors' tools. Off the top of my head: parameter ADDR_WIDTH = whatever; parameter DATA_WIDTH = whatever; ... reg [DATA_WIDTH-1:0] ram [0:(1<<ADDR_WIDTH)-1]; wire [ADDR_WIDTH-1:00] address; ... // combinatorial read assign data_out = ram[address]; // clocked write always @(posedge clock) begin if (write_enable) begin ram[address] <= data_in; end end BTW, comp.arch.fpga would be a more approriate newsgroup. Regards, Allan