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Low Jitter 20MHz oscillator

Started by hbv March 1, 2013
On Sun, 3 Mar 2013 07:39:47 -0800 (PST), jdc@teleport.com wrote:

>On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >> Hi all, >> >> >> >> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >> >> ended ), 20Mhz (+-few percent...) and most important a low jitter on >> >> this output (few ps). >> >> >> >> Any ideas are welcomed. Habib. > > > >Jitter is a function of the phase noise profile. > >Set your jitter spec., calculate your jitter from the phase noise > >of your chosen oscillator. > >Then you don't need to argue with anybody. > >It's not difficult.
At what kind of offsets from the carrier should the phase noise profile be measured, to give meaningful jitter characteristic ? At least for measuring phase noise for oscillators for RF applications (especially first LO), it is very hard to get meaningfully readings within +/-1 kHz from carrier, even with high quality test equipment, unless you use some deep crystal notch filters at the carrier frequency.
On 2013-03-03 16:39, jdc@teleport.com wrote:
> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >> Hi all, >> >> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >> this output (few ps). >> >> Any ideas are welcomed. Habib. > > Jitter is a function of the phase noise profile. > Set your jitter spec., calculate your jitter from the phase noise > of your chosen oscillator. > Then you don't need to argue with anybody. > It's not difficult. >
Well, this begs the question: How do you do it? Jeroen Belleman
On Tue, 05 Mar 2013 09:09:24 +0100, Jeroen Belleman <jeroen@nospam.please>
wrote:

>On 2013-03-03 16:39, jdc@teleport.com wrote: >> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >>> Hi all, >>> >>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >>> this output (few ps). >>> >>> Any ideas are welcomed. Habib. >> >> Jitter is a function of the phase noise profile. >> Set your jitter spec., calculate your jitter from the phase noise >> of your chosen oscillator. >> Then you don't need to argue with anybody. >> It's not difficult. >> > >Well, this begs the question: How do you do it? > >Jeroen Belleman
I have a cool Windows program that converts a phase noise profile to RMS jitter. Someone in SED supplied it (maybe you? I can't remember). The author isn't identified; it's PhaseNoiseCalc v 1.01 copyright ibrt 2003. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Tue, 05 Mar 2013 09:09:24 +0100, Jeroen Belleman
<jeroen@nospam.please> wrote:

>On 2013-03-03 16:39, jdc@teleport.com wrote: >> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >>> Hi all, >>> >>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >>> this output (few ps). >>> >>> Any ideas are welcomed. Habib. >> >> Jitter is a function of the phase noise profile. >> Set your jitter spec., calculate your jitter from the phase noise >> of your chosen oscillator. >> Then you don't need to argue with anybody. >> It's not difficult. >> > >Well, this begs the question: How do you do it? > >Jeroen Belleman
Dear Sir:- I must object in the strongest terms to the above use of "begs the question". http://en.wikipedia.org/wiki/Begging_the_question
On 2013-03-05 16:05, Spehro Pefhany wrote:
> On Tue, 05 Mar 2013 09:09:24 +0100, Jeroen Belleman > <jeroen@nospam.please> wrote: > >> On 2013-03-03 16:39, jdc@teleport.com wrote: >>> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >>>> Hi all, >>>> >>>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >>>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >>>> this output (few ps). >>>> >>>> Any ideas are welcomed. Habib. >>> >>> Jitter is a function of the phase noise profile. >>> Set your jitter spec., calculate your jitter from the phase noise >>> of your chosen oscillator. >>> Then you don't need to argue with anybody. >>> It's not difficult. >>> >> >> Well, this begs the question: How do you do it? >> >> Jeroen Belleman > > Dear Sir:- > > I must object in the strongest terms to the above use of "begs the > question". > > http://en.wikipedia.org/wiki/Begging_the_question >
Quite. Point taken. It prompts the question. Jeroen Belleman
On Tue, 05 Mar 2013 17:14:02 +0100, Jeroen Belleman
<jeroen@nospam.please> wrote:

>On 2013-03-05 16:05, Spehro Pefhany wrote: >> On Tue, 05 Mar 2013 09:09:24 +0100, Jeroen Belleman >> <jeroen@nospam.please> wrote: >> >>> On 2013-03-03 16:39, jdc@teleport.com wrote: >>>> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >>>>> Hi all, >>>>> >>>>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >>>>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >>>>> this output (few ps). >>>>> >>>>> Any ideas are welcomed. Habib. >>>> >>>> Jitter is a function of the phase noise profile. >>>> Set your jitter spec., calculate your jitter from the phase noise >>>> of your chosen oscillator. >>>> Then you don't need to argue with anybody. >>>> It's not difficult. >>>> >>> >>> Well, this begs the question: How do you do it? >>> >>> Jeroen Belleman >> >> Dear Sir:- >> >> I must object in the strongest terms to the above use of "begs the >> question". >> >> http://en.wikipedia.org/wiki/Begging_the_question >> > >Quite. Point taken. It prompts the question. > >Jeroen Belleman
Or begs (for) the question, which is a common use. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Tuesday, March 5, 2013 8:48:46 AM UTC-8, John Larkin wrote:
> On Tue, 05 Mar 2013 17:14:02 +0100, Jeroen Belleman >=20 > <jeroen@nospam.please> wrote: >=20 >=20 >=20 > >On 2013-03-05 16:05, Spehro Pefhany wrote: >=20 > >> On Tue, 05 Mar 2013 09:09:24 +0100, Jeroen Belleman >=20 > >> <jeroen@nospam.please> wrote: >=20 > >> >=20 > >>> On 2013-03-03 16:39, jdc@teleport.com wrote: >=20 > >>>> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >=20 > >>>>> Hi all, >=20 > >>>>> >=20 > >>>>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output singl=
e
>=20 > >>>>> ended ), 20Mhz (+-few percent...) and most important a low jitter o=
n>>
>=20 > >>>>> this output (few ps). >=20 > >>>>> >=20 > >>>>> Any ideas are welcomed. Habib. >=20 > >>>> >=20 > >>>> Jitter is a function of the phase noise profile. >=20 > >>>> Set your jitter spec., calculate your jitter from the phase noise >=20 > >>>> of your chosen oscillator. >=20 > >>>> Then you don't need to argue with anybody. >=20 > >>>> It's not difficult. >=20 > >>>> >=20 > >>> >=20 > >>> Well, this begs the question: How do you do it? >=20 > >>> >=20 > >>> Jeroen Belleman >=20 > >> >=20 > >> Dear Sir:- >=20 > >> >=20 > >> I must object in the strongest terms to the above use of "begs the >=20 > >> question". >=20 > >> >=20 > >> http://en.wikipedia.org/wiki/Begging_the_question >=20 > >> >=20 > > >=20 > >Quite. Point taken. It prompts the question. >=20 > > >=20 > >Jeroen Belleman >=20 >=20 >=20 > Or begs (for) the question, which is a common use. >=20 >=20 >=20 >=20 >=20 > --=20 >=20 >=20 >=20 > John Larkin Highland Technology, Inc >=20 >=20 >=20 > jlarkin at highlandtechnology dot com >=20 > http://www.highlandtechnology.com >=20 >=20 >=20 > Precision electronic instrumentation >=20 > Picosecond-resolution Digital Delay and Pulse generators >=20 > Custom laser drivers and controllers >=20 > Photonics and fiberoptic TTL data links >=20 > VME thermocouple, LVDT, synchro acquisition and simulation
The concept is pretty straight forward;=20 take the single sided spectral noise power and=20 convert it total rms jitter. =20 Where=92s it used, think about it for a second; What is one of the primary concerns when you=20 apply a clk to any high performance digitizer? What=92s on the back end of any modern day acquisition system?
On 2013-03-05 18:32, jdc@teleport.com wrote:
> On Tuesday, March 5, 2013 8:48:46 AM UTC-8, John Larkin wrote: >> On Tue, 05 Mar 2013 17:14:02 +0100, Jeroen Belleman >> >> <jeroen@nospam.please> wrote: >> >>>>> On 2013-03-03 16:39, jdc@teleport.com wrote: >> >>>>>> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >> >>>>>>> Hi all, >> >>>>>>> >> >>>>>>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >> >>>>>>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >> >>>>>>> this output (few ps). >> >>>>>> >> >>>>>> Jitter is a function of the phase noise profile. >>>>>> Set your jitter spec., calculate your jitter from the phase noise >>>>>> of your chosen oscillator. >>>>>> Then you don't need to argue with anybody. >>>>>> It's not difficult. >> >>>>> Well then, how do you do it? >> >>> Jeroen Belleman > > The concept is pretty straight forward; > take the single sided spectral noise power and > convert it total rms jitter.
That's not an answer! You'll have to come up with something a little more explicit! Jeroen Belleman
On 03/05/2013 02:00 PM, Jeroen wrote:
> On 2013-03-05 18:32, jdc@teleport.com wrote: >> On Tuesday, March 5, 2013 8:48:46 AM UTC-8, John Larkin wrote: >>> On Tue, 05 Mar 2013 17:14:02 +0100, Jeroen Belleman >>> >>> <jeroen@nospam.please> wrote: >>> >>>>>> On 2013-03-03 16:39, jdc@teleport.com wrote: >>> >>>>>>> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >>> >>>>>>>> Hi all, >>> >>>>>>>> >>> >>>>>>>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >>> >>>>>>>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >>> >>>>>>>> this output (few ps). >>> >>>>>>> >>> >>>>>>> Jitter is a function of the phase noise profile. >>>>>>> Set your jitter spec., calculate your jitter from the phase noise >>>>>>> of your chosen oscillator. >>>>>>> Then you don't need to argue with anybody. >>>>>>> It's not difficult. >>> >>>>>> Well then, how do you do it? >>> >>>> Jeroen Belleman >> >> The concept is pretty straight forward; >> take the single sided spectral noise power and >> convert it total rms jitter. > > That's not an answer! You'll have to come up with something a little > more explicit! > > Jeroen Belleman >
If the carrier-to-noise ratio is dominated by phase noise, the RMS phase jitter in radians is equal to 1/sqrt(CNR). You can derive that from the formula for sin(a+b), with a=omega*t and b a random variable. For additive noise, it's 1/sqrt(2*CNR), because half of that noise power goes into AM (I) rather than PM (Q). Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Tue, 5 Mar 2013 09:32:29 -0800 (PST), jdc@teleport.com wrote:

>On Tuesday, March 5, 2013 8:48:46 AM UTC-8, John Larkin wrote: >> On Tue, 05 Mar 2013 17:14:02 +0100, Jeroen Belleman >> >> <jeroen@nospam.please> wrote: >> >> >> >> >On 2013-03-05 16:05, Spehro Pefhany wrote: >> >> >> On Tue, 05 Mar 2013 09:09:24 +0100, Jeroen Belleman >> >> >> <jeroen@nospam.please> wrote: >> >> >> >> >> >>> On 2013-03-03 16:39, jdc@teleport.com wrote: >> >> >>>> On Friday, March 1, 2013 5:41:08 AM UTC-8, hbv wrote: >> >> >>>>> Hi all, >> >> >>>>> >> >> >>>>> We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single >> >> >>>>> ended ), 20Mhz (+-few percent...) and most important a low jitter on>> >> >> >>>>> this output (few ps). >> >> >>>>> >> >> >>>>> Any ideas are welcomed. Habib. >> >> >>>> >> >> >>>> Jitter is a function of the phase noise profile. >> >> >>>> Set your jitter spec., calculate your jitter from the phase noise >> >> >>>> of your chosen oscillator. >> >> >>>> Then you don't need to argue with anybody. >> >> >>>> It's not difficult. >> >> >>>> >> >> >>> >> >> >>> Well, this begs the question: How do you do it? >> >> >>> >> >> >>> Jeroen Belleman >> >> >> >> >> >> Dear Sir:- >> >> >> >> >> >> I must object in the strongest terms to the above use of "begs the >> >> >> question". >> >> >> >> >> >> http://en.wikipedia.org/wiki/Begging_the_question >> >> >> >> >> > >> >> >Quite. Point taken. It prompts the question. >> >> > >> >> >Jeroen Belleman >> >> >> >> Or begs (for) the question, which is a common use. >> >> >> >> >> >> -- >> >> >> >> John Larkin Highland Technology, Inc >> >> >> >> jlarkin at highlandtechnology dot com >> >> http://www.highlandtechnology.com >> >> >> >> Precision electronic instrumentation >> >> Picosecond-resolution Digital Delay and Pulse generators >> >> Custom laser drivers and controllers >> >> Photonics and fiberoptic TTL data links >> >> VME thermocouple, LVDT, synchro acquisition and simulation > > > >The concept is pretty straight forward; >take the single sided spectral noise power and >convert it total rms jitter.
RMS jitter has to be specified over some observation interval. The frequency-domain phase noise spectrum gets mapped into the jitter-vs-time curve. A cheap XO may have a picosecond of RMS jitter measured over single periods, and 100 ns RMS jitter measured over a full second. How much that matters in an ADC clock depends on what the digitized signal means. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators