On 11/15/2012 04:20 PM, John Larkin wrote:> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <me@somewhere.net> wrote: > >> On 11/14/2012 06:19 PM, John Larkin wrote: >>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <me@somewhere.net> wrote: >>> >>>> The thread related to large signal PSpice models and an emitter follower >>>> comes from the following problem: >>>> >>>> I have an oscillator that should drive a digital part of the system. >>>> In short, what is the best way to achieve this? >>>> >>>> My first attempt has been a common base Colpitts oscillator that gives a >>>> signal riding on the +Vcc rail. This has been AC coupled to a 74AC gate >>>> biased to the point that gives square output signals. >>>> >>>> This works more ore less ok, but: the startup transient, which is >>>> important here, is different depending if the oscillator amplitude is >>>> sufficient to toggle the gate. This translates into an envelope that >>>> raises more ore less smoothly until the gate begins toggling, where the >>>> envelope raises more abruptly -and I guess that the instantaneous >>>> frequency changes. >>>> >>>> I have thought of two causes for this. The first one is feedback via the >>>> DC supply: the spikes generated by the gate switching get coupled back >>>> to the oscillator. The second one could be the change in input impedance >>>> seen by the oscillator -does this make sense? The cure for #1 could be >>>> better supply bypassing. The cure for #2 a buffer stage. >>>> >>>> So, what could be a good way to generate a digital signal from an >>>> oscillator without loading it? Ideally I would like to preserve the >>>> instantaneous frequency of the unloaded startup transient. And: power >>>> consumption should be low, say preferably (much) less than 1 mA. >>>> Operating frequency should be initially 27 MHz, but ideally scalable up >>>> to ~1 GHz. >>>> >>>> Pere >>> >>> Do you want an LC oscillator that starts instantly and coherently, >>> with a digital clock output? We do that, with LCs at low frequencies, >>> and coaxial ceramic resonators at 500 MHz or so. 1 GHz shouldn't be >>> horribly difficult, except for the milliwatt constraint. It's just a >>> matter of getting the initial conditions right. >>> >>> https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg >> >> Are you building some kind of synchronous oscillator? > > We use gated oscillators in our digital delay generators. When we gat > a rrigger, we start a clock oscillator, and count ticks to get coarse > delay. An analog ramp thing gives fine delay to interpolate down to > picoseconds. Sometimes just the LC is good enough, for short delays. > The coaxial resonator things are great for medium accuracy and delay. > he best is to use a gated LC for the clock, but phase-lock it to a > crystal oscillator to get longterm precision.I have used ceramic coaxial resonators to build oscillators at ~433 MHz, and they are quite stable. I have also seen that you make stuff on FPGAs. IIRC there are interesting techniques to achieve high timing precision making use only of digital resources (keywords: time to digital FPGA)...> In our application >> an external signal influences the startup transient (think superreg. >> principle) and the information contained therein should be more or less >> preserved. > > OK, that's different. It's an externally quenched superregen, I guess. > > Why not use a grounded LC and a non-inverting gain element? Or you > could use a tiny toroidal transformer, with a secondary winding for > the base of a PNP transistor, to provide the gain.I have used several oscillator topologies. At 800 MHz the tapped-C // L resonator plus emitter follower works ok, i.e. it is a non-inverting topology. But the problem is more or less the same: how to tap the signal out.> One oscillator that I really like is an LVDS-CMOS converter chip that > is both the feedback gain and the comparator, with the LC grounded. > But that wouldn't work for your application, if I understand it.You mean something like the DS90C032? You mean sensing with the LVDS side and feeding back from the CMOS side to provide the gain? I guess that this would not work, as I need a wide linear part where the oscillator grows up more or less slowly... Thanks for your inputs. Pere
Oscillator buffer
Started by ●November 14, 2012
Reply by ●November 15, 20122012-11-15
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <me@somewhere.net> wrote: [snip]> >You mean something like the DS90C032? You mean sensing with the LVDS >side and feeding back from the CMOS side to provide the gain? I guess >that this would not work, as I need a wide linear part where the >oscillator grows up more or less slowly... > >Thanks for your inputs. > >Pere >Does your buffer need to replicate the oscillator amplitude ramp-up, or can the buffer simply square it up? ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <me@somewhere.net> wrote:>On 11/15/2012 04:20 PM, John Larkin wrote: >> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <me@somewhere.net> wrote: >> >>> On 11/14/2012 06:19 PM, John Larkin wrote: >>>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <me@somewhere.net> wrote: >>>> >>>>> The thread related to large signal PSpice models and an emitter follower >>>>> comes from the following problem: >>>>> >>>>> I have an oscillator that should drive a digital part of the system. >>>>> In short, what is the best way to achieve this? >>>>> >>>>> My first attempt has been a common base Colpitts oscillator that gives a >>>>> signal riding on the +Vcc rail. This has been AC coupled to a 74AC gate >>>>> biased to the point that gives square output signals. >>>>> >>>>> This works more ore less ok, but: the startup transient, which is >>>>> important here, is different depending if the oscillator amplitude is >>>>> sufficient to toggle the gate. This translates into an envelope that >>>>> raises more ore less smoothly until the gate begins toggling, where the >>>>> envelope raises more abruptly -and I guess that the instantaneous >>>>> frequency changes. >>>>> >>>>> I have thought of two causes for this. The first one is feedback via the >>>>> DC supply: the spikes generated by the gate switching get coupled back >>>>> to the oscillator. The second one could be the change in input impedance >>>>> seen by the oscillator -does this make sense? The cure for #1 could be >>>>> better supply bypassing. The cure for #2 a buffer stage. >>>>> >>>>> So, what could be a good way to generate a digital signal from an >>>>> oscillator without loading it? Ideally I would like to preserve the >>>>> instantaneous frequency of the unloaded startup transient. And: power >>>>> consumption should be low, say preferably (much) less than 1 mA. >>>>> Operating frequency should be initially 27 MHz, but ideally scalable up >>>>> to ~1 GHz. >>>>> >>>>> Pere >>>> >>>> Do you want an LC oscillator that starts instantly and coherently, >>>> with a digital clock output? We do that, with LCs at low frequencies, >>>> and coaxial ceramic resonators at 500 MHz or so. 1 GHz shouldn't be >>>> horribly difficult, except for the milliwatt constraint. It's just a >>>> matter of getting the initial conditions right. >>>> >>>> https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg >>> >>> Are you building some kind of synchronous oscillator? >> >> We use gated oscillators in our digital delay generators. When we gat >> a rrigger, we start a clock oscillator, and count ticks to get coarse >> delay. An analog ramp thing gives fine delay to interpolate down to >> picoseconds. Sometimes just the LC is good enough, for short delays. >> The coaxial resonator things are great for medium accuracy and delay. >> he best is to use a gated LC for the clock, but phase-lock it to a >> crystal oscillator to get longterm precision. > >I have used ceramic coaxial resonators to build oscillators at ~433 MHz, >and they are quite stable. >I have also seen that you make stuff on FPGAs. IIRC there are >interesting techniques to achieve high timing precision making use only >of digital resources (keywords: time to digital FPGA)...That stuff is interesting, but we haven't done it inside an FPGA. We don't see a big demand for TDCs these days, and a couple of people do it really well. No point trying to compete with someone established in a small market. We did do a new TDC lately, at a customer's request, but we used our old analog technique, with the FPGA just doing clocked logic.> >> In our application >>> an external signal influences the startup transient (think superreg. >>> principle) and the information contained therein should be more or less >>> preserved. >> >> OK, that's different. It's an externally quenched superregen, I guess. >> >> Why not use a grounded LC and a non-inverting gain element? Or you >> could use a tiny toroidal transformer, with a secondary winding for >> the base of a PNP transistor, to provide the gain. > >I have used several oscillator topologies. At 800 MHz the tapped-C // L >resonator plus emitter follower works ok, i.e. it is a non-inverting >topology. But the problem is more or less the same: how to tap the >signal out. > >> One oscillator that I really like is an LVDS-CMOS converter chip that >> is both the feedback gain and the comparator, with the LC grounded. >> But that wouldn't work for your application, if I understand it. > >You mean something like the DS90C032? You mean sensing with the LVDS >side and feeding back from the CMOS side to provide the gain? I guess >that this would not work, as I need a wide linear part where the >oscillator grows up more or less slowly...Yeah, if you want a clasic exponential oscillation buildup, you need a linear gain element, a transistor or a fast opamp or a MMIC. Given your power budget, a transistor might be best. How about a powdered-iron toroid with a feedback winding for the transistor/fet drive? The LC could be grounded. A fet would be cool, to keep the Q up. Or something like this.... https://dl.dropbox.com/u/53724080/Circuits/Oscillators/LC_quench.JPG -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 11:11:30 -0800, John Larkin wrote:> On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <me@somewhere.net> wrote: > >>On 11/15/2012 04:20 PM, John Larkin wrote: >>> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <me@somewhere.net> wrote: >>> >>>> On 11/14/2012 06:19 PM, John Larkin wrote: >>>>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <me@somewhere.net> >>>>> wrote: >>>>> >>>>>> The thread related to large signal PSpice models and an emitter >>>>>> follower comes from the following problem: >>>>>> >>>>>> I have an oscillator that should drive a digital part of the >>>>>> system. In short, what is the best way to achieve this? >>>>>> >>>>>> My first attempt has been a common base Colpitts oscillator that >>>>>> gives a signal riding on the +Vcc rail. This has been AC coupled to >>>>>> a 74AC gate biased to the point that gives square output signals. >>>>>> >>>>>> This works more ore less ok, but: the startup transient, which is >>>>>> important here, is different depending if the oscillator amplitude >>>>>> is sufficient to toggle the gate. This translates into an envelope >>>>>> that raises more ore less smoothly until the gate begins toggling, >>>>>> where the envelope raises more abruptly -and I guess that the >>>>>> instantaneous frequency changes. >>>>>> >>>>>> I have thought of two causes for this. The first one is feedback >>>>>> via the DC supply: the spikes generated by the gate switching get >>>>>> coupled back to the oscillator. The second one could be the change >>>>>> in input impedance seen by the oscillator -does this make sense? >>>>>> The cure for #1 could be better supply bypassing. The cure for #2 a >>>>>> buffer stage. >>>>>> >>>>>> So, what could be a good way to generate a digital signal from an >>>>>> oscillator without loading it? Ideally I would like to preserve the >>>>>> instantaneous frequency of the unloaded startup transient. And: >>>>>> power consumption should be low, say preferably (much) less than 1 >>>>>> mA. Operating frequency should be initially 27 MHz, but ideally >>>>>> scalable up to ~1 GHz. >>>>>> >>>>>> Pere >>>>> >>>>> Do you want an LC oscillator that starts instantly and coherently, >>>>> with a digital clock output? We do that, with LCs at low >>>>> frequencies, and coaxial ceramic resonators at 500 MHz or so. 1 GHz >>>>> shouldn't be horribly difficult, except for the milliwatt >>>>> constraint. It's just a matter of getting the initial conditions >>>>> right. >>>>> >>>>> https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg >>>> >>>> Are you building some kind of synchronous oscillator? >>> >>> We use gated oscillators in our digital delay generators. When we gat >>> a rrigger, we start a clock oscillator, and count ticks to get coarse >>> delay. An analog ramp thing gives fine delay to interpolate down to >>> picoseconds. Sometimes just the LC is good enough, for short delays. >>> The coaxial resonator things are great for medium accuracy and delay. >>> he best is to use a gated LC for the clock, but phase-lock it to a >>> crystal oscillator to get longterm precision. >> >>I have used ceramic coaxial resonators to build oscillators at ~433 MHz, >>and they are quite stable. >>I have also seen that you make stuff on FPGAs. IIRC there are >>interesting techniques to achieve high timing precision making use only >>of digital resources (keywords: time to digital FPGA)... > > That stuff is interesting, but we haven't done it inside an FPGA. We > don't see a big demand for TDCs these days, and a couple of people do it > really well. No point trying to compete with someone established in a > small market. > > We did do a new TDC lately, at a customer's request, but we used our old > analog technique, with the FPGA just doing clocked logic. > > > >>> In our application >>>> an external signal influences the startup transient (think superreg. >>>> principle) and the information contained therein should be more or >>>> less preserved. >>> >>> OK, that's different. It's an externally quenched superregen, I guess. >>> >>> Why not use a grounded LC and a non-inverting gain element? Or you >>> could use a tiny toroidal transformer, with a secondary winding for >>> the base of a PNP transistor, to provide the gain. >> >>I have used several oscillator topologies. At 800 MHz the tapped-C // L >>resonator plus emitter follower works ok, i.e. it is a non-inverting >>topology. But the problem is more or less the same: how to tap the >>signal out. >> >>> One oscillator that I really like is an LVDS-CMOS converter chip that >>> is both the feedback gain and the comparator, with the LC grounded. >>> But that wouldn't work for your application, if I understand it. >> >>You mean something like the DS90C032? You mean sensing with the LVDS >>side and feeding back from the CMOS side to provide the gain? I guess >>that this would not work, as I need a wide linear part where the >>oscillator grows up more or less slowly... > > Yeah, if you want a clasic exponential oscillation buildup, you need a > linear gain element, a transistor or a fast opamp or a MMIC. Given your > power budget, a transistor might be best. > > How about a powdered-iron toroid with a feedback winding for the > transistor/fet drive? The LC could be grounded. A fet would be cool, to > keep the Q up. > > Or something like this.... > > https://dl.dropbox.com/u/53724080/Circuits/Oscillators/LC_quench.JPGI have heard, from either Rhea's oscillator book or Hayward's RF circuits book, that a Hartley oscillator like that one tends to be more prone to UHF parasitic oscillations than a Colpitts. If you redraw the oscillator as a grounded-source, you'll see that the Hartley is a high pass between drain and gate (leading to more loop gain at high frequencies), where a Colpitts is a low pass. I have, like, zero experience with this as a problem, but given who's sourcing the comments it certainly makes sense. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 14:40:15 -0600, Tim Wescott <tim@seemywebsite.com> wrote:>On Thu, 15 Nov 2012 11:11:30 -0800, John Larkin wrote: > >> On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <me@somewhere.net> wrote: >> >>>On 11/15/2012 04:20 PM, John Larkin wrote: >>>> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <me@somewhere.net> wrote: >>>> >>>>> On 11/14/2012 06:19 PM, John Larkin wrote: >>>>>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <me@somewhere.net> >>>>>> wrote: >>>>>> >>>>>>> The thread related to large signal PSpice models and an emitter >>>>>>> follower comes from the following problem: >>>>>>> >>>>>>> I have an oscillator that should drive a digital part of the >>>>>>> system. In short, what is the best way to achieve this? >>>>>>> >>>>>>> My first attempt has been a common base Colpitts oscillator that >>>>>>> gives a signal riding on the +Vcc rail. This has been AC coupled to >>>>>>> a 74AC gate biased to the point that gives square output signals. >>>>>>> >>>>>>> This works more ore less ok, but: the startup transient, which is >>>>>>> important here, is different depending if the oscillator amplitude >>>>>>> is sufficient to toggle the gate. This translates into an envelope >>>>>>> that raises more ore less smoothly until the gate begins toggling, >>>>>>> where the envelope raises more abruptly -and I guess that the >>>>>>> instantaneous frequency changes. >>>>>>> >>>>>>> I have thought of two causes for this. The first one is feedback >>>>>>> via the DC supply: the spikes generated by the gate switching get >>>>>>> coupled back to the oscillator. The second one could be the change >>>>>>> in input impedance seen by the oscillator -does this make sense? >>>>>>> The cure for #1 could be better supply bypassing. The cure for #2 a >>>>>>> buffer stage. >>>>>>> >>>>>>> So, what could be a good way to generate a digital signal from an >>>>>>> oscillator without loading it? Ideally I would like to preserve the >>>>>>> instantaneous frequency of the unloaded startup transient. And: >>>>>>> power consumption should be low, say preferably (much) less than 1 >>>>>>> mA. Operating frequency should be initially 27 MHz, but ideally >>>>>>> scalable up to ~1 GHz. >>>>>>> >>>>>>> Pere >>>>>> >>>>>> Do you want an LC oscillator that starts instantly and coherently, >>>>>> with a digital clock output? We do that, with LCs at low >>>>>> frequencies, and coaxial ceramic resonators at 500 MHz or so. 1 GHz >>>>>> shouldn't be horribly difficult, except for the milliwatt >>>>>> constraint. It's just a matter of getting the initial conditions >>>>>> right. >>>>>> >>>>>> https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg >>>>> >>>>> Are you building some kind of synchronous oscillator? >>>> >>>> We use gated oscillators in our digital delay generators. When we gat >>>> a rrigger, we start a clock oscillator, and count ticks to get coarse >>>> delay. An analog ramp thing gives fine delay to interpolate down to >>>> picoseconds. Sometimes just the LC is good enough, for short delays. >>>> The coaxial resonator things are great for medium accuracy and delay. >>>> he best is to use a gated LC for the clock, but phase-lock it to a >>>> crystal oscillator to get longterm precision. >>> >>>I have used ceramic coaxial resonators to build oscillators at ~433 MHz, >>>and they are quite stable. >>>I have also seen that you make stuff on FPGAs. IIRC there are >>>interesting techniques to achieve high timing precision making use only >>>of digital resources (keywords: time to digital FPGA)... >> >> That stuff is interesting, but we haven't done it inside an FPGA. We >> don't see a big demand for TDCs these days, and a couple of people do it >> really well. No point trying to compete with someone established in a >> small market. >> >> We did do a new TDC lately, at a customer's request, but we used our old >> analog technique, with the FPGA just doing clocked logic. >> >> >> >>>> In our application >>>>> an external signal influences the startup transient (think superreg. >>>>> principle) and the information contained therein should be more or >>>>> less preserved. >>>> >>>> OK, that's different. It's an externally quenched superregen, I guess. >>>> >>>> Why not use a grounded LC and a non-inverting gain element? Or you >>>> could use a tiny toroidal transformer, with a secondary winding for >>>> the base of a PNP transistor, to provide the gain. >>> >>>I have used several oscillator topologies. At 800 MHz the tapped-C // L >>>resonator plus emitter follower works ok, i.e. it is a non-inverting >>>topology. But the problem is more or less the same: how to tap the >>>signal out. >>> >>>> One oscillator that I really like is an LVDS-CMOS converter chip that >>>> is both the feedback gain and the comparator, with the LC grounded. >>>> But that wouldn't work for your application, if I understand it. >>> >>>You mean something like the DS90C032? You mean sensing with the LVDS >>>side and feeding back from the CMOS side to provide the gain? I guess >>>that this would not work, as I need a wide linear part where the >>>oscillator grows up more or less slowly... >> >> Yeah, if you want a clasic exponential oscillation buildup, you need a >> linear gain element, a transistor or a fast opamp or a MMIC. Given your >> power budget, a transistor might be best. >> >> How about a powdered-iron toroid with a feedback winding for the >> transistor/fet drive? The LC could be grounded. A fet would be cool, to >> keep the Q up. >> >> Or something like this.... >> >> https://dl.dropbox.com/u/53724080/Circuits/Oscillators/LC_quench.JPG > >I have heard, from either Rhea's oscillator book or Hayward's RF circuits >book, that a Hartley oscillator like that one tends to be more prone to >UHF parasitic oscillations than a Colpitts. If you redraw the oscillator >as a grounded-source, you'll see that the Hartley is a high pass between >drain and gate (leading to more loop gain at high frequencies), where a >Colpitts is a low pass. > >I have, like, zero experience with this as a problem, but given who's >sourcing the comments it certainly makes sense.I wouldn't call that one a Hartley; I'd call it a transformer-coupled oscillator (which may have a formal name of its own?) The transformer coupling will be bad at any frequency except resonance, and the fet, into the tank, only has gain at resonance, so it should be OK. Of course it needs details. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 12:50:05 -0800, John Larkin wrote:> On Thu, 15 Nov 2012 14:40:15 -0600, Tim Wescott <tim@seemywebsite.com> > wrote: > >>On Thu, 15 Nov 2012 11:11:30 -0800, John Larkin wrote: >> >>> On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <me@somewhere.net> wrote: >>> >>>>On 11/15/2012 04:20 PM, John Larkin wrote: >>>>> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <me@somewhere.net> >>>>> wrote: >>>>> >>>>>> On 11/14/2012 06:19 PM, John Larkin wrote: >>>>>>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <me@somewhere.net> >>>>>>> wrote: >>>>>>> >>>>>>>> The thread related to large signal PSpice models and an emitter >>>>>>>> follower comes from the following problem: >>>>>>>> >>>>>>>> I have an oscillator that should drive a digital part of the >>>>>>>> system. In short, what is the best way to achieve this? >>>>>>>> >>>>>>>> My first attempt has been a common base Colpitts oscillator that >>>>>>>> gives a signal riding on the +Vcc rail. This has been AC coupled >>>>>>>> to a 74AC gate biased to the point that gives square output >>>>>>>> signals. >>>>>>>> >>>>>>>> This works more ore less ok, but: the startup transient, which is >>>>>>>> important here, is different depending if the oscillator >>>>>>>> amplitude is sufficient to toggle the gate. This translates into >>>>>>>> an envelope that raises more ore less smoothly until the gate >>>>>>>> begins toggling, where the envelope raises more abruptly -and I >>>>>>>> guess that the instantaneous frequency changes. >>>>>>>> >>>>>>>> I have thought of two causes for this. The first one is feedback >>>>>>>> via the DC supply: the spikes generated by the gate switching get >>>>>>>> coupled back to the oscillator. The second one could be the >>>>>>>> change in input impedance seen by the oscillator -does this make >>>>>>>> sense? The cure for #1 could be better supply bypassing. The cure >>>>>>>> for #2 a buffer stage. >>>>>>>> >>>>>>>> So, what could be a good way to generate a digital signal from an >>>>>>>> oscillator without loading it? Ideally I would like to preserve >>>>>>>> the instantaneous frequency of the unloaded startup transient. >>>>>>>> And: power consumption should be low, say preferably (much) less >>>>>>>> than 1 mA. Operating frequency should be initially 27 MHz, but >>>>>>>> ideally scalable up to ~1 GHz. >>>>>>>> >>>>>>>> Pere >>>>>>> >>>>>>> Do you want an LC oscillator that starts instantly and coherently, >>>>>>> with a digital clock output? We do that, with LCs at low >>>>>>> frequencies, and coaxial ceramic resonators at 500 MHz or so. 1 >>>>>>> GHz shouldn't be horribly difficult, except for the milliwatt >>>>>>> constraint. It's just a matter of getting the initial conditions >>>>>>> right. >>>>>>> >>>>>>> https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg >>>>>> >>>>>> Are you building some kind of synchronous oscillator? >>>>> >>>>> We use gated oscillators in our digital delay generators. When we >>>>> gat a rrigger, we start a clock oscillator, and count ticks to get >>>>> coarse delay. An analog ramp thing gives fine delay to interpolate >>>>> down to picoseconds. Sometimes just the LC is good enough, for short >>>>> delays. The coaxial resonator things are great for medium accuracy >>>>> and delay. he best is to use a gated LC for the clock, but >>>>> phase-lock it to a crystal oscillator to get longterm precision. >>>> >>>>I have used ceramic coaxial resonators to build oscillators at ~433 >>>>MHz, and they are quite stable. >>>>I have also seen that you make stuff on FPGAs. IIRC there are >>>>interesting techniques to achieve high timing precision making use >>>>only of digital resources (keywords: time to digital FPGA)... >>> >>> That stuff is interesting, but we haven't done it inside an FPGA. We >>> don't see a big demand for TDCs these days, and a couple of people do >>> it really well. No point trying to compete with someone established in >>> a small market. >>> >>> We did do a new TDC lately, at a customer's request, but we used our >>> old analog technique, with the FPGA just doing clocked logic. >>> >>> >>> >>>>> In our application >>>>>> an external signal influences the startup transient (think >>>>>> superreg. principle) and the information contained therein should >>>>>> be more or less preserved. >>>>> >>>>> OK, that's different. It's an externally quenched superregen, I >>>>> guess. >>>>> >>>>> Why not use a grounded LC and a non-inverting gain element? Or you >>>>> could use a tiny toroidal transformer, with a secondary winding for >>>>> the base of a PNP transistor, to provide the gain. >>>> >>>>I have used several oscillator topologies. At 800 MHz the tapped-C // >>>>L resonator plus emitter follower works ok, i.e. it is a non-inverting >>>>topology. But the problem is more or less the same: how to tap the >>>>signal out. >>>> >>>>> One oscillator that I really like is an LVDS-CMOS converter chip >>>>> that is both the feedback gain and the comparator, with the LC >>>>> grounded. But that wouldn't work for your application, if I >>>>> understand it. >>>> >>>>You mean something like the DS90C032? You mean sensing with the LVDS >>>>side and feeding back from the CMOS side to provide the gain? I guess >>>>that this would not work, as I need a wide linear part where the >>>>oscillator grows up more or less slowly... >>> >>> Yeah, if you want a clasic exponential oscillation buildup, you need a >>> linear gain element, a transistor or a fast opamp or a MMIC. Given >>> your power budget, a transistor might be best. >>> >>> How about a powdered-iron toroid with a feedback winding for the >>> transistor/fet drive? The LC could be grounded. A fet would be cool, >>> to keep the Q up. >>> >>> Or something like this.... >>> >>> https://dl.dropbox.com/u/53724080/Circuits/Oscillators/LC_quench.JPG >> >>I have heard, from either Rhea's oscillator book or Hayward's RF >>circuits book, that a Hartley oscillator like that one tends to be more >>prone to UHF parasitic oscillations than a Colpitts. If you redraw the >>oscillator as a grounded-source, you'll see that the Hartley is a high >>pass between drain and gate (leading to more loop gain at high >>frequencies), where a Colpitts is a low pass. >> >>I have, like, zero experience with this as a problem, but given who's >>sourcing the comments it certainly makes sense. > > I wouldn't call that one a Hartley; I'd call it a transformer-coupled > oscillator (which may have a formal name of its own?) > > The transformer coupling will be bad at any frequency except resonance, > and the fet, into the tank, only has gain at resonance, so it should be > OK. Of course it needs details.The references that I've read basically say that if it's got coils fore and aft then it's a Hartley, regardless of whether those coils are coupled or not. Yes, the FET only has gain at resonance. Each and every one of them, whether intended or not. With the Hartley oscillator, the higher-than- intended resonances get a better chance of hijacking the oscillator behavior. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Reply by ●November 15, 20122012-11-15
Am 15.11.2012 09:25, schrieb o pere o:> > Unfortunately not in this application. The startup transient is the > relevant fact here.Download the operating & service manual for the HP 5370 A/B time interval counter. It has startable oscillators that really work. Circuits included. regards, Gerhard
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 16:11:01 -0600, Tim Wescott <tim@seemywebsite.com> wrote:>On Thu, 15 Nov 2012 12:50:05 -0800, John Larkin wrote: > >> On Thu, 15 Nov 2012 14:40:15 -0600, Tim Wescott <tim@seemywebsite.com> >> wrote: >> >>>On Thu, 15 Nov 2012 11:11:30 -0800, John Larkin wrote: >>> >>>> On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <me@somewhere.net> wrote: >>>> >>>>>On 11/15/2012 04:20 PM, John Larkin wrote: >>>>>> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <me@somewhere.net> >>>>>> wrote: >>>>>> >>>>>>> On 11/14/2012 06:19 PM, John Larkin wrote: >>>>>>>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <me@somewhere.net> >>>>>>>> wrote: >>>>>>>> >>>>>>>>> The thread related to large signal PSpice models and an emitter >>>>>>>>> follower comes from the following problem: >>>>>>>>> >>>>>>>>> I have an oscillator that should drive a digital part of the >>>>>>>>> system. In short, what is the best way to achieve this? >>>>>>>>> >>>>>>>>> My first attempt has been a common base Colpitts oscillator that >>>>>>>>> gives a signal riding on the +Vcc rail. This has been AC coupled >>>>>>>>> to a 74AC gate biased to the point that gives square output >>>>>>>>> signals. >>>>>>>>> >>>>>>>>> This works more ore less ok, but: the startup transient, which is >>>>>>>>> important here, is different depending if the oscillator >>>>>>>>> amplitude is sufficient to toggle the gate. This translates into >>>>>>>>> an envelope that raises more ore less smoothly until the gate >>>>>>>>> begins toggling, where the envelope raises more abruptly -and I >>>>>>>>> guess that the instantaneous frequency changes. >>>>>>>>> >>>>>>>>> I have thought of two causes for this. The first one is feedback >>>>>>>>> via the DC supply: the spikes generated by the gate switching get >>>>>>>>> coupled back to the oscillator. The second one could be the >>>>>>>>> change in input impedance seen by the oscillator -does this make >>>>>>>>> sense? The cure for #1 could be better supply bypassing. The cure >>>>>>>>> for #2 a buffer stage. >>>>>>>>> >>>>>>>>> So, what could be a good way to generate a digital signal from an >>>>>>>>> oscillator without loading it? Ideally I would like to preserve >>>>>>>>> the instantaneous frequency of the unloaded startup transient. >>>>>>>>> And: power consumption should be low, say preferably (much) less >>>>>>>>> than 1 mA. Operating frequency should be initially 27 MHz, but >>>>>>>>> ideally scalable up to ~1 GHz. >>>>>>>>> >>>>>>>>> Pere >>>>>>>> >>>>>>>> Do you want an LC oscillator that starts instantly and coherently, >>>>>>>> with a digital clock output? We do that, with LCs at low >>>>>>>> frequencies, and coaxial ceramic resonators at 500 MHz or so. 1 >>>>>>>> GHz shouldn't be horribly difficult, except for the milliwatt >>>>>>>> constraint. It's just a matter of getting the initial conditions >>>>>>>> right. >>>>>>>> >>>>>>>> https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg >>>>>>> >>>>>>> Are you building some kind of synchronous oscillator? >>>>>> >>>>>> We use gated oscillators in our digital delay generators. When we >>>>>> gat a rrigger, we start a clock oscillator, and count ticks to get >>>>>> coarse delay. An analog ramp thing gives fine delay to interpolate >>>>>> down to picoseconds. Sometimes just the LC is good enough, for short >>>>>> delays. The coaxial resonator things are great for medium accuracy >>>>>> and delay. he best is to use a gated LC for the clock, but >>>>>> phase-lock it to a crystal oscillator to get longterm precision. >>>>> >>>>>I have used ceramic coaxial resonators to build oscillators at ~433 >>>>>MHz, and they are quite stable. >>>>>I have also seen that you make stuff on FPGAs. IIRC there are >>>>>interesting techniques to achieve high timing precision making use >>>>>only of digital resources (keywords: time to digital FPGA)... >>>> >>>> That stuff is interesting, but we haven't done it inside an FPGA. We >>>> don't see a big demand for TDCs these days, and a couple of people do >>>> it really well. No point trying to compete with someone established in >>>> a small market. >>>> >>>> We did do a new TDC lately, at a customer's request, but we used our >>>> old analog technique, with the FPGA just doing clocked logic. >>>> >>>> >>>> >>>>>> In our application >>>>>>> an external signal influences the startup transient (think >>>>>>> superreg. principle) and the information contained therein should >>>>>>> be more or less preserved. >>>>>> >>>>>> OK, that's different. It's an externally quenched superregen, I >>>>>> guess. >>>>>> >>>>>> Why not use a grounded LC and a non-inverting gain element? Or you >>>>>> could use a tiny toroidal transformer, with a secondary winding for >>>>>> the base of a PNP transistor, to provide the gain. >>>>> >>>>>I have used several oscillator topologies. At 800 MHz the tapped-C // >>>>>L resonator plus emitter follower works ok, i.e. it is a non-inverting >>>>>topology. But the problem is more or less the same: how to tap the >>>>>signal out. >>>>> >>>>>> One oscillator that I really like is an LVDS-CMOS converter chip >>>>>> that is both the feedback gain and the comparator, with the LC >>>>>> grounded. But that wouldn't work for your application, if I >>>>>> understand it. >>>>> >>>>>You mean something like the DS90C032? You mean sensing with the LVDS >>>>>side and feeding back from the CMOS side to provide the gain? I guess >>>>>that this would not work, as I need a wide linear part where the >>>>>oscillator grows up more or less slowly... >>>> >>>> Yeah, if you want a clasic exponential oscillation buildup, you need a >>>> linear gain element, a transistor or a fast opamp or a MMIC. Given >>>> your power budget, a transistor might be best. >>>> >>>> How about a powdered-iron toroid with a feedback winding for the >>>> transistor/fet drive? The LC could be grounded. A fet would be cool, >>>> to keep the Q up. >>>> >>>> Or something like this.... >>>> >>>> https://dl.dropbox.com/u/53724080/Circuits/Oscillators/LC_quench.JPG >>> >>>I have heard, from either Rhea's oscillator book or Hayward's RF >>>circuits book, that a Hartley oscillator like that one tends to be more >>>prone to UHF parasitic oscillations than a Colpitts. If you redraw the >>>oscillator as a grounded-source, you'll see that the Hartley is a high >>>pass between drain and gate (leading to more loop gain at high >>>frequencies), where a Colpitts is a low pass. >>> >>>I have, like, zero experience with this as a problem, but given who's >>>sourcing the comments it certainly makes sense. >> >> I wouldn't call that one a Hartley; I'd call it a transformer-coupled >> oscillator (which may have a formal name of its own?) >> >> The transformer coupling will be bad at any frequency except resonance, >> and the fet, into the tank, only has gain at resonance, so it should be >> OK. Of course it needs details. > >The references that I've read basically say that if it's got coils fore >and aft then it's a Hartley, regardless of whether those coils are >coupled or not. > >Yes, the FET only has gain at resonance. Each and every one of them, >whether intended or not. With the Hartley oscillator, the higher-than- >intended resonances get a better chance of hijacking the oscillator >behavior.OK, rising to this here challenge here, I open my trusty copy of Radio Engineering (Frederick Terman, 3rd edition, 1947, p 410.) He shows the three classic oscillators as "Hartley", "Colpitts", and "Tickler Feedback", the latter being transformer coupled. But he does show the resonating cap in the grid winding, not the plate. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
Reply by ●November 15, 20122012-11-15
On Thu, 15 Nov 2012 23:17:34 +0100, Gerhard Hoffmann <dk4xp@arcor.de> wrote:>Am 15.11.2012 09:25, schrieb o pere o: > >> >> Unfortunately not in this application. The startup transient is the >> relevant fact here. > >Download the operating & service manual for the HP 5370 A/B time >interval counter. It has startable oscillators that really work. >Circuits included. > >regards, GerhardThey used ECL gate delay-line oscillators, varicap tuned. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
Reply by ●November 15, 20122012-11-15
On Nov 15, 6:01=A0pm, John Larkin <jlar...@highlandtechnology.com> wrote:> On Thu, 15 Nov 2012 16:11:01 -0600, Tim Wescott <t...@seemywebsite.com> > wrote: > > > > > > >On Thu, 15 Nov 2012 12:50:05 -0800, John Larkin wrote: > > >> On Thu, 15 Nov 2012 14:40:15 -0600, Tim Wescott <t...@seemywebsite.com= > > >> wrote: > > >>>On Thu, 15 Nov 2012 11:11:30 -0800, John Larkin wrote: > > >>>> On Thu, 15 Nov 2012 18:44:59 +0100, o pere o <m...@somewhere.net> wr=ote:> > >>>>>On 11/15/2012 04:20 PM, John Larkin wrote: > >>>>>> On Thu, 15 Nov 2012 09:24:50 +0100, o pere o <m...@somewhere.net> > >>>>>> wrote: > > >>>>>>> On 11/14/2012 06:19 PM, John Larkin wrote: > >>>>>>>> On Wed, 14 Nov 2012 16:58:13 +0100, o pere o <m...@somewhere.net= > > >>>>>>>> wrote: > > >>>>>>>>> The thread related to large signal PSpice models and an emitter > >>>>>>>>> follower comes from the following problem: > > >>>>>>>>> I have an oscillator that should drive a digital part of the > >>>>>>>>> system. In short, what is the best way to achieve this? > > >>>>>>>>> My first attempt has been a common base Colpitts oscillator tha=t> >>>>>>>>> gives a signal riding on the +Vcc rail. This has been AC couple=d> >>>>>>>>> to a 74AC gate biased to the point that gives square output > >>>>>>>>> signals. > > >>>>>>>>> This works more ore less ok, but: the startup transient, which =is> >>>>>>>>> important here, is different depending if the oscillator > >>>>>>>>> amplitude is sufficient to toggle the gate. This translates int=o> >>>>>>>>> an envelope that raises more ore less smoothly until the gate > >>>>>>>>> begins toggling, where the envelope raises more abruptly -and I > >>>>>>>>> guess that the instantaneous frequency changes. > > >>>>>>>>> I have thought of two causes for this. The first one is feedbac=k> >>>>>>>>> via the DC supply: the spikes generated by the gate switching g=et> >>>>>>>>> coupled back to the oscillator. The second one could be the > >>>>>>>>> change in input impedance seen by the oscillator -does this mak=e> >>>>>>>>> sense? The cure for #1 could be better supply bypassing. The cu=re> >>>>>>>>> for #2 a buffer stage. > > >>>>>>>>> So, what could be a good way to generate a digital signal from =an> >>>>>>>>> oscillator without loading it? Ideally I would like to preserve > >>>>>>>>> the instantaneous frequency of the unloaded startup transient. > >>>>>>>>> And: power consumption should be low, say preferably (much) les=s> >>>>>>>>> than 1 mA. Operating frequency should =A0be initially 27 MHz, b=ut> >>>>>>>>> ideally scalable up to ~1 GHz. > > >>>>>>>>> Pere > > >>>>>>>> Do you want an LC oscillator that starts instantly and coherentl=y,> >>>>>>>> with a digital clock output? We do that, with LCs at low > >>>>>>>> frequencies, and coaxial ceramic resonators at 500 MHz or so. 1 > >>>>>>>> GHz shouldn't be horribly difficult, except for the milliwatt > >>>>>>>> constraint. It's just a matter of getting the initial conditions > >>>>>>>> right. > > >>>>>>>>https://dl.dropbox.com/u/53724080/Circuits/Burst_Osc.jpg > > >>>>>>> Are you building some kind of synchronous oscillator? > > >>>>>> We use gated oscillators in our digital delay generators. When we > >>>>>> gat a rrigger, we start a clock oscillator, and count ticks to get > >>>>>> coarse delay. An analog ramp thing gives fine delay to interpolate > >>>>>> down to picoseconds. Sometimes just the LC is good enough, for sho=rt> >>>>>> delays. The coaxial resonator things are great for medium accuracy > >>>>>> and delay. he best is to use a gated LC for the clock, but > >>>>>> phase-lock it to a crystal oscillator to get longterm precision. > > >>>>>I have used ceramic coaxial resonators to build oscillators at ~433 > >>>>>MHz, and they are quite stable. > >>>>>I have also seen that you make stuff on FPGAs. IIRC there are > >>>>>interesting techniques to achieve high timing precision making use > >>>>>only of digital resources (keywords: time to digital FPGA)... > > >>>> That stuff is interesting, but we haven't done it inside an FPGA. We > >>>> don't see a big demand for TDCs these days, and a couple of people d=o> >>>> it really well. No point trying to compete with someone established =in> >>>> a small market. > > >>>> We did do a new TDC lately, at a customer's request, but we used our > >>>> old analog technique, with the FPGA just doing clocked logic. > > >>>>>> In our application > >>>>>>> an external signal influences the startup transient (think > >>>>>>> superreg. principle) and the information contained therein should > >>>>>>> be more or less preserved. > > >>>>>> OK, that's different. It's an externally quenched superregen, I > >>>>>> guess. > > >>>>>> Why not use a grounded LC and a non-inverting gain element? Or you > >>>>>> could use a tiny toroidal transformer, with a secondary winding fo=r> >>>>>> the base of a PNP transistor, to provide the gain. > > >>>>>I have used several oscillator topologies. At 800 MHz the tapped-C /=/> >>>>>L resonator plus emitter follower works ok, i.e. it is a non-inverti=ng> >>>>>topology. But the problem is more or less the same: how =A0to tap th=e> >>>>>signal out. > > >>>>>> One oscillator that I really like is an LVDS-CMOS converter chip > >>>>>> that is both the feedback gain and the comparator, with the LC > >>>>>> grounded. But that wouldn't work for your application, if I > >>>>>> understand it. > > >>>>>You mean something like the DS90C032? You mean sensing with the LVDS > >>>>>side and feeding back from the CMOS side to provide the gain? I gues=s> >>>>>that this would not work, as I need a wide linear part where the > >>>>>oscillator grows up more or less slowly... > > >>>> Yeah, if you want a clasic exponential oscillation buildup, you need=a> >>>> linear gain element, a transistor or a fast opamp or a MMIC. Given > >>>> your power budget, a transistor might be best. > > >>>> How about a powdered-iron toroid with a feedback winding for the > >>>> transistor/fet drive? The LC could be grounded. A fet would be cool, > >>>> to keep the Q up. > > >>>> Or something like this.... > > >>>>https://dl.dropbox.com/u/53724080/Circuits/Oscillators/LC_quench.JPG > > >>>I have heard, from either Rhea's oscillator book or Hayward's RF > >>>circuits book, that a Hartley oscillator like that one tends to be mor=e> >>>prone to UHF parasitic oscillations than a Colpitts. =A0If you redraw =the> >>>oscillator as a grounded-source, you'll see that the Hartley is a high > >>>pass between drain and gate (leading to more loop gain at high > >>>frequencies), where a Colpitts is a low pass. > > >>>I have, like, zero experience with this as a problem, but given who's > >>>sourcing the comments it certainly makes sense. > > >> I wouldn't call that one a Hartley; I'd call it a transformer-coupled > >> oscillator (which may have a formal name of its own?) > > >> The transformer coupling will be bad at any frequency except resonance=,> >> and the fet, into the tank, only has gain at resonance, so it should b=e> >> OK. Of course it needs details. > > >The references that I've read basically say that if it's got coils fore > >and aft then it's a Hartley, regardless of whether those coils are > >coupled or not. > > >Yes, the FET only has gain at resonance. =A0Each and every one of them, > >whether intended or not. =A0With the Hartley oscillator, the higher-than=-> >intended resonances get a better chance of hijacking the oscillator > >behavior. > > OK, rising to this here challenge here, I open my trusty copy of Radio > Engineering (Frederick Terman, 3rd edition, 1947, p 410.) He shows the > three classic oscillators as "Hartley", "Colpitts", and "Tickler > Feedback", the latter being transformer coupled. But he does show the > resonating cap in the grid winding, not the plate. > > -- > > John Larkin =A0 =A0 =A0 =A0 Highland Technology, Inc > > jlarkin at highlandtechnology dot comhttp://www.highlandtechnology.com > > Precision electronic instrumentation > Picosecond-resolution Digital Delay and Pulse generators > Custom laser drivers and controllers > Photonics and fiberoptic TTL data links > VME thermocouple, LVDT, synchro =A0 acquisition and simulation- Hide quot=ed text -> > - Show quoted text -Nice thread, (wiki calls the tickler the Armstrong.) The only RF oscillator I know is used to drive a Rb discharge lamp. It's a Hartly basically copied from an efratom lamp circuit. To Opere, I don't quite get your problem. To sense the circuit you're going to have to take a bit of energy out. This must change the Q and (thus) the resonant frequency. If it's a changing Q when you switch in your circuit.. (?) then you have to balance it out. George H.
