Forums

Low bias current opamps

Started by Jeroen November 7, 2012
On 11/8/2012 6:09 PM, Spehro Pefhany wrote:
> On Thu, 08 Nov 2012 17:31:42 -0800, the renowned miso <miso@sushi.com> > wrote: > >> On 11/8/2012 6:56 AM, Spehro Pefhany wrote: >>> On Thu, 08 Nov 2012 08:45:54 +0100, Jeroen Belleman >>> <jeroen@nospam.please> wrote: >>> >>>> >>>> I made it an integrator with a 10pF feedback capacitance. The >>>> output drifts slowly and linearly at about 17uV/s. It drifted >>>> a mere volt since yesterday afternoon! There is a plot of the >>>> voltage vs. time curve at <http://cern.ch/jeroen/tmp/chamber.gif>. >>>> The steeper part near the start is where I put something slightly >>>> radioactive nearby. >>>> >>>> Jeroen Belleman >>> >>> Interesting that the data sheet shows the part in "hermetic package" >>> to be more than 10x worse leakage (but no hermetic packages are shown, >>> just DIP and SOIC). >>> >> >> What page are you on? > > http://www.ti.com/lit/ds/symlink/lpc661.pdf > > Upper right graph on PDF page 5 (numbered page 4). "Input Bias Current > vs. Temperature". > >> The bold face limits are over temperature, so the military ("M") part >> has a higher leakage limit over temp. [100pA versus 4pA.] >> >> What I find confusing is the Ib limit on datasheet page 2. The >> industrial temp range devices will have no leakage higher than 4pA over >> temperature. But the military part can leak as much as 20pA at 25 deg C. > > Strange- maybe that limit is actually tested? I see datasheets from > as far back as 2001 that are exactly the same regarding the > above-mentioned two points. > > > Best regards, > Spehro Pefhany >
Well as you know, only the electrical test limits (in theory) can be trusted. The curves are guidelines. The story I was always told about electrical limits is the customer gets the right to return a part for a replacement if the part fails electricals. Since nobody does incoming inspection these days, that means a lot of crap gets shipped if the vendor has poor quality. [Note the manufacturers flow usually has a QA test for each lot on a sample basis to insure the test hardware wasn't fubar. QA test is probably over temperature. ] Anyway, I see your point and the datasheet doesn't make sense. I can't think of anything in a ceramic package that would cause it to leak more than plastic. I assume they don't put carbon black in this plastic package, but that could make it worse than ceramic. Some manufacturers put goop over the chip prior to the plastic going around the leadframe. I assume that goop has high resistivity.
On Thu, 08 Nov 2012 00:26:50 +0100, Jeroen <jeroen@nospam.please> wrote:

>I was playing today with a little ionization chamber amplifier, >which is an exercise in high-impedance design. My usual business >revolves around wideband RF amplifiers, so this is unfamiliar >territory for me. > >I selected an LPC661 opamp which has a specified maximum Ib of >4pA, but with a typical value stated to be 2fA. That's a very >large difference, which, I guess, is motivated by the need to >minimize testing time. It takes a while to measure fA >currents with some precision. > >It appears I got lucky: Its measured Ib comes out at an amazing >170aA! I'm impressed. I hadn't yet noticed some opamps had gotten >*that* good. > >Jeroen Belleman
Cool. I had not noticed that they had gotten that good either, but it = did not surprise me. How is the offset voltage? ?-)
On Nov 8, 11:53=A0pm, miso <m...@sushi.com> wrote:
> On 11/8/2012 6:09 PM, Spehro Pefhany wrote: > > > > > > > > > > > On Thu, 08 Nov 2012 17:31:42 -0800, the renowned miso <m...@sushi.com> > > wrote: > > >> On 11/8/2012 6:56 AM, Spehro Pefhany wrote: > >>> On Thu, 08 Nov 2012 08:45:54 +0100, Jeroen Belleman > >>> <jer...@nospam.please> wrote: > > >>>> I made it an integrator with a 10pF feedback capacitance. The > >>>> output drifts slowly and linearly at about 17uV/s. It drifted > >>>> a mere volt since yesterday afternoon! There is a plot of the > >>>> voltage vs. time curve at <http://cern.ch/jeroen/tmp/chamber.gif>. > >>>> The steeper part near the start is where I put something slightly > >>>> radioactive nearby. > > >>>> Jeroen Belleman > > >>> Interesting that the data sheet shows the part in "hermetic package" > >>> to be more than 10x worse leakage (but no hermetic packages are shown=
,
> >>> just DIP and SOIC). > > >> What page are you on? > > >http://www.ti.com/lit/ds/symlink/lpc661.pdf > > > Upper right graph on PDF page 5 (numbered page 4). "Input Bias Current > > vs. Temperature". > > >> The bold face limits are over temperature, so the military ("M") part > >> has a higher leakage limit over temp. [100pA versus 4pA.] > > >> What I find confusing is the Ib limit on datasheet page 2. The > >> industrial temp range devices will have no leakage higher than 4pA ove=
r
> >> temperature. But the military part can leak as much as 20pA at 25 deg =
C.
> > > Strange- maybe that limit is actually tested? =A0I see datasheets from > > as far back as 2001 that are exactly the same regarding the > > above-mentioned two points. > > > Best regards, > > Spehro Pefhany > > Well as you know, only the electrical test limits (in theory) can be > trusted. The curves are guidelines. The story I was always told about > electrical limits is the customer gets the right to return a part for a > replacement if the part fails electricals. Since nobody does incoming > inspection these days, that means a lot of crap gets shipped if the > vendor has poor quality. [Note the manufacturers flow usually has a QA > test for each lot on a sample basis to insure the test hardware wasn't > fubar. QA test is probably over temperature. ] > > Anyway, I see your point and the datasheet doesn't make sense. I can't > think of anything in a ceramic package that would cause it to leak more > than plastic.
Plastic: 1e16 ohms. Ceramic: 1e14 ohms. Pease says so.
> I assume they don't put carbon black in this plastic > package, but that could make it worse than ceramic. > > Some manufacturers put goop over the chip prior to the plastic going > around the leadframe. I assume that goop has high resistivity.
James Arthur
On 11/08/2012 08:31 PM, miso wrote:
> On 11/8/2012 6:56 AM, Spehro Pefhany wrote: >> On Thu, 08 Nov 2012 08:45:54 +0100, Jeroen Belleman >> <jeroen@nospam.please> wrote: >> >>> >>> I made it an integrator with a 10pF feedback capacitance. The >>> output drifts slowly and linearly at about 17uV/s. It drifted >>> a mere volt since yesterday afternoon! There is a plot of the >>> voltage vs. time curve at <http://cern.ch/jeroen/tmp/chamber.gif>. >>> The steeper part near the start is where I put something slightly >>> radioactive nearby. >>> >>> Jeroen Belleman >> >> Interesting that the data sheet shows the part in "hermetic package" >> to be more than 10x worse leakage (but no hermetic packages are shown, >> just DIP and SOIC). >> > > What page are you on? > > The bold face limits are over temperature, so the military ("M") part > has a higher leakage limit over temp. [100pA versus 4pA.] > > What I find confusing is the Ib limit on datasheet page 2. The > industrial temp range devices will have no leakage higher than 4pA over > temperature. But the military part can leak as much as 20pA at 25 deg C. >
They pound the crap out of the mil spec devices during testing, probably. Back in the JANTX days that was a real problem with some transistors--the COTS versions were more reliable because they suffered less abuse. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
> Plastic: 1e16 ohms. Ceramic: 1e14 ohms. Pease says so. > >> I assume they don't put carbon black in this plastic >> package, but that could make it worse than ceramic. >> >> Some manufacturers put goop over the chip prior to the plastic going >> around the leadframe. I assume that goop has high resistivity. > > James Arthur >
I found a spec for ceramic, which runs 1e14 to 1e16 ohm meter. Did Pease drop the units?
> http://www.theeestory.com/files/Complete_Alumina_Parametrics__rated_by_purity__in_bulk_.pdf
In a ceramic package, you generally solder the die bottom to the metal inside the package. [I think they call it a scrub. I've never that step done.] Now since the resistance is volumetric, the metal on the inside of the package certainly has a decent contact to the ceramic. Actually it approaches the ideal metal plate used in the typical description of how you define volumetric resistivity. In a plastic package, the part sits on a paddle in the leadframe, which can be isolated. But it also has contact to the plastic. Visualizing this, it seems like both packages have significant contact to the insulating material. But it is possible in a plastic package to put the chip on "glass beads." That floats the substrate contact. I don't know if that scheme is possible for ceramic packages. Obviously if we had a packaging engineer on the list it would be far better than someone who has just had chips packaged. I haven't found a spec on the plastic resistivity.
Am 10.11.2012 01:36, schrieb miso:
>> Plastic: 1e16 ohms. Ceramic: 1e14 ohms. Pease says so.
> But it is possible in a plastic package to put the chip on "glass > beads." That floats the substrate contact. I don't know if that scheme > is possible for ceramic packages. Obviously if we had a packaging > engineer on the list it would be far better than someone who has just > had chips packaged. > > I haven't found a spec on the plastic resistivity.
The sealing glass in those cheap non-sidebrazed ceramic Eproms produced so much water during fritting that it already was corrosive. regards, Gerhard
On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote:

> >Well as you know, only the electrical test limits (in theory) can be=20 >trusted. The curves are guidelines. The story I was always told about=20 >electrical limits is the customer gets the right to return a part for a=20 >replacement if the part fails electricals. Since nobody does incoming=20 >inspection these days, that means a lot of crap gets shipped if the=20 >vendor has poor quality. [Note the manufacturers flow usually has a QA=20 >test for each lot on a sample basis to insure the test hardware wasn't=20 >fubar. QA test is probably over temperature. ]
Actual testing for commercial parts is limited to basic function, often = on wafer. Industrial parts get tested at 25 C and maybe at high temp, usually after packaging, no real process difference except test failures are usually dropped back into commercial bins. Military grades require much more bookkeeping. Generally only "selected wafers" get a chance to be Military grade.
> >Anyway, I see your point and the datasheet doesn't make sense. I can't=20 >think of anything in a ceramic package that would cause it to leak more=20 >than plastic. I assume they don't put carbon black in this plastic=20 >package, but that could make it worse than ceramic. > >Some manufacturers put goop over the chip prior to the plastic going=20 >around the leadframe. I assume that goop has high resistivity. >
The goop would have to be much less expensive that package plastic or preserve exotic properties like ultra low leakage. ?-)
On 11/10/2012 9:00 PM, josephkk wrote:
> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: > >> >> Well as you know, only the electrical test limits (in theory) can be >> trusted. The curves are guidelines. The story I was always told about >> electrical limits is the customer gets the right to return a part for a >> replacement if the part fails electricals. Since nobody does incoming >> inspection these days, that means a lot of crap gets shipped if the >> vendor has poor quality. [Note the manufacturers flow usually has a QA >> test for each lot on a sample basis to insure the test hardware wasn't >> fubar. QA test is probably over temperature. ] > > Actual testing for commercial parts is limited to basic function, often on > wafer. Industrial parts get tested at 25 C and maybe at high temp, > usually after packaging, no real process difference except test failures > are usually dropped back into commercial bins. Military grades require > much more bookkeeping. Generally only "selected wafers" get a chance to > be Military grade. >> >> Anyway, I see your point and the datasheet doesn't make sense. I can't >> think of anything in a ceramic package that would cause it to leak more >> than plastic. I assume they don't put carbon black in this plastic >> package, but that could make it worse than ceramic. >> >> Some manufacturers put goop over the chip prior to the plastic going >> around the leadframe. I assume that goop has high resistivity. >> > The goop would have to be much less expensive that package plastic or > preserve exotic properties like ultra low leakage. > > ?-) >
The goop is something to do with packaging in general, not low leakage. Not everyone uses it. Wafer test is simply to save packaging parts that will fail at final test anyway. Nobody, or at least no place I ever worked, packages parts and didn't test them. Plenty can go wrong in backlap, bonding, packaging, etc. Everything with electrical limits is tested at ATE at all grades at room temp for packaged parts. If you look carefully, you may see GBD (guaranteed by design). That can mean a lot of things. If it is a capacitance at a pin, the assumption is if the wafer passed parametric testing, then the pin capacitance will be totally predictable, hence GBD. If the part has a reference in it. the drift at elevated temperature in theory can correlate to the drift at cold temperature. All the tests have guardbands. Depending on the company, some test wide at wafer then accept the rejects at final. You do this is the chips are expensive. That is, you are willing to spend some money packaging borderline parts in order to get product to sell. The other scheme is to test tight at wafer and then have looser limts as the part goes down the test flow. That is, the test limits are tighter than the datasheet spec at wafer. At QA, the test limits are exactly what is on the datasheet less the bench to ATE correlation error. That is, somebody should be able to bench test the part and have it pass publsihed electricals. If you are not familiar with parameter wafer testing, the devices on the test pattern have to meet test criteria before product wafer testing is done. If something fails the parametric test, then a decision is made to see if the parts are OK to sell in terms of reliability. That is, say the oxide breakdown was out of spec. You would probably reject the wafer just because you don't trust it. Put if a parameter is off on a device you don't use (say epifet), then the wafer can go off to production wafer test.
On 11/12/2012 12:22 AM, miso wrote:
> On 11/10/2012 9:00 PM, josephkk wrote: >> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: >> >>> >>> Well as you know, only the electrical test limits (in theory) can be >>> trusted. The curves are guidelines. The story I was always told about >>> electrical limits is the customer gets the right to return a part for a >>> replacement if the part fails electricals. Since nobody does incoming >>> inspection these days, that means a lot of crap gets shipped if the >>> vendor has poor quality. [Note the manufacturers flow usually has a QA >>> test for each lot on a sample basis to insure the test hardware wasn't >>> fubar. QA test is probably over temperature. ] >> >> Actual testing for commercial parts is limited to basic function, >> often on >> wafer. Industrial parts get tested at 25 C and maybe at high temp, >> usually after packaging, no real process difference except test failures >> are usually dropped back into commercial bins. Military grades require >> much more bookkeeping. Generally only "selected wafers" get a chance to >> be Military grade. >>> >>> Anyway, I see your point and the datasheet doesn't make sense. I can't >>> think of anything in a ceramic package that would cause it to leak more >>> than plastic. I assume they don't put carbon black in this plastic >>> package, but that could make it worse than ceramic. >>> >>> Some manufacturers put goop over the chip prior to the plastic going >>> around the leadframe. I assume that goop has high resistivity. >>> >> The goop would have to be much less expensive that package plastic or >> preserve exotic properties like ultra low leakage. >> >> ?-) >> > > The goop is something to do with packaging in general, not low leakage. > Not everyone uses it. > > Wafer test is simply to save packaging parts that will fail at final > test anyway. Nobody, or at least no place I ever worked, packages parts > and didn't test them. Plenty can go wrong in backlap, bonding, > packaging, etc. > > Everything with electrical limits is tested at ATE at all grades at room > temp for packaged parts. If you look carefully, you may see GBD > (guaranteed by design). That can mean a lot of things. If it is a > capacitance at a pin, the assumption is if the wafer passed parametric > testing, then the pin capacitance will be totally predictable, hence > GBD. If the part has a reference in it. the drift at elevated > temperature in theory can correlate to the drift at cold temperature. > > All the tests have guardbands. Depending on the company, some test wide > at wafer then accept the rejects at final. You do this is the chips are > expensive. That is, you are willing to spend some money packaging > borderline parts in order to get product to sell. The other scheme is to > test tight at wafer and then have looser limts as the part goes down the > test flow. That is, the test limits are tighter than the datasheet spec > at wafer. At QA, the test limits are exactly what is on the datasheet > less the bench to ATE correlation error. That is, somebody should be > able to bench test the part and have it pass publsihed electricals. > > If you are not familiar with parameter wafer testing, the devices on the > test pattern have to meet test criteria before product wafer testing is > done. If something fails the parametric test, then a decision is made to > see if the parts are OK to sell in terms of reliability. That is, say > the oxide breakdown was out of spec. You would probably reject the wafer > just because you don't trust it. Put if a parameter is off on a device > you don't use (say epifet), then the wafer can go off to production > wafer test. >
Interesting, thanks. IIRC the goop is generally RTV silicone, which greatly reduces die stress due to epoxy shrinkage and temperature cycling. That's often recommended for people who want to pot their circuits in epoxy--a layer of RTV underneath prevents stuff getting torn off or cracking when the epoxy cures. OTOH for chips, the RTV will make the package floppier, which might increase die stress from external effects. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 11/12/2012 12:22 AM, miso wrote: >> On 11/10/2012 9:00 PM, josephkk wrote: >>> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: >>> >>>> >>>> Well as you know, only the electrical test limits (in theory) can be >>>> trusted. The curves are guidelines. The story I was always told about >>>> electrical limits is the customer gets the right to return a part for a >>>> replacement if the part fails electricals. Since nobody does incoming >>>> inspection these days, that means a lot of crap gets shipped if the >>>> vendor has poor quality. [Note the manufacturers flow usually has a QA >>>> test for each lot on a sample basis to insure the test hardware wasn't >>>> fubar. QA test is probably over temperature. ] >>> >>> Actual testing for commercial parts is limited to basic function, >>> often on >>> wafer. Industrial parts get tested at 25 C and maybe at high temp, >>> usually after packaging, no real process difference except test failures >>> are usually dropped back into commercial bins. Military grades require >>> much more bookkeeping. Generally only "selected wafers" get a chance to >>> be Military grade. >>>> >>>> Anyway, I see your point and the datasheet doesn't make sense. I can't >>>> think of anything in a ceramic package that would cause it to leak more >>>> than plastic. I assume they don't put carbon black in this plastic >>>> package, but that could make it worse than ceramic. >>>> >>>> Some manufacturers put goop over the chip prior to the plastic going >>>> around the leadframe. I assume that goop has high resistivity. >>>> >>> The goop would have to be much less expensive that package plastic or >>> preserve exotic properties like ultra low leakage. >>> >>> ?-) >>> >> >> The goop is something to do with packaging in general, not low leakage. >> Not everyone uses it. >> >> Wafer test is simply to save packaging parts that will fail at final >> test anyway. Nobody, or at least no place I ever worked, packages parts >> and didn't test them. Plenty can go wrong in backlap, bonding, >> packaging, etc. >> >> Everything with electrical limits is tested at ATE at all grades at room >> temp for packaged parts. If you look carefully, you may see GBD >> (guaranteed by design). That can mean a lot of things. If it is a >> capacitance at a pin, the assumption is if the wafer passed parametric >> testing, then the pin capacitance will be totally predictable, hence >> GBD. If the part has a reference in it. the drift at elevated >> temperature in theory can correlate to the drift at cold temperature. >> >> All the tests have guardbands. Depending on the company, some test wide >> at wafer then accept the rejects at final. You do this is the chips are >> expensive. That is, you are willing to spend some money packaging >> borderline parts in order to get product to sell. The other scheme is to >> test tight at wafer and then have looser limts as the part goes down the >> test flow. That is, the test limits are tighter than the datasheet spec >> at wafer. At QA, the test limits are exactly what is on the datasheet >> less the bench to ATE correlation error. That is, somebody should be >> able to bench test the part and have it pass publsihed electricals. >> >> If you are not familiar with parameter wafer testing, the devices on the >> test pattern have to meet test criteria before product wafer testing is >> done. If something fails the parametric test, then a decision is made to >> see if the parts are OK to sell in terms of reliability. That is, say >> the oxide breakdown was out of spec. You would probably reject the wafer >> just because you don't trust it. Put if a parameter is off on a device >> you don't use (say epifet), then the wafer can go off to production >> wafer test. >> > >Interesting, thanks. > >IIRC the goop is generally RTV silicone, which greatly reduces die >stress due to epoxy shrinkage and temperature cycling. That's often >recommended for people who want to pot their circuits in epoxy--a layer >of RTV underneath prevents stuff getting torn off or cracking when the >epoxy cures. OTOH for chips, the RTV will make the package floppier, >which might increase die stress from external effects. > >Cheers > >Phil Hobbs
Lots of chip packages are so thin there can't be room for a filler inside. Fun: push here and there on an opamp or a DAC with a pencil point and watch the DC offset change. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators