Forums

Low RDSon Logic CMOS Gate

Started by Klaus Kragelund October 1, 2012
On Thu, 04 Oct 2012 09:43:18 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Thu, 04 Oct 2012 09:04:29 -0700, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Thu, 04 Oct 2012 08:38:20 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>>On Wed, 3 Oct 2012 21:14:26 -0700 (PDT), dagmargoodboat@yahoo.com >>>wrote: >>> >>>>On Oct 3, 1:48&#2013266080;pm, John Larkin <jlar...@highlandtechnology.com> wrote: >>>[snip] >>>>> >>>>> Even a break-before-make CMOS analog switch has several CMOS gate >>>>> driver sections, each of which will have shoot-through. Then the final >>>>> switch capacitance behaves just like a Cpd effect, wasting energy on >>>>> every transition. No free lunch. >>>> >>>>The lunch doesn't have to be free. If it's smaller, cheaper, and all >>>>wrapped up in a nicer box, that counts too. >>> >>>An interesting thought sprung into my head. The driver sections don't >>>have to have shoot-thru, they can be time staggered all the way back >>>to the basic on-off control. I'll have to implement that in my next >>>H-bridge controller ;-) >>> >>> ...Jim Thompson >> >>If they switch, they have to at least charge node capacitances. If a >>chip has a narrow specified Vcc range, I guess you can avoid overlap >>fet conduction, at the cost of speed. > >Nope, not necessary. Ask Klaus. I sent him my whole chip design... >minus customer-identifying information. Of course YOU are not allowed >to see it >:-) > >>
You have a CMOS gate design with zero node capacitances? I would indeed like to see that. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Wed, 3 Oct 2012 21:34:46 -0700 (PDT), dagmargoodboat@yahoo.com wrote:

>On Oct 3, 1:15&#2013266080;pm, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >wrote: >> On Tue, 2 Oct 2012 19:43:44 -0700 (PDT), dagmargoodb...@yahoo.com wrote: >> >On Oct 1, 10:09&#2013266080;pm, "Vladimir Vassilevsky" <nos...@nowhere.com> wrote: >> >> "John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in message >> >> >>news:n5bk68h59kckkcmb8ntr5ecfauefjkmq6l@4ax.com... >> >> >> > If a CMOS gate's input is roughly midway between Vcc and ground, both >> >> > p-channel and n-channel fets can be partially turned on in the front >> >> > end. >> >> >> This problem is greatly overstated. >> >> While ago I tested static cross conduction of HCT04 gate powered at +5V. >> >> The worst case was about 4mA, at 0.9V at the input. >> >> >> Vladimir Vassilevsky >> >> DSP and Mixed Signal Consultantwww.abvolt.com >> >> >I've destroyed 74AC parts that way. &#2013266080;Smoked 'em. >> >> HCT stuff isn't tuned for speed so has little crossover current (none, >> ideally). &#2013266080;AC logic is a whole different kettle. &#2013266080;Better decouple AC gates >> well. &#2013266080; ;-) > >I was experimenting using one as a VHF amplifier. That works well, >until the smoke comes out. Another guy put a resistor in the supply >line with some success.
Right. AC has a significant and intentional crossover current for speed.
>I switched to 'HC. Cool as a cucumber, and it just worked.
HC does not.
On Thu, 4 Oct 2012 04:43:12 -0700 (PDT), Klaus Kragelund
<klauskvik@hotmail.com> wrote:

>On Thursday, October 4, 2012 1:00:39 PM UTC+2, Fred Bartoli wrote: >> Jon Kirwan a &#2013265929;crit : >> >> > On Thu, 4 Oct 2012 01:12:24 -0700 (PDT), Klaus Kragelund >> >> > <klauskvik@hotmail.com> wrote: >> >> > >> >> >> Some measurements of supply current: >> >> >> >> >> >> For NC7SZ14: >> >> >> >> >> >> 100kHz, 3 gates in parallel, one gate feeding the 3 gates >> >> >> for fast switching of inputs, no output load: >> >> >> >> >> >> 3.3V, 366uA >> >> >> 5V, 1400uA >> >> >> >> >> >> 1MHz: >> >> >> >> >> >> 3V3,1280uA >> >> >> 5V, 3100uA >> >> > >> >> > Linear assumption, then: >> >> > >> >> > 3.3V: I = 265uA + 1.02uA*f (in kHz) >> >> > 5.0V: I = 1210uA + 1.89uA*f (in kHz) >> >> > >> >> > Jon >> >> >> >> Which seems a lot... >> >> Also, the "static" (1210uA) current is way too big. >> >> >> >> 1.89uA/kHz -> 1.89nC/switch event and a *big* 380pF Cpd under 5V >> >> >> >> 380pF/4 gates, mean 95pF/gate which is 3 time the Fairchild figure... >> >> >> > >The static consumption is unmeaserable (or at least below 1uA) > >Regarding the high consumption, they are in parallel, so might be cross conduction from device to device if propagation times are no equal > >I'll dig further and post back here > >Cheers > >Klaus
Are your input edges fast? Thanks for the data. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Thu, 04 Oct 2012 09:52:22 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Thu, 04 Oct 2012 09:43:18 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>On Thu, 04 Oct 2012 09:04:29 -0700, John Larkin >><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Thu, 04 Oct 2012 08:38:20 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> >>>>On Wed, 3 Oct 2012 21:14:26 -0700 (PDT), dagmargoodboat@yahoo.com >>>>wrote: >>>> >>>>>On Oct 3, 1:48&#2013266080;pm, John Larkin <jlar...@highlandtechnology.com> wrote: >>>>[snip] >>>>>> >>>>>> Even a break-before-make CMOS analog switch has several CMOS gate >>>>>> driver sections, each of which will have shoot-through. Then the final >>>>>> switch capacitance behaves just like a Cpd effect, wasting energy on >>>>>> every transition. No free lunch. >>>>> >>>>>The lunch doesn't have to be free. If it's smaller, cheaper, and all >>>>>wrapped up in a nicer box, that counts too. >>>> >>>>An interesting thought sprung into my head. The driver sections don't >>>>have to have shoot-thru, they can be time staggered all the way back >>>>to the basic on-off control. I'll have to implement that in my next >>>>H-bridge controller ;-) >>>> >>>> ...Jim Thompson >>> >>>If they switch, they have to at least charge node capacitances. If a >>>chip has a narrow specified Vcc range, I guess you can avoid overlap >>>fet conduction, at the cost of speed. >> >>Nope, not necessary. Ask Klaus. I sent him my whole chip design... >>minus customer-identifying information. Of course YOU are not allowed >>to see it >:-) >> >>> > >You have a CMOS gate design with zero node capacitances? I would >indeed like to see that.
On-chip nodal capacitances are quite small... often in the low femto-Farad range. Where you get hurt is when you drive a pin to the outside world. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Klaus Kragelund a &#2013265929;crit :
> On Thursday, October 4, 2012 1:00:39 PM UTC+2, Fred Bartoli wrote: >> Jon Kirwan a &#2013265929;crit : >> >>> On Thu, 4 Oct 2012 01:12:24 -0700 (PDT), Klaus Kragelund >>> <klauskvik@hotmail.com> wrote: >>>> Some measurements of supply current: >>>> For NC7SZ14: >>>> 100kHz, 3 gates in parallel, one gate feeding the 3 gates >>>> for fast switching of inputs, no output load: >>>> 3.3V, 366uA >>>> 5V, 1400uA >>>> 1MHz: >>>> 3V3,1280uA >>>> 5V, 3100uA >>> Linear assumption, then: >>> 3.3V: I = 265uA + 1.02uA*f (in kHz) >>> 5.0V: I = 1210uA + 1.89uA*f (in kHz) >>> Jon >> >> >> Which seems a lot... >> >> Also, the "static" (1210uA) current is way too big. >> >> >> >> 1.89uA/kHz -> 1.89nC/switch event and a *big* 380pF Cpd under 5V >> >> >> >> 380pF/4 gates, mean 95pF/gate which is 3 time the Fairchild figure... >> >> >> > > The static consumption is unmeaserable (or at least below 1uA) >
Of course the static current is that small. That's why I did put quotes. I meant the Jon_fitted_current_at_frequency_zero ...
> Regarding the high consumption, they are in parallel, so might be cross conduction from device to device if propagation times are no equal >
My thought too.
> I'll dig further and post back here
If you have time, more than 2 frequency points will be interesting because of the big "F=0 current" ... -- Thanks, Fred.
John Larkin a &#2013265929;crit :
> On Mon, 01 Oct 2012 21:39:48 +0200, Fred Bartoli <" "> wrote: > >> Klaus Kragelund a &#2013265929;crit : >>> Hi >>> >>> I need a CMOS gate with low voltage drop at about 30mA current source and sink. The tiny logic NL27WZ14 has 600mV drop at 32mA which equates to 18ohm RDS on. >>> >>> I am searching for a device with less than 5-10 ohms and it would need to be ok to parallel to get lower resistance. Also, it must not have to much crossover shoot-through (so probably schmitt trigger type) and must have low dissipation at high operational frequency (1-10MHz) >>> >>> Any one have a part in mind? >>> >>> Thanks >>> >>> Klaus >> Mucho thanks for posting this... >> >> In an attempt to answer I had a look at a recent design and noticed that >> a 5V powered LVC14 escaped all the design reviews :-( >> >> It survived all the stress test: 27MHz switching, with PCB temp=100&#2013266096;C >> while driving a 250pF Ciss Mosfet... >> >> How did you know ?-) > > Abs max Vcc is 6.5. What's your problem? > >
I was using that one: http://www.nxp.com/products/logic/schmitt_triggers/74LVC14ABQ.html You're right, for the Abs max, but its normal operation range is stated as up to 3.6V -- Thanks, Fred.
On Fri, 05 Oct 2012 00:14:22 +0200, Fred Bartoli <" "> wrote:

>John Larkin a &#2013265929;crit : >> On Mon, 01 Oct 2012 21:39:48 +0200, Fred Bartoli <" "> wrote: >> >>> Klaus Kragelund a &#2013265929;crit : >>>> Hi >>>> >>>> I need a CMOS gate with low voltage drop at about 30mA current source and sink. The tiny logic NL27WZ14 has 600mV drop at 32mA which equates to 18ohm RDS on. >>>> >>>> I am searching for a device with less than 5-10 ohms and it would need to be ok to parallel to get lower resistance. Also, it must not have to much crossover shoot-through (so probably schmitt trigger type) and must have low dissipation at high operational frequency (1-10MHz) >>>> >>>> Any one have a part in mind? >>>> >>>> Thanks >>>> >>>> Klaus >>> Mucho thanks for posting this... >>> >>> In an attempt to answer I had a look at a recent design and noticed that >>> a 5V powered LVC14 escaped all the design reviews :-( >>> >>> It survived all the stress test: 27MHz switching, with PCB temp=100&#2013266096;C >>> while driving a 250pF Ciss Mosfet... >>> >>> How did you know ?-) >> >> Abs max Vcc is 6.5. What's your problem? >> >> > >I was using that one: > >http://www.nxp.com/products/logic/schmitt_triggers/74LVC14ABQ.html > >You're right, for the Abs max, but its normal operation range is stated >as up to 3.6V
These little parts just get better as Vcc goes up. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Thu, 04 Oct 2012 11:41:38 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Thu, 04 Oct 2012 09:52:22 -0700, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Thu, 04 Oct 2012 09:43:18 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>>On Thu, 04 Oct 2012 09:04:29 -0700, John Larkin >>><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Thu, 04 Oct 2012 08:38:20 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> >>>>>On Wed, 3 Oct 2012 21:14:26 -0700 (PDT), dagmargoodboat@yahoo.com >>>>>wrote: >>>>> >>>>>>On Oct 3, 1:48&#2013266080;pm, John Larkin <jlar...@highlandtechnology.com> wrote: >>>>>[snip] >>>>>>> >>>>>>> Even a break-before-make CMOS analog switch has several CMOS gate >>>>>>> driver sections, each of which will have shoot-through. Then the final >>>>>>> switch capacitance behaves just like a Cpd effect, wasting energy on >>>>>>> every transition. No free lunch. >>>>>> >>>>>>The lunch doesn't have to be free. If it's smaller, cheaper, and all >>>>>>wrapped up in a nicer box, that counts too. >>>>> >>>>>An interesting thought sprung into my head. The driver sections don't >>>>>have to have shoot-thru, they can be time staggered all the way back >>>>>to the basic on-off control. I'll have to implement that in my next >>>>>H-bridge controller ;-) >>>>> >>>>> ...Jim Thompson >>>> >>>>If they switch, they have to at least charge node capacitances. If a >>>>chip has a narrow specified Vcc range, I guess you can avoid overlap >>>>fet conduction, at the cost of speed. >>> >>>Nope, not necessary. Ask Klaus. I sent him my whole chip design... >>>minus customer-identifying information. Of course YOU are not allowed >>>to see it >:-) >>> >>>> >> >>You have a CMOS gate design with zero node capacitances? I would >>indeed like to see that. > >On-chip nodal capacitances are quite small... often in the low >femto-Farad range. Where you get hurt is when you drive a pin to the >outside world. > > ...Jim Thompson
What's the total node capacitance of a p-fet+n-fet drain pair feeding a p-fet+n-fet gate pair, in something like HC? -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Thu, 04 Oct 2012 20:07:02 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Thu, 04 Oct 2012 11:41:38 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>On Thu, 04 Oct 2012 09:52:22 -0700, John Larkin >><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Thu, 04 Oct 2012 09:43:18 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> >>>>On Thu, 04 Oct 2012 09:04:29 -0700, John Larkin >>>><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Thu, 04 Oct 2012 08:38:20 -0700, Jim Thompson >>>>><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>>> >>>>>>On Wed, 3 Oct 2012 21:14:26 -0700 (PDT), dagmargoodboat@yahoo.com >>>>>>wrote: >>>>>> >>>>>>>On Oct 3, 1:48&#2013266080;pm, John Larkin <jlar...@highlandtechnology.com> wrote: >>>>>>[snip] >>>>>>>> >>>>>>>> Even a break-before-make CMOS analog switch has several CMOS gate >>>>>>>> driver sections, each of which will have shoot-through. Then the final >>>>>>>> switch capacitance behaves just like a Cpd effect, wasting energy on >>>>>>>> every transition. No free lunch. >>>>>>> >>>>>>>The lunch doesn't have to be free. If it's smaller, cheaper, and all >>>>>>>wrapped up in a nicer box, that counts too. >>>>>> >>>>>>An interesting thought sprung into my head. The driver sections don't >>>>>>have to have shoot-thru, they can be time staggered all the way back >>>>>>to the basic on-off control. I'll have to implement that in my next >>>>>>H-bridge controller ;-) >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>>If they switch, they have to at least charge node capacitances. If a >>>>>chip has a narrow specified Vcc range, I guess you can avoid overlap >>>>>fet conduction, at the cost of speed. >>>> >>>>Nope, not necessary. Ask Klaus. I sent him my whole chip design... >>>>minus customer-identifying information. Of course YOU are not allowed >>>>to see it >:-) >>>> >>>>> >>> >>>You have a CMOS gate design with zero node capacitances? I would >>>indeed like to see that. >> >>On-chip nodal capacitances are quite small... often in the low >>femto-Farad range. Where you get hurt is when you drive a pin to the >>outside world. >> >> ...Jim Thompson > >What's the total node capacitance of a p-fet+n-fet drain pair feeding >a p-fet+n-fet gate pair, in something like HC?
Do you mean something like an 'HC04? I don't know. I'll have to look it up. I last did 'HC' stuff for Motorola/ON-Semi in 1997 when I redid all their logic parts to be compatible with Chartered Semiconductor processing. It'll be large. 'HC' is basically 0.8um feature size, which makes for huge devices. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Thu, 04 Oct 2012 20:07:02 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

[snip]
> >What's the total node capacitance of a p-fet+n-fet drain pair feeding >a p-fet+n-fet gate pair, in something like HC?
I started to look that up, then realized that all the information you need is right there on a 74HC04 data sheet ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.