Forums

Deglitching a DAC

Started by Spehro Pefhany July 17, 2012
John Larkin wrote:


> > Sure. But I have an idea for a gated deglitcher, but it wouldn't > handle big voltage steps. It might work if Speff can digitally > slew-rate-limit the dac steps.
What I'm trying to say is you CAN'T slew-rate limit it from the digital side, as when you cross one of those major boundaries, you get a BIG glitch, maybe 1/4 scale of the whole DAC range, and lasting for tens to hundreds of ns. Now, some DACs are not bad, and the worst-case glitch is quite reasonable, but some others have horrible glitch magnitude. Jon
Spehro Pefhany wrote:


> Nope. Although I suppose I could declare some codes personna > (numbera?) non grata and avoid the worst of them at the expense of a > bit or two resolution. 8-(
I'm sure it varies by the exact DAC construction, but my experience is the glitches are not related to specific codes, but specific transitions. So, if there is a big glitch across the 1/4 scale transition, then ANY transition that crosses the boundary creates a roughly similar glitch. This would be when the N-2 bit changes state. So, my understanding is that eliminating the two states on either side of the transition won't get rid of the glitch. Slowly creeping up on this transition also won't get rid of the glitch. It seems that lacking a DAC which has been designed from the ground up to minimize glitch energy, then some sort of sample/hold circuit would be the only solution that actually works. Jon
On Thu, 19 Jul 2012 15:26:18 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Thu, 19 Jul 2012 12:19:20 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>On Thu, 19 Jul 2012 14:51:51 -0400, Spehro Pefhany >><speffSNIP@interlogDOTyou.knowwhat> wrote: >> >>> >>>>>in the fast converter). >>>> >>>>Glitch width = ? >>>> >>>>Bit time = ? >>>> >>>>Not clear from your "every few ns" comment :-) >>>> >>>> ...Jim Thompson >>> >>>http://www.speff.com/glitch.png >>> >>>The real kicker is to do this without affecting the ppm-level DC >>>stability of the signal chain. >> >>That's with your filter. What does it look like, step plus glitch, >>unfiltered? >> >> ...Jim Thompson > >That's unfiltered, from the DAC output buffer op-amp, with a single >LSB step (not visible on that scale).
How much time until the next bit? (My CMOS DAC's, tucked in my custom ASIC's, sure look better than that :-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Spehro Pefhany wrote:

> On Thu, 19 Jul 2012 06:29:59 GMT, Jan Panteltje > <pNaonStpealmtje@yahoo.com> wrote: > > >>On a sunny day (Wed, 18 Jul 2012 17:18:23 -0400) it happened Spehro Pefhany >><speffSNIP@interlogDOTyou.knowwhat> wrote in >><o06e08hrvjuuthplmih2qij2pabo7oo9p0@4ax.com>: >> >> >>>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> >>>wrote: >>> >>> >>>>Spehro Pefhany wrote: >>>> >>>>>On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>>>><sgoldHAM@alum.mit.edu> wrote: >>>>> >>>>> >>>>>>Message off into the ether. >>>>>> >>>>>>What kind of logic are you using to drive the DAC? Is there any >>>>>>relationship to the driving edge speed, or does it depend only >>>>>>on the internal update signal after the data are in? >>>>> >>>>>It's doing pretty much what the data sheet says it should do, >>>>>unfortunately. The glitching happens with the update. >>>>> >>>> >>>>You've got to re-sample it outside the chip. There is no way to push >>>>things down to ppm levels on the same chip with the digital stuff on >>>>there. Mainly because there's lead inductance, chatter across the >>>>substrate, finite metal layer conductivity, inductive coupling, and all >>>>this fun stuff. I'd consider a diff-output DAC followed by a >>>>differential S&H. Decouple and bypass the supplies really well. Ferrite >>>>beads and 0402 or 0603 caps are your friends here. >>> >>>The irritating thing is that it's directly related to the switches.. >>>and it ought to be possible to match that stuff on the chip to very >>>close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV >>>glitches on a chip (datasheet claim, so ideal conditions) on a chip >>>with ~100nV of RMS output noise and 1ppm linearity seems... a bit >>>much. >>> >>>http://www.speff.com/glitch.png >> >>Maybe the opposite can be done, open a series switch on the spikes. >>If you have the switch signal and it is early, use it to open a switch >>in the output for a few ns (longer than the transients). >>For the rest eitehr way it is homework, drive impedance, switch resistance, >>RC time, maybe need buffers, noise level, opamp choices. > > > Yeah, it is homework and I'd like to cheat. > >
At least you're honest :) Jamie
> A simple slew-rate limiter circuit might make a pretty good > deglitcher. Sort of like a lowpass filter, but with more precise > settling behavior. > > > >
You may be onto something here, but slew rate symmetry would be important. I would say an OTA with cap load is more of what you want. gm*C sets the BW, and output stage current sets the slew rate.
On Thu, 19 Jul 2012 14:55:03 -0500, Jon Elson <jmelson@wustl.edu>
wrote:

>John Larkin wrote: > > >> >> Sure. But I have an idea for a gated deglitcher, but it wouldn't >> handle big voltage steps. It might work if Speff can digitally >> slew-rate-limit the dac steps. >What I'm trying to say is you CAN'T slew-rate limit it from the >digital side,
I can't? Of course I can. The math is simple. as when you cross one of those major boundaries, you
>get a BIG glitch, maybe 1/4 scale of the whole DAC range, and lasting >for tens to hundreds of ns.
Speff's glitch pics aren't anything like that bad. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Thu, 19 Jul 2012 14:38:37 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Thu, 19 Jul 2012 11:07:56 -0700, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>On Thu, 19 Jul 2012 13:26:39 -0400, Spehro Pefhany >><speffSNIP@interlogDOTyou.knowwhat> wrote: >> >>>On Thu, 19 Jul 2012 07:29:19 -0700, John Larkin >>><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer >>>><robertbaer@localnet.com> wrote: >>>> >>>>>Spehro Pefhany wrote: >>>>>> Any clever ideas on getting rid of glitches in a high precision DAC >>>>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>>> and I'd like to keep the glitches (especially variation in glitches) >>>>>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >>>>>> switch? >>>>>> >>>>> Run two "in parallel", take only the glitches from one, invert and >>>>>sum that wit output from the other. >>>> >>>>Isn't that equivalent to lowpass filtering a single DAC? Just a lot >>>>more expensive >>> >>>Well, if I high-passed the (variable with code) height glitches from >>>one DAC and they closely matched the glitches from the other (over >>>different codes), I could subtract the two, and indeed it might be >>>much better than a LPF. >> >>How is that better than highpass filtering the glitch from the same >>dac, and subtracting that? I believe I've just described a lowpass >>filter. > >Yup, absolutely right. Dunh. > >>A fast clocked 8-bit DAC could cancel every glitch from the main dac. >>The lookup table would be many gigabytes, and sort of hard to >>generate. > >2^20-1 bytes = 1Mbyte per time slice, so with 256 time slices, >256Mbytes clocked out every few ns at the transitions. Kind of heroic, >but maybe possible. The glitches are currently ~ 10 bits (1000 LSBs) >high though, so 8 bits might be a problem (as might be LF noise/drift >in the fast converter).
Your glitch lasts about a microsecond, and peaks at 40 millivolts. Assume an 8-bit DAC with +-50 mV range. An LSB of the correction DAC is 100 uV, so it can cancel the glitch to within 100 uV, about a 400:1 improvement. Of course, you need a time sequence of points; say we clock the correction DAC at 64 MHz, so we need a burst of 64 points for 1 usec at each main DAC load, to generate the anti-glitch waveform. If the lookup table contains every possible code transition of the main DAC, that's a mere 64 * 2^40 bytes of lookup table. Next, we calculate how long it will take to generate the correction table... Oh, seems to me that the glitch you posted is a lot bigger than the 1.4 nV-sec glitch impulse on the AD5791 web page sheet. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
John Larkin wrote:
> > On Thu, 19 Jul 2012 14:38:37 -0400, Spehro Pefhany > <speffSNIP@interlogDOTyou.knowwhat> wrote: > > >On Thu, 19 Jul 2012 11:07:56 -0700, John Larkin > ><jlarkin@highlandtechnology.com> wrote: > > > >>On Thu, 19 Jul 2012 13:26:39 -0400, Spehro Pefhany > >><speffSNIP@interlogDOTyou.knowwhat> wrote: > >> > >>>On Thu, 19 Jul 2012 07:29:19 -0700, John Larkin > >>><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>> > >>>>On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer > >>>><robertbaer@localnet.com> wrote: > >>>> > >>>>>Spehro Pefhany wrote: > >>>>>> Any clever ideas on getting rid of glitches in a high precision DAC > >>>>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, > >>>>>> and I'd like to keep the glitches (especially variation in glitches) > >>>>>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection > >>>>>> switch? > >>>>>> > >>>>> Run two "in parallel", take only the glitches from one, invert and > >>>>>sum that wit output from the other. > >>>> > >>>>Isn't that equivalent to lowpass filtering a single DAC? Just a lot > >>>>more expensive > >>> > >>>Well, if I high-passed the (variable with code) height glitches from > >>>one DAC and they closely matched the glitches from the other (over > >>>different codes), I could subtract the two, and indeed it might be > >>>much better than a LPF. > >> > >>How is that better than highpass filtering the glitch from the same > >>dac, and subtracting that? I believe I've just described a lowpass > >>filter. > > > >Yup, absolutely right. Dunh. > > > >>A fast clocked 8-bit DAC could cancel every glitch from the main dac. > >>The lookup table would be many gigabytes, and sort of hard to > >>generate. > > > >2^20-1 bytes = 1Mbyte per time slice, so with 256 time slices, > >256Mbytes clocked out every few ns at the transitions. Kind of heroic, > >but maybe possible. The glitches are currently ~ 10 bits (1000 LSBs) > >high though, so 8 bits might be a problem (as might be LF noise/drift > >in the fast converter). > > Your glitch lasts about a microsecond, and peaks at 40 millivolts. > Assume an 8-bit DAC with +-50 mV range. An LSB of the correction DAC > is 100 uV, so it can cancel the glitch to within 100 uV, about a 400:1 > improvement. > > Of course, you need a time sequence of points; say we clock the > correction DAC at 64 MHz, so we need a burst of 64 points for 1 usec > at each main DAC load, to generate the anti-glitch waveform. > > If the lookup table contains every possible code transition of the > main DAC, that's a mere 64 * 2^40 bytes of lookup table. > > Next, we calculate how long it will take to generate the correction > table...
For each value of T. ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
John Larkin wrote:
> On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer > <robertbaer@localnet.com> wrote: > >> Spehro Pefhany wrote: >>> Any clever ideas on getting rid of glitches in a high precision DAC >>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>> and I'd like to keep the glitches (especially variation in glitches) >>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >>> switch? >>> >> Run two "in parallel", take only the glitches from one, invert and >> sum that wit output from the other. > > Isn't that equivalent to lowpass filtering a single DAC? Just a lot > more expensive > >
Not if the spikes are "inband" or the data BW precludes normal filtering (did anybody say the dreaded sampling "N" word?).
On Thu, 19 Jul 2012 19:40:28 -0700, the renowned John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:


>Oh, seems to me that the glitch you posted is a lot bigger than the >1.4 nV-sec glitch impulse on the AD5791 web page sheet.
The small print says 3.1 nV-sec typical for +/-10V reference. I get about 4.2 nV-sec from the graph, give or take 15% or so. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com