Forums

Deglitching a DAC

Started by Spehro Pefhany July 17, 2012
On Thu, 19 Jul 2012 12:35:41 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

> > >How about this: > >Ordinary two op amp closed loop T/H, with a resistor and a couple of >Schottky diodes to prevent the input amp from railing, dual-gate MOSFET
You mean close the loop around both op-amps with the RC in there? I guess that might need some thought to guarantee stability. The diode leakage shouldn't matter much since it's only got a few mV across it.
>connected S+G2 to the first op amp output, D to the hold cap, G1 is the >track/hold control. Drive G1 negative during the glitch using an open >collector with a resistor to S so that it returns to S potential while >on.
What's the advantage of that over driving G1 with a digital signal of, say +10/-5V? (BTW, and thanks, Phil, one thing that I'd forgotten since the last time I used a dual gate MOSFET it was a little metal can with a spring clip around the leads-- these things are depletion mode, so if you need a _small_ depletion mode MOSFET even with one gate, they're a possibility).
On Thu, 19 Jul 2012 16:48:23 GMT, Jan Panteltje
<pNaonStpealmtje@yahoo.com> wrote:

>On a sunny day (Thu, 19 Jul 2012 12:12:50 -0400) it happened Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote in ><ffcg081efvnqjrmhn8vuqpbdttkdj4nrjp@4ax.com>: > >>>>http://www.speff.com/glitch.png >>> >>>Maybe the opposite can be done, open a series switch on the spikes. >>>If you have the switch signal and it is early, use it to open a switch >>>in the output for a few ns (longer than the transients). >>>For the rest eitehr way it is homework, drive impedance, switch resistance, >>>RC time, maybe need buffers, noise level, opamp choices. >> >>Yeah, it is homework and I'd like to cheat. > >From that glitch.png loks like you could open a switch for the first 2 uS. >74HC4053 or something like that (16) is about 180 Ohm.
A 4053 has a huge charge injection glitch, which will vary with signal voltage levels and temperature and supply voltages.
>What is the drive impedance? >Lowpass never works for these things.
Why not? -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Thu, 19 Jul 2012 13:26:39 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Thu, 19 Jul 2012 07:29:19 -0700, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer >><robertbaer@localnet.com> wrote: >> >>>Spehro Pefhany wrote: >>>> Any clever ideas on getting rid of glitches in a high precision DAC >>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>> and I'd like to keep the glitches (especially variation in glitches) >>>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >>>> switch? >>>> >>> Run two "in parallel", take only the glitches from one, invert and >>>sum that wit output from the other. >> >>Isn't that equivalent to lowpass filtering a single DAC? Just a lot >>more expensive > >Well, if I high-passed the (variable with code) height glitches from >one DAC and they closely matched the glitches from the other (over >different codes), I could subtract the two, and indeed it might be >much better than a LPF.
How is that better than highpass filtering the glitch from the same dac, and subtracting that? I believe I've just described a lowpass filter. A fast clocked 8-bit DAC could cancel every glitch from the main dac. The lookup table would be many gigabytes, and sort of hard to generate. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Thu, 19 Jul 2012 16:48:23 GMT, Jan Panteltje
<pNaonStpealmtje@yahoo.com> wrote:

>On a sunny day (Thu, 19 Jul 2012 12:12:50 -0400) it happened Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote in ><ffcg081efvnqjrmhn8vuqpbdttkdj4nrjp@4ax.com>: > >>>>http://www.speff.com/glitch.png >>> >>>Maybe the opposite can be done, open a series switch on the spikes. >>>If you have the switch signal and it is early, use it to open a switch >>>in the output for a few ns (longer than the transients). >>>For the rest eitehr way it is homework, drive impedance, switch resistance, >>>RC time, maybe need buffers, noise level, opamp choices. >> >>Yeah, it is homework and I'd like to cheat. > >From that glitch.png loks like you could open a switch for the first 2 uS. >74HC4053 or something like that (16) is about 180 Ohm.
No... charge injection of a 4053 is orders of magnitude too big. Even the AD analog switches are an order of magnitude too big.
>What is the drive impedance?
It's an op-amp output, so it's really, really low at DC and probably looks like 100 ohms or so at higher frequencies.
>Lowpass never works for these things.
On Thu, 19 Jul 2012 11:07:56 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>On Thu, 19 Jul 2012 13:26:39 -0400, Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote: > >>On Thu, 19 Jul 2012 07:29:19 -0700, John Larkin >><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer >>><robertbaer@localnet.com> wrote: >>> >>>>Spehro Pefhany wrote: >>>>> Any clever ideas on getting rid of glitches in a high precision DAC >>>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>> and I'd like to keep the glitches (especially variation in glitches) >>>>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >>>>> switch? >>>>> >>>> Run two "in parallel", take only the glitches from one, invert and >>>>sum that wit output from the other. >>> >>>Isn't that equivalent to lowpass filtering a single DAC? Just a lot >>>more expensive >> >>Well, if I high-passed the (variable with code) height glitches from >>one DAC and they closely matched the glitches from the other (over >>different codes), I could subtract the two, and indeed it might be >>much better than a LPF. > >How is that better than highpass filtering the glitch from the same >dac, and subtracting that? I believe I've just described a lowpass >filter.
Yup, absolutely right. Dunh.
>A fast clocked 8-bit DAC could cancel every glitch from the main dac. >The lookup table would be many gigabytes, and sort of hard to >generate.
2^20-1 bytes = 1Mbyte per time slice, so with 256 time slices, 256Mbytes clocked out every few ns at the transitions. Kind of heroic, but maybe possible. The glitches are currently ~ 10 bits (1000 LSBs) high though, so 8 bits might be a problem (as might be LF noise/drift in the fast converter).
On Thu, 19 Jul 2012 14:38:37 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Thu, 19 Jul 2012 11:07:56 -0700, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>On Thu, 19 Jul 2012 13:26:39 -0400, Spehro Pefhany >><speffSNIP@interlogDOTyou.knowwhat> wrote: >> >>>On Thu, 19 Jul 2012 07:29:19 -0700, John Larkin >>><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer >>>><robertbaer@localnet.com> wrote: >>>> >>>>>Spehro Pefhany wrote: >>>>>> Any clever ideas on getting rid of glitches in a high precision DAC >>>>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>>> and I'd like to keep the glitches (especially variation in glitches) >>>>>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >>>>>> switch? >>>>>> >>>>> Run two "in parallel", take only the glitches from one, invert and >>>>>sum that wit output from the other. >>>> >>>>Isn't that equivalent to lowpass filtering a single DAC? Just a lot >>>>more expensive >>> >>>Well, if I high-passed the (variable with code) height glitches from >>>one DAC and they closely matched the glitches from the other (over >>>different codes), I could subtract the two, and indeed it might be >>>much better than a LPF. >> >>How is that better than highpass filtering the glitch from the same >>dac, and subtracting that? I believe I've just described a lowpass >>filter. > >Yup, absolutely right. Dunh. > >>A fast clocked 8-bit DAC could cancel every glitch from the main dac. >>The lookup table would be many gigabytes, and sort of hard to >>generate. > >2^20-1 bytes = 1Mbyte per time slice, so with 256 time slices, >256Mbytes clocked out every few ns at the transitions. Kind of heroic, >but maybe possible. The glitches are currently ~ 10 bits (1000 LSBs) >high though, so 8 bits might be a problem (as might be LF noise/drift >in the fast converter).
Glitch width = ? Bit time = ? Not clear from your "every few ns" comment :-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
>>in the fast converter). > >Glitch width = ? > >Bit time = ? > >Not clear from your "every few ns" comment :-) > > ...Jim Thompson
http://www.speff.com/glitch.png The real kicker is to do this without affecting the ppm-level DC stability of the signal chain.
Spehro Pefhany wrote:
> > On Thu, 19 Jul 2012 12:35:41 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > > > > > > >How about this: > > > >Ordinary two op amp closed loop T/H, with a resistor and a couple of > >Schottky diodes to prevent the input amp from railing, dual-gate MOSFET > > You mean close the loop around both op-amps with the RC in there? I > guess that might need some thought to guarantee stability. The diode > leakage shouldn't matter much since it's only got a few mV across it. > > >connected S+G2 to the first op amp output, D to the hold cap, G1 is the > >track/hold control. Drive G1 negative during the glitch using an open > >collector with a resistor to S so that it returns to S potential while > >on. > > What's the advantage of that over driving G1 with a digital signal of, > say +10/-5V? > > (BTW, and thanks, Phil, one thing that I'd forgotten since the last > time I used a dual gate MOSFET it was a little metal can with a spring > clip around the leads-- these things are depletion mode, so if you > need a _small_ depletion mode MOSFET even with one gate, they're a > possibility).
There are two kinds of closed-loop S/Hs, as JL pointed out--you can run the second stage as a buffer or as an integrator. Either way, you have to do all the frequency compensation in the outer loop due to the two or three lags. Using the integrator method lets you keep the FET's drain near ground, which is nice. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
On Thu, 19 Jul 2012 14:51:51 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

> >>>in the fast converter). >> >>Glitch width = ? >> >>Bit time = ? >> >>Not clear from your "every few ns" comment :-) >> >> ...Jim Thompson > >http://www.speff.com/glitch.png > >The real kicker is to do this without affecting the ppm-level DC >stability of the signal chain.
That's with your filter. What does it look like, step plus glitch, unfiltered? ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Thu, 19 Jul 2012 12:19:20 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Thu, 19 Jul 2012 14:51:51 -0400, Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote: > >> >>>>in the fast converter). >>> >>>Glitch width = ? >>> >>>Bit time = ? >>> >>>Not clear from your "every few ns" comment :-) >>> >>> ...Jim Thompson >> >>http://www.speff.com/glitch.png >> >>The real kicker is to do this without affecting the ppm-level DC >>stability of the signal chain. > >That's with your filter. What does it look like, step plus glitch, >unfiltered? > > ...Jim Thompson
That's unfiltered, from the DAC output buffer op-amp, with a single LSB step (not visible on that scale).