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Deglitching a DAC

Started by Spehro Pefhany July 17, 2012
Spehro Pefhany wrote:
> Any clever ideas on getting rid of glitches in a high precision DAC > output? Update rate is a fixed rate, probably in the 10-100kHz range, > and I'd like to keep the glitches (especially variation in glitches) > to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection > switch? >
Run two "in parallel", take only the glitches from one, invert and sum that wit output from the other. Will not be perfect,but that may do enough that a nice filter can fix.
On a sunny day (Wed, 18 Jul 2012 17:18:23 -0400) it happened Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote in
<o06e08hrvjuuthplmih2qij2pabo7oo9p0@4ax.com>:

>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> >wrote: > >>Spehro Pefhany wrote: >>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>> <sgoldHAM@alum.mit.edu> wrote: >>> >>>> Message off into the ether. >>>> >>>> What kind of logic are you using to drive the DAC? Is there any >>>> relationship to the driving edge speed, or does it depend only >>>> on the internal update signal after the data are in? >>> >>> It's doing pretty much what the data sheet says it should do, >>> unfortunately. The glitching happens with the update. >>> >> >>You've got to re-sample it outside the chip. There is no way to push >>things down to ppm levels on the same chip with the digital stuff on >>there. Mainly because there's lead inductance, chatter across the >>substrate, finite metal layer conductivity, inductive coupling, and all >>this fun stuff. I'd consider a diff-output DAC followed by a >>differential S&H. Decouple and bypass the supplies really well. Ferrite >>beads and 0402 or 0603 caps are your friends here. > >The irritating thing is that it's directly related to the switches.. >and it ought to be possible to match that stuff on the chip to very >close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV >glitches on a chip (datasheet claim, so ideal conditions) on a chip >with ~100nV of RMS output noise and 1ppm linearity seems... a bit >much. > >http://www.speff.com/glitch.png
Maybe the opposite can be done, open a series switch on the spikes. If you have the switch signal and it is early, use it to open a switch in the output for a few ns (longer than the transients). For the rest eitehr way it is homework, drive impedance, switch resistance, RC time, maybe need buffers, noise level, opamp choices.
On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer
<robertbaer@localnet.com> wrote:

>Spehro Pefhany wrote: >> Any clever ideas on getting rid of glitches in a high precision DAC >> output? Update rate is a fixed rate, probably in the 10-100kHz range, >> and I'd like to keep the glitches (especially variation in glitches) >> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >> switch? >> > Run two "in parallel", take only the glitches from one, invert and >sum that wit output from the other.
Isn't that equivalent to lowpass filtering a single DAC? Just a lot more expensive -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Wed, 18 Jul 2012 21:17:41 -0400, Stephan Goldstein
<sgoldHAM@alum.mit.edu> wrote:

> > >Yep, per the designer it's the internal switches. Glitch is the price >paid for a high-voltage part, as the switches are necessarily bigger >(= higher capacitance) in a higher-voltage process. > >Is the problem the area of the glitch or the height? If the height, >then you may be able to simply filter the output with a cap since >output resistance is ~3k. If it's area, you're stuck, a filter cap >won't change that. In that case you'd need a deglitcher, no mean >feat at 20bits. At that level you're looking at expensive caps like >porcelain, and even then you might need trims for dielectric >absorbtion. FR-4 could be problematic as well. I did a true >16-bit chip-and-wire hybrid SHA many moons ago (like 300 = 25 >years) and it had two DA trims even with a porcelain hold cap on >a ceramic substrate. > >He also said to make sure you have the latest silicon version. >A fix following introduction that reduced glitch energy. I don't >know if there's a difference in brand, or if it's just date code, >sorry. If I weren't in the midst of moving office I could probably >figure out who to ask, but not this week. > >Steve
Thanks, Steve, great info. I've simulated a passive notch filter that might be okay enough, especially if there is a significant reduction in glitching at the silicon level (have to simulate the signal a bit more accurately to be sure). I'm not sure DA is that important in this application- it will just add a bit of a tail to the response. Leakage, OTOH matters a lot. Would love to know how to find out how to tell the chips apart when/if you get a chance.
On Thu, 19 Jul 2012 06:29:59 GMT, Jan Panteltje
<pNaonStpealmtje@yahoo.com> wrote:

>On a sunny day (Wed, 18 Jul 2012 17:18:23 -0400) it happened Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote in ><o06e08hrvjuuthplmih2qij2pabo7oo9p0@4ax.com>: > >>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> >>wrote: >> >>>Spehro Pefhany wrote: >>>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>>> <sgoldHAM@alum.mit.edu> wrote: >>>> >>>>> Message off into the ether. >>>>> >>>>> What kind of logic are you using to drive the DAC? Is there any >>>>> relationship to the driving edge speed, or does it depend only >>>>> on the internal update signal after the data are in? >>>> >>>> It's doing pretty much what the data sheet says it should do, >>>> unfortunately. The glitching happens with the update. >>>> >>> >>>You've got to re-sample it outside the chip. There is no way to push >>>things down to ppm levels on the same chip with the digital stuff on >>>there. Mainly because there's lead inductance, chatter across the >>>substrate, finite metal layer conductivity, inductive coupling, and all >>>this fun stuff. I'd consider a diff-output DAC followed by a >>>differential S&H. Decouple and bypass the supplies really well. Ferrite >>>beads and 0402 or 0603 caps are your friends here. >> >>The irritating thing is that it's directly related to the switches.. >>and it ought to be possible to match that stuff on the chip to very >>close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV >>glitches on a chip (datasheet claim, so ideal conditions) on a chip >>with ~100nV of RMS output noise and 1ppm linearity seems... a bit >>much. >> >>http://www.speff.com/glitch.png > >Maybe the opposite can be done, open a series switch on the spikes. >If you have the switch signal and it is early, use it to open a switch >in the output for a few ns (longer than the transients). >For the rest eitehr way it is homework, drive impedance, switch resistance, >RC time, maybe need buffers, noise level, opamp choices.
Yeah, it is homework and I'd like to cheat.
On Thu, 19 Jul 2012 06:29:59 GMT, Jan Panteltje
<pNaonStpealmtje@yahoo.com> wrote:

>On a sunny day (Wed, 18 Jul 2012 17:18:23 -0400) it happened Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote in ><o06e08hrvjuuthplmih2qij2pabo7oo9p0@4ax.com>: > >>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> >>wrote: >> >>>Spehro Pefhany wrote: >>>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>>> <sgoldHAM@alum.mit.edu> wrote: >>>> >>>>> Message off into the ether. >>>>> >>>>> What kind of logic are you using to drive the DAC? Is there any >>>>> relationship to the driving edge speed, or does it depend only >>>>> on the internal update signal after the data are in? >>>> >>>> It's doing pretty much what the data sheet says it should do, >>>> unfortunately. The glitching happens with the update. >>>> >>> >>>You've got to re-sample it outside the chip. There is no way to push >>>things down to ppm levels on the same chip with the digital stuff on >>>there. Mainly because there's lead inductance, chatter across the >>>substrate, finite metal layer conductivity, inductive coupling, and all >>>this fun stuff. I'd consider a diff-output DAC followed by a >>>differential S&H. Decouple and bypass the supplies really well. Ferrite >>>beads and 0402 or 0603 caps are your friends here. >> >>The irritating thing is that it's directly related to the switches.. >>and it ought to be possible to match that stuff on the chip to very >>close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV >>glitches on a chip (datasheet claim, so ideal conditions) on a chip >>with ~100nV of RMS output noise and 1ppm linearity seems... a bit >>much. >> >>http://www.speff.com/glitch.png > >Maybe the opposite can be done, open a series switch on the spikes. >If you have the switch signal and it is early, use it to open a switch >in the output for a few ns (longer than the transients). >For the rest eitehr way it is homework, drive impedance, switch resistance, >RC time, maybe need buffers, noise level, opamp choices. >
... charge injection... -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Spehro Pefhany wrote:
> > On Thu, 19 Jul 2012 06:29:59 GMT, Jan Panteltje > <pNaonStpealmtje@yahoo.com> wrote: > > >On a sunny day (Wed, 18 Jul 2012 17:18:23 -0400) it happened Spehro Pefhany > ><speffSNIP@interlogDOTyou.knowwhat> wrote in > ><o06e08hrvjuuthplmih2qij2pabo7oo9p0@4ax.com>: > > > >>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> > >>wrote: > >> > >>>Spehro Pefhany wrote: > >>>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein > >>>> <sgoldHAM@alum.mit.edu> wrote: > >>>> > >>>>> Message off into the ether. > >>>>> > >>>>> What kind of logic are you using to drive the DAC? Is there any > >>>>> relationship to the driving edge speed, or does it depend only > >>>>> on the internal update signal after the data are in? > >>>> > >>>> It's doing pretty much what the data sheet says it should do, > >>>> unfortunately. The glitching happens with the update. > >>>> > >>> > >>>You've got to re-sample it outside the chip. There is no way to push > >>>things down to ppm levels on the same chip with the digital stuff on > >>>there. Mainly because there's lead inductance, chatter across the > >>>substrate, finite metal layer conductivity, inductive coupling, and all > >>>this fun stuff. I'd consider a diff-output DAC followed by a > >>>differential S&H. Decouple and bypass the supplies really well. Ferrite > >>>beads and 0402 or 0603 caps are your friends here. > >> > >>The irritating thing is that it's directly related to the switches.. > >>and it ought to be possible to match that stuff on the chip to very > >>close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV > >>glitches on a chip (datasheet claim, so ideal conditions) on a chip > >>with ~100nV of RMS output noise and 1ppm linearity seems... a bit > >>much. > >> > >>http://www.speff.com/glitch.png > > > >Maybe the opposite can be done, open a series switch on the spikes. > >If you have the switch signal and it is early, use it to open a switch > >in the output for a few ns (longer than the transients). > >For the rest eitehr way it is homework, drive impedance, switch resistance, > >RC time, maybe need buffers, noise level, opamp choices. > > Yeah, it is homework and I'd like to cheat.
How about this: Ordinary two op amp closed loop T/H, with a resistor and a couple of Schottky diodes to prevent the input amp from railing, dual-gate MOSFET connected S+G2 to the first op amp output, D to the hold cap, G1 is the track/hold control. Drive G1 negative during the glitch using an open collector with a resistor to S so that it returns to S potential while on. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
On a sunny day (Thu, 19 Jul 2012 12:12:50 -0400) it happened Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote in
<ffcg081efvnqjrmhn8vuqpbdttkdj4nrjp@4ax.com>:

>>>http://www.speff.com/glitch.png >> >>Maybe the opposite can be done, open a series switch on the spikes. >>If you have the switch signal and it is early, use it to open a switch >>in the output for a few ns (longer than the transients). >>For the rest eitehr way it is homework, drive impedance, switch resistance, >>RC time, maybe need buffers, noise level, opamp choices. > >Yeah, it is homework and I'd like to cheat.
From that glitch.png loks like you could open a switch for the first 2 uS. 74HC4053 or something like that (16) is about 180 Ohm. What is the drive impedance? Lowpass never works for these things.
On Thu, 19 Jul 2012 12:35:41 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>Spehro Pefhany wrote: >> >> On Thu, 19 Jul 2012 06:29:59 GMT, Jan Panteltje >> <pNaonStpealmtje@yahoo.com> wrote: >> >> >On a sunny day (Wed, 18 Jul 2012 17:18:23 -0400) it happened Spehro Pefhany >> ><speffSNIP@interlogDOTyou.knowwhat> wrote in >> ><o06e08hrvjuuthplmih2qij2pabo7oo9p0@4ax.com>: >> > >> >>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> >> >>wrote: >> >> >> >>>Spehro Pefhany wrote: >> >>>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >> >>>> <sgoldHAM@alum.mit.edu> wrote: >> >>>> >> >>>>> Message off into the ether. >> >>>>> >> >>>>> What kind of logic are you using to drive the DAC? Is there any >> >>>>> relationship to the driving edge speed, or does it depend only >> >>>>> on the internal update signal after the data are in? >> >>>> >> >>>> It's doing pretty much what the data sheet says it should do, >> >>>> unfortunately. The glitching happens with the update. >> >>>> >> >>> >> >>>You've got to re-sample it outside the chip. There is no way to push >> >>>things down to ppm levels on the same chip with the digital stuff on >> >>>there. Mainly because there's lead inductance, chatter across the >> >>>substrate, finite metal layer conductivity, inductive coupling, and all >> >>>this fun stuff. I'd consider a diff-output DAC followed by a >> >>>differential S&H. Decouple and bypass the supplies really well. Ferrite >> >>>beads and 0402 or 0603 caps are your friends here. >> >> >> >>The irritating thing is that it's directly related to the switches.. >> >>and it ought to be possible to match that stuff on the chip to very >> >>close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV >> >>glitches on a chip (datasheet claim, so ideal conditions) on a chip >> >>with ~100nV of RMS output noise and 1ppm linearity seems... a bit >> >>much. >> >> >> >>http://www.speff.com/glitch.png >> > >> >Maybe the opposite can be done, open a series switch on the spikes. >> >If you have the switch signal and it is early, use it to open a switch >> >in the output for a few ns (longer than the transients). >> >For the rest eitehr way it is homework, drive impedance, switch resistance, >> >RC time, maybe need buffers, noise level, opamp choices. >> >> Yeah, it is homework and I'd like to cheat. > >How about this: > >Ordinary two op amp closed loop T/H, with a resistor and a couple of >Schottky diodes to prevent the input amp from railing, dual-gate MOSFET >connected S+G2 to the first op amp output, D to the hold cap, G1 is the >track/hold control. Drive G1 negative during the glitch using an open >collector with a resistor to S so that it returns to S potential while >on. > >Cheers > >Phil Hobbs
I had in mind this: an input error amp with modest gain, like 1, followed by an integrator, closed loop. The midway connection is schottky clamped, maybe not necesary for small glitches. The difference is that I'd propose to blank the glitch by shorting the midway signal to ground with a PHEMT, which probably has the best Ron*Cdg product that you can get anywhere. Cut the loop gain by 10:1 or so around glitch time. The dual-gate will shoot some of the G1 charge back into the first opamp, which can cause problems there. Making the second stage an integrator keeps the switch, whichever kind, always working near ground. That keeps things more linear, and makes charge cancellation, if it's needed, a lot easier. Either way, the s/h is usually in track mode, briefly in hold mode at glitch time. So cap DA doesn't matter much. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Thu, 19 Jul 2012 07:29:19 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Wed, 18 Jul 2012 22:50:07 -0700, Robert Baer ><robertbaer@localnet.com> wrote: > >>Spehro Pefhany wrote: >>> Any clever ideas on getting rid of glitches in a high precision DAC >>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>> and I'd like to keep the glitches (especially variation in glitches) >>> to<< 25ppm, preferably< 5ppm. A S&H with a low charge injection >>> switch? >>> >> Run two "in parallel", take only the glitches from one, invert and >>sum that wit output from the other. > >Isn't that equivalent to lowpass filtering a single DAC? Just a lot >more expensive
Well, if I high-passed the (variable with code) height glitches from one DAC and they closely matched the glitches from the other (over different codes), I could subtract the two, and indeed it might be much better than a LPF. It's an innovative & interesting idea, but the thousands of dollars extra in parts and board area make it a bit less attractive (also it would have to be established that the matching was reasonable between parts). Sounds like st that the chip maker could have done more efficiently.