Forums

Deglitching a DAC

Started by Spehro Pefhany July 17, 2012
Spehro Pefhany wrote:
> On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Spehro Pefhany wrote: >>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>> <sgoldHAM@alum.mit.edu> wrote: >>> >>>> Message off into the ether. >>>> >>>> What kind of logic are you using to drive the DAC? Is there any >>>> relationship to the driving edge speed, or does it depend only >>>> on the internal update signal after the data are in? >>> It's doing pretty much what the data sheet says it should do, >>> unfortunately. The glitching happens with the update. >>> >> You've got to re-sample it outside the chip. There is no way to push >> things down to ppm levels on the same chip with the digital stuff on >> there. Mainly because there's lead inductance, chatter across the >> substrate, finite metal layer conductivity, inductive coupling, and all >> this fun stuff. I'd consider a diff-output DAC followed by a >> differential S&H. Decouple and bypass the supplies really well. Ferrite >> beads and 0402 or 0603 caps are your friends here. > > The irritating thing is that it's directly related to the switches.. > and it ought to be possible to match that stuff on the chip to very > close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV > glitches on a chip (datasheet claim, so ideal conditions) on a chip > with ~100nV of RMS output noise and 1ppm linearity seems... a bit > much. > > http://www.speff.com/glitch.png >
My very first "real" project in this direction was my masters project. I've got to scan that stuff in some day. Anyhow, it was the design of a CCD camera from scratch because the circuit from the CCD manufacturer was ... ahem ... lets say, the pits. They got a measly 45dB of dynamic range because of bad charge injection noise and such. So I used diode quads, one for each of the three output channels. Off the bat that bumped it to 60dB. Charge injection wasn't even measurable anymore and we were down to the inherent noise of the CCD "bucket-brigade" cells. The trick: The transformers driving the sampler were carefully made not to favor one side over the other, so any capacitive coupling would be neutralized. I made them out of ferrite, cost almost nothing. We did have a DC offset due to diode imbalances but that was a piece of cake to compensate for (I just clamped it away). If a FET switch is desired one could either look for well neutralized mux ICs or counter-inject a charge of opposite polarity. The usual, two bent wires near each other as a poor man's capacitor, bent with a wooden chop stick until it's just right. A good excuse for an evening at the Japanese restaurant. -- Regards, Joerg http://www.analogconsultants.com/
On Wed, 18 Jul 2012 17:28:11 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Wed, 18 Jul 2012 13:21:42 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>On Wed, 18 Jul 2012 12:37:04 -0700, John Larkin >><jlarkin@highlandtechnology.com> wrote: >> >>>On Tue, 17 Jul 2012 20:28:29 -0700 (PDT), >>>bloggs.fredbloggs.fred@gmail.com wrote: >>> >>>>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >>>>> Any clever ideas on getting rid of glitches in a high precision DAC >>>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>> and I&#39;d like to keep the glitches (especially variation in glitches) >>>>> to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >>>>> switch? >>>> >>>>One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though. >>> >>>A simple slew-rate limiter circuit might make a pretty good >>>deglitcher. Sort of like a lowpass filter, but with more precise >>>settling behavior. >> >>Yep. Trick is to make desired slew-rate, yet have precise settling. >> >> ...Jim Thompson > >Not sure slew rate is the right way- the glitches look to have about >the same time-voltage area above nominal as below, so a linear filter >might be better.
What I had in mind was making the slew _time_, to negotiate one step increment, slightly longer than the glitch width. I've done it in CMOS. With the advantage that I can make a current output stage (with bounds) OpAmp, compensated by the slew cap :-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
"John Larkin" <jlarkin@highlandtechnology.com> wrote in message 
news:bq3e08dgc9t3g1tnc760tr49ped1uo6avi@4ax.com...
> Sure. But I have an idea for a gated deglitcher, but it wouldn't > handle big voltage steps. It might work if Speff can digitally > slew-rate-limit the dac steps. > > Still thinking about it.
Sounds like a diode balanced mixer with balanced CCS pull up and pull down. Use LEDs and avoid the voltage limit. Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms
John Larkin wrote:

> On Tue, 17 Jul 2012 20:28:29 -0700 (PDT), > bloggs.fredbloggs.fred@gmail.com wrote: > > >>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >> >>>Any clever ideas on getting rid of glitches in a high precision DAC >>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>and I&#39;d like to keep the glitches (especially variation in glitches) >>>to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >>>switch? >> >>One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though. > > > A simple slew-rate limiter circuit might make a pretty good > deglitcher. Sort of like a lowpass filter, but with more precise > settling behavior. >
What's wrong with a resetable integrator? Jamie
On Wed, 18 Jul 2012 18:06:55 -0500, "Tim Williams"
<tmoranwms@charter.net> wrote:

>"John Larkin" <jlarkin@highlandtechnology.com> wrote in message >news:bq3e08dgc9t3g1tnc760tr49ped1uo6avi@4ax.com... >> Sure. But I have an idea for a gated deglitcher, but it wouldn't >> handle big voltage steps. It might work if Speff can digitally >> slew-rate-limit the dac steps. >> >> Still thinking about it. > >Sounds like a diode balanced mixer with balanced CCS pull up and pull down.
If you can balance the drive currents really, really well. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Wed, 18 Jul 2012 19:11:43 -0400, Jamie
<jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote:

>John Larkin wrote: > >> On Tue, 17 Jul 2012 20:28:29 -0700 (PDT), >> bloggs.fredbloggs.fred@gmail.com wrote: >> >> >>>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >>> >>>>Any clever ideas on getting rid of glitches in a high precision DAC >>>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>and I&#39;d like to keep the glitches (especially variation in glitches) >>>>to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >>>>switch? >>> >>>One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though. >> >> >> A simple slew-rate limiter circuit might make a pretty good >> deglitcher. Sort of like a lowpass filter, but with more precise >> settling behavior. >> > What's wrong with a resetable integrator? > > Jamie
When would you reset it? -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Wed, 18 Jul 2012 16:29:25 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>On Wed, 18 Jul 2012 18:06:55 -0500, "Tim Williams" ><tmoranwms@charter.net> wrote: > >>"John Larkin" <jlarkin@highlandtechnology.com> wrote in message >>news:bq3e08dgc9t3g1tnc760tr49ped1uo6avi@4ax.com... >>> Sure. But I have an idea for a gated deglitcher, but it wouldn't >>> handle big voltage steps. It might work if Speff can digitally >>> slew-rate-limit the dac steps. >>> >>> Still thinking about it. >> >>Sounds like a diode balanced mixer with balanced CCS pull up and pull down. > >If you can balance the drive currents really, really well.
"Balance" is not critical if you use an OpAmp. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
John Larkin wrote:

> On Wed, 18 Jul 2012 19:11:43 -0400, Jamie > <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote: > > >>John Larkin wrote: >> >> >>>On Tue, 17 Jul 2012 20:28:29 -0700 (PDT), >>>bloggs.fredbloggs.fred@gmail.com wrote: >>> >>> >>> >>>>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >>>> >>>> >>>>>Any clever ideas on getting rid of glitches in a high precision DAC >>>>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>>and I&#39;d like to keep the glitches (especially variation in glitches) >>>>>to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >>>>>switch? >>>> >>>>One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though. >>> >>> >>>A simple slew-rate limiter circuit might make a pretty good >>>deglitcher. Sort of like a lowpass filter, but with more precise >>>settling behavior. >>> >> >> What's wrong with a resetable integrator? >> >> Jamie > > > When would you reset it? > >
I've used low bit count DACs and past them through an integrate that is controlled with a JFET on another IO port. When output value is shifted beyond the jitter point, the integrator id switched off. Jfet is in the integrator feed back loop. This all assumes we have a uC of some sort behind the scenes. Jamie
On Wed, 18 Jul 2012 17:18:23 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid> >wrote: > >>Spehro Pefhany wrote: >>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>> <sgoldHAM@alum.mit.edu> wrote: >>> >>>> Message off into the ether. >>>> >>>> What kind of logic are you using to drive the DAC? Is there any >>>> relationship to the driving edge speed, or does it depend only >>>> on the internal update signal after the data are in? >>> >>> It's doing pretty much what the data sheet says it should do, >>> unfortunately. The glitching happens with the update. >>> >> >>You've got to re-sample it outside the chip. There is no way to push >>things down to ppm levels on the same chip with the digital stuff on >>there. Mainly because there's lead inductance, chatter across the >>substrate, finite metal layer conductivity, inductive coupling, and all >>this fun stuff. I'd consider a diff-output DAC followed by a >>differential S&H. Decouple and bypass the supplies really well. Ferrite >>beads and 0402 or 0603 caps are your friends here. > >The irritating thing is that it's directly related to the switches.. >and it ought to be possible to match that stuff on the chip to very >close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV >glitches on a chip (datasheet claim, so ideal conditions) on a chip >with ~100nV of RMS output noise and 1ppm linearity seems... a bit >much. > >http://www.speff.com/glitch.png >
Yep, per the designer it's the internal switches. Glitch is the price paid for a high-voltage part, as the switches are necessarily bigger (= higher capacitance) in a higher-voltage process. Is the problem the area of the glitch or the height? If the height, then you may be able to simply filter the output with a cap since output resistance is ~3k. If it's area, you're stuck, a filter cap won't change that. In that case you'd need a deglitcher, no mean feat at 20bits. At that level you're looking at expensive caps like porcelain, and even then you might need trims for dielectric absorbtion. FR-4 could be problematic as well. I did a true 16-bit chip-and-wire hybrid SHA many moons ago (like 300 = 25 years) and it had two DA trims even with a porcelain hold cap on a ceramic substrate. He also said to make sure you have the latest silicon version. A fix following introduction that reduced glitch energy. I don't know if there's a difference in brand, or if it's just date code, sorry. If I weren't in the midst of moving office I could probably figure out who to ask, but not this week. Steve
On 7/18/2012 2:28 PM, Spehro Pefhany wrote:
> On Wed, 18 Jul 2012 16:39:38 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> >> That's where the dual-gate MOSFET comes in. They work great. >> >> Cheers >> >> Phil Hobbs > > Sure looks nice in simulation. >
Cascoding the charger transfer device was done back in the NMOS analog days. [Intel 6um double poly eprom process.] Once you went to CMOS, charge injection was less of a problem since you had some cancellation due to using both sexes of switches. The old video DACs used a combination of binary weighting and thermometer coding. You still got glitches when the binary segments were switched.