Forums

Deglitching a DAC

Started by Spehro Pefhany July 17, 2012
Spehro Pefhany wrote:
> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein > <sgoldHAM@alum.mit.edu> wrote: > >> Message off into the ether. >> >> What kind of logic are you using to drive the DAC? Is there any >> relationship to the driving edge speed, or does it depend only >> on the internal update signal after the data are in? > > It's doing pretty much what the data sheet says it should do, > unfortunately. The glitching happens with the update. >
You've got to re-sample it outside the chip. There is no way to push things down to ppm levels on the same chip with the digital stuff on there. Mainly because there's lead inductance, chatter across the substrate, finite metal layer conductivity, inductive coupling, and all this fun stuff. I'd consider a diff-output DAC followed by a differential S&H. Decouple and bypass the supplies really well. Ferrite beads and 0402 or 0603 caps are your friends here. -- Regards, Joerg http://www.analogconsultants.com/
Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Tue, 17 Jul 2012 20:11:32 GMT, nico@puntnl.niks (Nico Coesel) >wrote: > >>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote: >> >>>Any clever ideas on getting rid of glitches in a high precision DAC >>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>and I'd like to keep the glitches (especially variation in glitches) >>>to << 25ppm, preferably < 5ppm. A S&H with a low charge injection >>>switch? >> >>What kind of DAC is it? IIRC the better DACs have a latch enable pin >>which sets the new value for a bits in 1 go. Or does the DAC have that >>and is still misbehaving? > >It's not a digital thing. There's an output glitch whenever the code >is updated. The size depends on the number of switches changing, so >it's almost independent of the output value (eg. 0x3F..F changing to >0x40..0 is only one LSB but most of the switches change, while >0x40..00 to 0x40..01 is the same change single LSB but only a single >switch changes.
Is the glitch also noticable when you change one bit? Adding more analog stuff often means more error & noise. Could this be handled in the digital domain by converging to the new value by flipping one bit at a time? -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
On Wed, 18 Jul 2012 12:37:04 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>On Tue, 17 Jul 2012 20:28:29 -0700 (PDT), >bloggs.fredbloggs.fred@gmail.com wrote: > >>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >>> Any clever ideas on getting rid of glitches in a high precision DAC >>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>> and I&#39;d like to keep the glitches (especially variation in glitches) >>> to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >>> switch? >> >>One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though. > >A simple slew-rate limiter circuit might make a pretty good >deglitcher. Sort of like a lowpass filter, but with more precise >settling behavior.
Yep. Trick is to make desired slew-rate, yet have precise settling. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid>
wrote:

>Spehro Pefhany wrote: >> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >> <sgoldHAM@alum.mit.edu> wrote: >> >>> Message off into the ether. >>> >>> What kind of logic are you using to drive the DAC? Is there any >>> relationship to the driving edge speed, or does it depend only >>> on the internal update signal after the data are in? >> >> It's doing pretty much what the data sheet says it should do, >> unfortunately. The glitching happens with the update. >> > >You've got to re-sample it outside the chip. There is no way to push >things down to ppm levels on the same chip with the digital stuff on >there. Mainly because there's lead inductance, chatter across the >substrate, finite metal layer conductivity, inductive coupling, and all >this fun stuff. I'd consider a diff-output DAC followed by a >differential S&H. Decouple and bypass the supplies really well. Ferrite >beads and 0402 or 0603 caps are your friends here.
The big problem will be charge injection in the s/h switch. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On 07/18/2012 04:35 PM, John Larkin wrote:
> On Wed, 18 Jul 2012 12:49:04 -0700, Joerg<invalid@invalid.invalid> > wrote: > >> Spehro Pefhany wrote: >>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>> <sgoldHAM@alum.mit.edu> wrote: >>> >>>> Message off into the ether. >>>> >>>> What kind of logic are you using to drive the DAC? Is there any >>>> relationship to the driving edge speed, or does it depend only >>>> on the internal update signal after the data are in? >>> >>> It's doing pretty much what the data sheet says it should do, >>> unfortunately. The glitching happens with the update. >>> >> >> You've got to re-sample it outside the chip. There is no way to push >> things down to ppm levels on the same chip with the digital stuff on >> there. Mainly because there's lead inductance, chatter across the >> substrate, finite metal layer conductivity, inductive coupling, and all >> this fun stuff. I'd consider a diff-output DAC followed by a >> differential S&H. Decouple and bypass the supplies really well. Ferrite >> beads and 0402 or 0603 caps are your friends here. > > The big problem will be charge injection in the s/h switch. > >
That's where the dual-gate MOSFET comes in. They work great. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
On Wed, 18 Jul 2012 12:49:04 -0700, Joerg <invalid@invalid.invalid>
wrote:

>Spehro Pefhany wrote: >> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >> <sgoldHAM@alum.mit.edu> wrote: >> >>> Message off into the ether. >>> >>> What kind of logic are you using to drive the DAC? Is there any >>> relationship to the driving edge speed, or does it depend only >>> on the internal update signal after the data are in? >> >> It's doing pretty much what the data sheet says it should do, >> unfortunately. The glitching happens with the update. >> > >You've got to re-sample it outside the chip. There is no way to push >things down to ppm levels on the same chip with the digital stuff on >there. Mainly because there's lead inductance, chatter across the >substrate, finite metal layer conductivity, inductive coupling, and all >this fun stuff. I'd consider a diff-output DAC followed by a >differential S&H. Decouple and bypass the supplies really well. Ferrite >beads and 0402 or 0603 caps are your friends here.
The irritating thing is that it's directly related to the switches.. and it ought to be possible to match that stuff on the chip to very close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV glitches on a chip (datasheet claim, so ideal conditions) on a chip with ~100nV of RMS output noise and 1ppm linearity seems... a bit much. http://www.speff.com/glitch.png
On Wed, 18 Jul 2012 20:12:24 GMT, nico@puntnl.niks (Nico Coesel)
wrote:

>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote: > >>On Tue, 17 Jul 2012 20:11:32 GMT, nico@puntnl.niks (Nico Coesel) >>wrote: >> >>>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote: >>> >>>>Any clever ideas on getting rid of glitches in a high precision DAC >>>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>and I'd like to keep the glitches (especially variation in glitches) >>>>to << 25ppm, preferably < 5ppm. A S&H with a low charge injection >>>>switch? >>> >>>What kind of DAC is it? IIRC the better DACs have a latch enable pin >>>which sets the new value for a bits in 1 go. Or does the DAC have that >>>and is still misbehaving? >> >>It's not a digital thing. There's an output glitch whenever the code >>is updated. The size depends on the number of switches changing, so >>it's almost independent of the output value (eg. 0x3F..F changing to >>0x40..0 is only one LSB but most of the switches change, while >>0x40..00 to 0x40..01 is the same change single LSB but only a single >>switch changes. > >Is the glitch also noticable when you change one bit?
Yes, it's dependent on the number of switches changing.. so as few as one and as many as 19 switches for a single LSB output change.
>Adding more >analog stuff often means more error & noise. Could this be handled in >the digital domain by converging to the new value by flipping one bit >at a time?
Nope. Although I suppose I could declare some codes personna (numbera?) non grata and avoid the worst of them at the expense of a bit or two resolution. 8-(
On Wed, 18 Jul 2012 13:21:42 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Wed, 18 Jul 2012 12:37:04 -0700, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>On Tue, 17 Jul 2012 20:28:29 -0700 (PDT), >>bloggs.fredbloggs.fred@gmail.com wrote: >> >>>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >>>> Any clever ideas on getting rid of glitches in a high precision DAC >>>> output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>> and I&#39;d like to keep the glitches (especially variation in glitches) >>>> to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >>>> switch? >>> >>>One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though. >> >>A simple slew-rate limiter circuit might make a pretty good >>deglitcher. Sort of like a lowpass filter, but with more precise >>settling behavior. > >Yep. Trick is to make desired slew-rate, yet have precise settling. > > ...Jim Thompson
Not sure slew rate is the right way- the glitches look to have about the same time-voltage area above nominal as below, so a linear filter might be better.
On Wed, 18 Jul 2012 16:39:38 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

> >That's where the dual-gate MOSFET comes in. They work great. > >Cheers > >Phil Hobbs
Sure looks nice in simulation.
On Wed, 18 Jul 2012 16:39:38 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 07/18/2012 04:35 PM, John Larkin wrote: >> On Wed, 18 Jul 2012 12:49:04 -0700, Joerg<invalid@invalid.invalid> >> wrote: >> >>> Spehro Pefhany wrote: >>>> On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein >>>> <sgoldHAM@alum.mit.edu> wrote: >>>> >>>>> Message off into the ether. >>>>> >>>>> What kind of logic are you using to drive the DAC? Is there any >>>>> relationship to the driving edge speed, or does it depend only >>>>> on the internal update signal after the data are in? >>>> >>>> It's doing pretty much what the data sheet says it should do, >>>> unfortunately. The glitching happens with the update. >>>> >>> >>> You've got to re-sample it outside the chip. There is no way to push >>> things down to ppm levels on the same chip with the digital stuff on >>> there. Mainly because there's lead inductance, chatter across the >>> substrate, finite metal layer conductivity, inductive coupling, and all >>> this fun stuff. I'd consider a diff-output DAC followed by a >>> differential S&H. Decouple and bypass the supplies really well. Ferrite >>> beads and 0402 or 0603 caps are your friends here. >> >> The big problem will be charge injection in the s/h switch. >> >> >That's where the dual-gate MOSFET comes in. They work great. > >Cheers > >Phil Hobbs
PHEMTs have insanely low Cd-g. A phemt would be best used as a shunt switch to ground, where it would only need about a volt of gate swing, and would short a signal to ground, but it couldn't handle much signal swing. So, I'm thinking about a 2-opamp closed-loop thing, with an integrator, that has a phemt in there to short out the signal during the glitch, essentially killing loop gain during the glitch. It would, overall, have a 1st order lowpass response, or it could be configured as a slew rate limiter. Something like that. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation