Forums

Deglitching a DAC

Started by Spehro Pefhany July 17, 2012
On a sunny day (Tue, 17 Jul 2012 16:37:34 -0400) it happened Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote in
<62jb081kke22qqhjgunr6t0ocklhu8sh0i@4ax.com>:

>On Tue, 17 Jul 2012 20:11:32 GMT, nico@puntnl.niks (Nico Coesel) >wrote: > >>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote: >> >>>Any clever ideas on getting rid of glitches in a high precision DAC >>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>and I'd like to keep the glitches (especially variation in glitches) >>>to << 25ppm, preferably < 5ppm. A S&H with a low charge injection >>>switch? >> >>What kind of DAC is it? IIRC the better DACs have a latch enable pin >>which sets the new value for a bits in 1 go. Or does the DAC have that >>and is still misbehaving? > >It's not a digital thing. There's an output glitch whenever the code >is updated. The size depends on the number of switches changing, so >it's almost independent of the output value (eg. 0x3F..F changing to >0x40..0 is only one LSB but most of the switches change, while >0x40..00 to 0x40..01 is the same change single LSB but only a single >switch changes. >
Sample output after switch change, store, etc.?
On Tue, 17 Jul 2012 16:47:29 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Tue, 17 Jul 2012 13:23:37 -0700, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>On Tue, 17 Jul 2012 15:43:21 -0400, Spehro Pefhany >><speffSNIP@interlogDOTyou.knowwhat> wrote: >> >>>Any clever ideas on getting rid of glitches in a high precision DAC >>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>and I'd like to keep the glitches (especially variation in glitches) >>>to << 25ppm, preferably < 5ppm. A S&H with a low charge injection >>>switch? >> >> >>LTC makes some 16-bit internally-deglitched DACs. >> >>Or use a fast dac and lowpass filter it. That will help kill digital >>clock+data feedthrough, which can be as big a problem as pure >>glitches. >> >>A delta-sigma dac will have low glitch energy, but maybe not enough >>bandwidth. > >It's an Analog '5791- pretty much a real 20 bits.
I'll ask the designer, he's a colleague.
On Wed, 18 Jul 2012 07:00:04 -0400, Stephan Goldstein
<sgoldHAM@alum.mit.edu> wrote:

>On Tue, 17 Jul 2012 16:47:29 -0400, Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote: > >>On Tue, 17 Jul 2012 13:23:37 -0700, John Larkin >><jlarkin@highlandtechnology.com> wrote: >> >>>On Tue, 17 Jul 2012 15:43:21 -0400, Spehro Pefhany >>><speffSNIP@interlogDOTyou.knowwhat> wrote: >>> >>>>Any clever ideas on getting rid of glitches in a high precision DAC >>>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>and I'd like to keep the glitches (especially variation in glitches) >>>>to << 25ppm, preferably < 5ppm. A S&H with a low charge injection >>>>switch? >>> >>> >>>LTC makes some 16-bit internally-deglitched DACs. >>> >>>Or use a fast dac and lowpass filter it. That will help kill digital >>>clock+data feedthrough, which can be as big a problem as pure >>>glitches. >>> >>>A delta-sigma dac will have low glitch energy, but maybe not enough >>>bandwidth. >> >>It's an Analog '5791- pretty much a real 20 bits. > >I'll ask the designer, he's a colleague.
Message off into the ether. What kind of logic are you using to drive the DAC? Is there any relationship to the driving edge speed, or does it depend only on the internal update signal after the data are in?
On Wed, 18 Jul 2012 06:50:13 GMT, the renowned Jan Panteltje
<pNaonStpealmtje@yahoo.com> wrote:

>On a sunny day (Tue, 17 Jul 2012 16:37:34 -0400) it happened Spehro Pefhany ><speffSNIP@interlogDOTyou.knowwhat> wrote in ><62jb081kke22qqhjgunr6t0ocklhu8sh0i@4ax.com>: > >>On Tue, 17 Jul 2012 20:11:32 GMT, nico@puntnl.niks (Nico Coesel) >>wrote: >> >>>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote: >>> >>>>Any clever ideas on getting rid of glitches in a high precision DAC >>>>output? Update rate is a fixed rate, probably in the 10-100kHz range, >>>>and I'd like to keep the glitches (especially variation in glitches) >>>>to << 25ppm, preferably < 5ppm. A S&H with a low charge injection >>>>switch? >>> >>>What kind of DAC is it? IIRC the better DACs have a latch enable pin >>>which sets the new value for a bits in 1 go. Or does the DAC have that >>>and is still misbehaving? >> >>It's not a digital thing. There's an output glitch whenever the code >>is updated. The size depends on the number of switches changing, so >>it's almost independent of the output value (eg. 0x3F..F changing to >>0x40..0 is only one LSB but most of the switches change, while >>0x40..00 to 0x40..01 is the same change single LSB but only a single >>switch changes. >> > >Sample output after switch change, store, etc.?
Sure, that's the idea.. but the details of ppm-level S&H are where it gets "interesting". Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
On Wed, 18 Jul 2012 07:10:22 -0400, the renowned Stephan Goldstein
<sgoldHAM@alum.mit.edu> wrote:

> >Message off into the ether. > >What kind of logic are you using to drive the DAC? Is there any >relationship to the driving edge speed, or does it depend only >on the internal update signal after the data are in?
It's doing pretty much what the data sheet says it should do, unfortunately. The glitching happens with the update. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
On Wed, 18 Jul 2012 02:02:50 -0400, "Michael A. Terrell"
<mike.terrell@earthlink.net> wrote:

> >John Larkin wrote: >> >> On Tue, 17 Jul 2012 19:50:15 -0400, "Michael A. Terrell" >> <mike.terrell@earthlink.net> wrote: >> >> > >> >John Larkin wrote: >> >> >> >> We used to use AD1862 (20 bit parallel) DACs, but we had bad popcorn >> >> noise problems, and AD eventually discontinued them. >> >> >> >> We have 140 in stock, popcorn fallouts. >> > >> > >> > Would they be useful for a digitally controlled power supply? >> >> Sure, if you don't mind the occasional 10 PPM bump. > > > That wouldn't bother me. I want to build some new bench supplies that >I can program the voltage & current limiting. I would need two per >output and I'd like at least four outputs.
I can certainly send you some DACs, and some nice voltage references, too. You will need a uP and some displays and encoders or something, too. One could also do it as a feedback system, where a 24-bit delta-sigma ADC would measure the output and servo it to a target value. Some of those cheap d-s adcs are amazingly good. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
John Larkin wrote:
> > On Wed, 18 Jul 2012 02:02:50 -0400, "Michael A. Terrell" > <mike.terrell@earthlink.net> wrote: > > > > >John Larkin wrote: > >> > >> On Tue, 17 Jul 2012 19:50:15 -0400, "Michael A. Terrell" > >> <mike.terrell@earthlink.net> wrote: > >> > >> > > >> >John Larkin wrote: > >> >> > >> >> We used to use AD1862 (20 bit parallel) DACs, but we had bad popcorn > >> >> noise problems, and AD eventually discontinued them. > >> >> > >> >> We have 140 in stock, popcorn fallouts. > >> > > >> > > >> > Would they be useful for a digitally controlled power supply? > >> > >> Sure, if you don't mind the occasional 10 PPM bump. > > > > > > That wouldn't bother me. I want to build some new bench supplies that > >I can program the voltage & current limiting. I would need two per > >output and I'd like at least four outputs. > > I can certainly send you some DACs, and some nice voltage references, > too. You will need a uP and some displays and encoders or something, > too. > > One could also do it as a feedback system, where a 24-bit delta-sigma > ADC would measure the output and servo it to a target value. Some of > those cheap d-s adcs are amazingly good.
I have some LCD displays & encoders. I have some 12x1 LCD displays like these: http://www.ebay.com/itm/180915257890 I have some 16x2 LCD displays like these: http://www.ebay.com/itm/120949311392 I have some similar to these Rotary Encoders: http://www.ebay.com/itm/140739970480 I am learning to program Atmel processors on a Arduino Mega 2560. I just haven't been able to find the DACs. We used some dual 18 bit at Microdyne to set video output levels & DC offset. A lookup table gave accurate .1 dB steps over a range of 0 to -63 dB. I'll send you an email for my address.
John Larkin wrote:


> Could you possibly digitally limit the amount of code change, > essentially digitally slew limit? I have an idea for a deglitcher but > it could only tolerate a half volt or so of voltage step.
Generally doesn't work. There are certain code transitions that produce large spikes, such as the half-scale and the quarter-scale transitions. It is very dependent on the internal construction of the DAC, some are really HORRIBLE, some are much better. Jon
On Wed, 18 Jul 2012 14:20:09 -0500, Jon Elson <jmelson@wustl.edu>
wrote:

>John Larkin wrote: > > >> Could you possibly digitally limit the amount of code change, >> essentially digitally slew limit? I have an idea for a deglitcher but >> it could only tolerate a half volt or so of voltage step. >Generally doesn't work. There are certain code transitions that >produce large spikes, such as the half-scale and the quarter-scale >transitions. It is very dependent on the internal construction of the DAC, >some are really HORRIBLE, some are much better. > >Jon
Sure. But I have an idea for a gated deglitcher, but it wouldn't handle big voltage steps. It might work if Speff can digitally slew-rate-limit the dac steps. Still thinking about it. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Tue, 17 Jul 2012 20:28:29 -0700 (PDT),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Tuesday, July 17, 2012 3:43:21 PM UTC-4, Spehro Pefhany wrote: >> Any clever ideas on getting rid of glitches in a high precision DAC >> output? Update rate is a fixed rate, probably in the 10-100kHz range, >> and I&#39;d like to keep the glitches (especially variation in glitches) >> to &lt;&lt; 25ppm, preferably &lt; 5ppm. A S&amp;H with a low charge injection >> switch? > >One clever idea is the so-called re-glitching technique used by National Instruments for the past 15 years or so. Less is more, no T/H is used. The idea there is to uniformize the glitch energy, or make it code independent, and shift its spectrum to the sampling frequency where the so-called anti-imaging LPF can eliminate it. This can't be done with code-dependent glitch energy since quite a lot of it remains withing the signal band. See US5646620...guess it's still protected though.
A simple slew-rate limiter circuit might make a pretty good deglitcher. Sort of like a lowpass filter, but with more precise settling behavior. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation