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CMOS process at lower voltage?

Started by o pere o March 28, 2012
This is a basic question on CMOS processes. Given a fabrication process 
that is labellled as "1.8V process", is it possible / advisable / etc to 
have a design work at _lower_ voltages? If simulations, for instance at 
1.2V show up OK, is there any risk?

Pere
o pere o wrote:
> > This is a basic question on CMOS processes. Given a fabrication process > that is labellled as "1.8V process", is it possible / advisable / etc to > have a design work at _lower_ voltages? If simulations, for instance at > 1.2V show up OK, is there any risk? > > Pere
There's a whole field dealing with subthreshold CMOS processes, including a recent DARPA program that dealt with subthreshold FPGAs. Chips slow down in funny ways when run at lower voltages than intended, so your simulation software and device models have to be sufficiently sophisticated to do this well. Cheers Phil "Not a chip designer" Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
On Wed, 28 Mar 2012 17:04:53 +0200, o pere o <me@somewhere.net> wrote:

>This is a basic question on CMOS processes. Given a fabrication process >that is labellled as "1.8V process", is it possible / advisable / etc to >have a design work at _lower_ voltages? If simulations, for instance at >1.2V show up OK, is there any risk? > >Pere
A "1.8V CMOS Process" is designed to work at a nominal VDD of 1.8V. While it will operate at lower voltages, speed will suffer and you can get weird behavior when VDD < VTHP+VTHN (sum of thresholds). Sometimes it is necessary to run non-optimum potentials, such as in level translators, say 3.3V down to 1.8V: Input stage 3.3V process running at VDD=3.3V, middle stage 3.3V process running at VDD=1.8V (gate voltage stand-off forces the process), last stage 1.8V process running at VDD=1.8V. And, of course, custom sizing to keep waveform symmetry. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On 3/28/2012 8:04 AM, o pere o wrote:
> This is a basic question on CMOS processes. Given a fabrication process > that is labellled as "1.8V process", is it possible / advisable / etc to > have a design work at _lower_ voltages? If simulations, for instance at > 1.2V show up OK, is there any risk? > > Pere
No problem...as long as your simulation models ACCURATELY describe the guaranteed worst-case behavior when operated at 2/3 the design voltage. And the fabrication house has the hardware and financial incentive to test your parts at 1.2V. Maybe the process designers didn't recognize the enormous potential of a process that worked at 1.2V and erroneously spec'd it at 1.8V. You'd be doing them a favor. Request a consulting fee. You might want to have an exit strategy in case there are problems with the decision. The answers to your questions are yes, no way in hell, huge.
On Wed, 28 Mar 2012 11:17:54 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>o pere o wrote: >> >> This is a basic question on CMOS processes. Given a fabrication process >> that is labellled as "1.8V process", is it possible / advisable / etc to >> have a design work at _lower_ voltages? If simulations, for instance at >> 1.2V show up OK, is there any risk? >> >> Pere > >There's a whole field dealing with subthreshold CMOS processes, >including a recent DARPA program that dealt with subthreshold FPGAs. >Chips slow down in funny ways when run at lower voltages than intended, >so your simulation software and device models have to be sufficiently >sophisticated to do this well. > >Cheers > >Phil "Not a chip designer" Hobbs
Subthreshold operation is usually only an issue with analog circuits... current mirrors not in the saturation region, etc. Good models are critical, but available now from the better process houses. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Phil Hobbs wrote:
> o pere o wrote: >> >> This is a basic question on CMOS processes. Given a fabrication process >> that is labellled as "1.8V process", is it possible / advisable / etc to >> have a design work at _lower_ voltages? If simulations, for instance at >> 1.2V show up OK, is there any risk? >> >> Pere > > There's a whole field dealing with subthreshold CMOS processes, > including a recent DARPA program that dealt with subthreshold FPGAs. > Chips slow down in funny ways when run at lower voltages than intended, > so your simulation software and device models have to be sufficiently > sophisticated to do this well. > > Cheers > > Phil "Not a chip designer" Hobbs
--------------^^----^^ You mean to say you do not use your hatchet in an artistic way, when cutting firewood?
Supposedly, 74HC series logic can even operate at 1.8V -- switching is very 
slow (just as others have mentioned), but the current consumption is very 
small, because both transistors are never conducting at the same time (Vdd < 
2 * Vgs(th) so they don't shoot through).

I would expect the same applies to other processes, but I get the impression 
transconductance isn't proportionally higher in high density processes. 
That is, a 5V process might go from fully off (below threshold) to 
reasonably on over a change of 1V (20% of the supply).  A 1.8V process will 
have higher gain in absolute terms (it might take a change of only 0.8V to 
go from off to on), but it's much lower in relative terms (0.8V is 44% of 
1.8V).  Subthreshold leakage, in very high density, low voltage processes 
(Vdd ~ 1V) occurs when it doesn't even turn off completely, because there 
simply isn't enough voltage available to turn it off.  (That, and the 
structures are so small, current just leaks right on through by tunneling..)

Tim

-- 
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

"o pere o" <me@somewhere.net> wrote in message 
news:jkv9am$k2e$1@dont-email.me...
> This is a basic question on CMOS processes. Given a fabrication process > that is labellled as "1.8V process", is it possible / advisable / etc to > have a design work at _lower_ voltages? If simulations, for instance at > 1.2V show up OK, is there any risk? > > Pere
On 3/28/2012 8:04 AM, o pere o wrote:
> This is a basic question on CMOS processes. Given a fabrication process > that is labellled as "1.8V process", is it possible / advisable / etc to > have a design work at _lower_ voltages? If simulations, for instance at > 1.2V show up OK, is there any risk? > > Pere
Logic or analog? If the design is fully flogged and you want to save some power, I don't see a problem. However you generally get your money's worth operating at the rated voltage. For example, if a lower voltage process existed, it would have thinner gate oxide and thus stronger transistors, probably allowing the chip to be smaller. Look at it this way. There is a class of products designed for naked battery operation. That is, they don't want to deal with DC/DC chips, but rather use parts designed to operate over a wide range. These parts are designed to work at a lower voltage than the upper limit of the process. Lastly, and I don't suggest this, but I have seen low voltage designs on a high voltage process run without field implants. Some schlocky fabs use outside implant services, so if you can skip a field implant, the wafer is cheaper. It sounds like a bad idea to me.
On 03/28/2012 05:58 PM, Jim Thompson wrote:
> On Wed, 28 Mar 2012 11:17:54 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> o pere o wrote: >>> >>> This is a basic question on CMOS processes. Given a fabrication process >>> that is labellled as "1.8V process", is it possible / advisable / etc to >>> have a design work at _lower_ voltages? If simulations, for instance at >>> 1.2V show up OK, is there any risk? >>> >>> Pere >> >> There's a whole field dealing with subthreshold CMOS processes, >> including a recent DARPA program that dealt with subthreshold FPGAs. >> Chips slow down in funny ways when run at lower voltages than intended, >> so your simulation software and device models have to be sufficiently >> sophisticated to do this well. >> >> Cheers >> >> Phil "Not a chip designer" Hobbs > > Subthreshold operation is usually only an issue with analog > circuits... current mirrors not in the saturation region, etc. Good > models are critical, but available now from the better process houses. > > ...Jim Thompson
Thanks for all your inputs! Well, I should have added that this is an analog, more precisely, an RF application. And the objective is, as is easy to guess, power reduction without switching to other, probably more expensive, processes. We have some Cadence simulations using the models from UMC showing good behavior at 1.2V and I was wondering if there may be "hidden effects" that should be considered. Pere
On Thu, 29 Mar 2012 10:51:44 +0200, o pere o <me@somewhere.net> wrote:

>On 03/28/2012 05:58 PM, Jim Thompson wrote: >> On Wed, 28 Mar 2012 11:17:54 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> o pere o wrote: >>>> >>>> This is a basic question on CMOS processes. Given a fabrication process >>>> that is labellled as "1.8V process", is it possible / advisable / etc to >>>> have a design work at _lower_ voltages? If simulations, for instance at >>>> 1.2V show up OK, is there any risk? >>>> >>>> Pere >>> >>> There's a whole field dealing with subthreshold CMOS processes, >>> including a recent DARPA program that dealt with subthreshold FPGAs. >>> Chips slow down in funny ways when run at lower voltages than intended, >>> so your simulation software and device models have to be sufficiently >>> sophisticated to do this well. >>> >>> Cheers >>> >>> Phil "Not a chip designer" Hobbs >> >> Subthreshold operation is usually only an issue with analog >> circuits... current mirrors not in the saturation region, etc. Good >> models are critical, but available now from the better process houses. >> >> ...Jim Thompson > >Thanks for all your inputs! Well, I should have added that this is an >analog, more precisely, an RF application. And the objective is, as is >easy to guess, power reduction without switching to other, probably more >expensive, processes. We have some Cadence simulations using the models >from UMC showing good behavior at 1.2V and I was wondering if there may >be "hidden effects" that should be considered. > >Pere
I have used UMC models dated 2010 and Hejian/UMC models dated 2011 with good success, so you should be OK... using PSpice at 1/10 the cost of the average Cadence tool set ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.