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Stable simple dc amplifiers

Started by Archival March 11, 2012
Jim Thompson wrote:
> On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer > <robertbaer@localnet.com> wrote: > >> Jim Thompson wrote: >>> > [snip] >>> >>> In the I/C world a "pure" diode, unencumbered by parasitic junctions >>> does not exist. So you can rest assured that a "diode" on an I/C >>> schematic is actually a three (or more) layer device, connected in >>> diode mode. >>> >>> That's why I'm always wary of more than trivial currents in ESD >>> "diodes"... the positive rail one (in most processes) is actually a >>> PNP with a very BIG collector (otherwise known as the whole device >>> substrate)... and the "guard ring" diffusions to limit parasitic >>> action DO NOT go all the way thru the die thickness. >>> >>> ...Jim Thompson >> Check and double check. >> Start with something simple to illustrate: two "isolated" NPNs on a >> substrate. In one case, if properly done in a geometrical fashion, they >> will be matched extremely well (beta,leakage) with good thermal tracking >> (better than 10mSec hysteresis). >> In another case, in a high gain op-amp, the lateral PNP (base is the >> substrate) > > Almost correct. See... > > http://www.analog-innovations.com/SED/NPN-VPNP.pdf > > This is a typical bipolar process cross-section. CMOS? Still a > P-type substrate. > > A lateral-PNP is like a vertical-PNP except there are two P-base > emitters side-by-side... plus a feeble attempt to kill the vertical > device by adding buried layer > >> Q1 to Q2 could have a beta of 0.000001 or so and give hell in >> feedback - all the way across a chip where Q1 is part the op-amp input >> and Q2 is part of the output. >> A measly gain over 10^6 can be trouble in river city. >> Happened in the first cut for the uA741 at (the original) Fairchild. >> If i remember right, the solution was to wrap a vertical PNP around >> the output and make it a DCT to kill the beta across the chip. > > But you are right, all kinds of sneak paths to "brighten" (*) your > day. > > (*) I had a complex pin driver chip, ~1980, that glowed in the dark > ;-) > > ...Jim Thompson
Too bad that the glow effect was not looked into..then become an early LED and maybe an analog controllable LED.
Robert Baer wrote:
> > Jim Thompson wrote: > > On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer > > <robertbaer@localnet.com> wrote: > > > >> Jim Thompson wrote: > >>> > > [snip] > >>> > >>> In the I/C world a "pure" diode, unencumbered by parasitic junctions > >>> does not exist. So you can rest assured that a "diode" on an I/C > >>> schematic is actually a three (or more) layer device, connected in > >>> diode mode. > >>> > >>> That's why I'm always wary of more than trivial currents in ESD > >>> "diodes"... the positive rail one (in most processes) is actually a > >>> PNP with a very BIG collector (otherwise known as the whole device > >>> substrate)... and the "guard ring" diffusions to limit parasitic > >>> action DO NOT go all the way thru the die thickness. > >>> > >>> ...Jim Thompson > >> Check and double check. > >> Start with something simple to illustrate: two "isolated" NPNs on a > >> substrate. In one case, if properly done in a geometrical fashion, they > >> will be matched extremely well (beta,leakage) with good thermal tracking > >> (better than 10mSec hysteresis). > >> In another case, in a high gain op-amp, the lateral PNP (base is the > >> substrate) > > > > Almost correct. See... > > > > http://www.analog-innovations.com/SED/NPN-VPNP.pdf > > > > This is a typical bipolar process cross-section. CMOS? Still a > > P-type substrate. > > > > A lateral-PNP is like a vertical-PNP except there are two P-base > > emitters side-by-side... plus a feeble attempt to kill the vertical > > device by adding buried layer > > > >> Q1 to Q2 could have a beta of 0.000001 or so and give hell in > >> feedback - all the way across a chip where Q1 is part the op-amp input > >> and Q2 is part of the output. > >> A measly gain over 10^6 can be trouble in river city. > >> Happened in the first cut for the uA741 at (the original) Fairchild. > >> If i remember right, the solution was to wrap a vertical PNP around > >> the output and make it a DCT to kill the beta across the chip. > > > > But you are right, all kinds of sneak paths to "brighten" (*) your > > day. > > > > (*) I had a complex pin driver chip, ~1980, that glowed in the dark > > ;-) > > > > ...Jim Thompson > Too bad that the glow effect was not looked into..then become an > early LED and maybe an analog controllable LED.
Photoemission from silicon is a commonly-used diagnostic tool. Ordinary recombination produces ~1.1 um photons, which you can see through a thinned die, and hot carriers produce visible photons. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
On Sun, 18 Mar 2012 20:27:56 -0800, Robert Baer
<robertbaer@localnet.com> wrote:

>Jim Thompson wrote: >> On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer >> <robertbaer@localnet.com> wrote: >> >>> Jim Thompson wrote: >>>> >> [snip] >>>> >>>> In the I/C world a "pure" diode, unencumbered by parasitic junctions >>>> does not exist. So you can rest assured that a "diode" on an I/C >>>> schematic is actually a three (or more) layer device, connected in >>>> diode mode. >>>> >>>> That's why I'm always wary of more than trivial currents in ESD >>>> "diodes"... the positive rail one (in most processes) is actually a >>>> PNP with a very BIG collector (otherwise known as the whole device >>>> substrate)... and the "guard ring" diffusions to limit parasitic >>>> action DO NOT go all the way thru the die thickness. >>>> >>>> ...Jim Thompson >>> Check and double check. >>> Start with something simple to illustrate: two "isolated" NPNs on a >>> substrate. In one case, if properly done in a geometrical fashion, they >>> will be matched extremely well (beta,leakage) with good thermal tracking >>> (better than 10mSec hysteresis). >>> In another case, in a high gain op-amp, the lateral PNP (base is the >>> substrate) >> >> Almost correct. See... >> >> http://www.analog-innovations.com/SED/NPN-VPNP.pdf >> >> This is a typical bipolar process cross-section. CMOS? Still a >> P-type substrate. >> >> A lateral-PNP is like a vertical-PNP except there are two P-base >> emitters side-by-side... plus a feeble attempt to kill the vertical >> device by adding buried layer >> >>> Q1 to Q2 could have a beta of 0.000001 or so and give hell in >>> feedback - all the way across a chip where Q1 is part the op-amp input >>> and Q2 is part of the output. >>> A measly gain over 10^6 can be trouble in river city. >>> Happened in the first cut for the uA741 at (the original) Fairchild. >>> If i remember right, the solution was to wrap a vertical PNP around >>> the output and make it a DCT to kill the beta across the chip. >> >> But you are right, all kinds of sneak paths to "brighten" (*) your >> day. >> >> (*) I had a complex pin driver chip, ~1980, that glowed in the dark >> ;-) >> >> ...Jim Thompson > Too bad that the glow effect was not looked into..then become an >early LED and maybe an analog controllable LED.
That was back in the days when we didn't have multi-layer metal, so an N+ crossover made an unintended device that light-emitted. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.