# Clock Frequency Synthesis

Started by January 26, 2012
```I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

I will do this by filtering out the harmonics of a square wave with an
MAX294 switched capacitor filter:
http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdf
I will need to clock each of the six filter chips at approximately 167
times the frequency of the square wave to be filtered. This is to get
the third harmonic in the notch shown at 1.8kHz in the MAX294
frequency response curve on page 4.

Before I look into programing the dividers and timers into an FPGA to
synthesize these 12 frequencies from a single reference frequency I am
looking for off the shelf logic that can do this in just a few chips.
What can you suggest?

The sine waves will be used to drive LEDs that illuminate optrodes. It
is expected there will be a small amount of light crosstalking into
the other channels. The crosstalk will be eliminated by FFT on the
output of the photodiode's TIA. Maximum suppression of crosstalk will
happen when the channel frequencies are a multiple of 1/T where T is
the length of time the transform is done over. T can be 100 ms, 200
ms, 500 ms or 1 s.
```
```On Wed, 25 Jan 2012 21:46:51 -0800, spflanze wrote:

> I need to design a sine wave synthesizer for six channels. Each channel
> must have a different frequency and be an exact multiple of 1Hz.
> Frequency ranges are from 100Hz to 1Khz.
>
> I will do this by filtering out the harmonics of a square wave with an
> MAX294 switched capacitor filter:
> http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdf I will need to
> clock each of the six filter chips at approximately 167 times the
> frequency of the square wave to be filtered. This is to get the third
> harmonic in the notch shown at 1.8kHz in the MAX294 frequency response
> curve on page 4.
>
> Before I look into programing the dividers and timers into an FPGA to
> synthesize these 12 frequencies from a single reference frequency I am
> looking for off the shelf logic that can do this in just a few chips.
> What can you suggest?
>
> The sine waves will be used to drive LEDs that illuminate optrodes. It
> is expected there will be a small amount of light crosstalking into the
> other channels. The crosstalk will be eliminated by FFT on the output of
> the photodiode's TIA. Maximum suppression of crosstalk will happen when
> the channel frequencies are a multiple of 1/T where T is the length of
> time the transform is done over. T can be 100 ms, 200 ms, 500 ms or 1 s.

I suggest that you ditch the idea of doing it with a switched capacitor
filters and frequency synthesis, and instead do it by direct digital
synthesis and some ADCs.  One reasonably fast microprocessor (32-bit ARM
Cortex) should be able to handle six channels with ease.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
```
```On Jan 26, 6:46=A0am, spflanze <art...@wavenet.org> wrote:
> I need to design a sine wave synthesizer for six channels. Each
> channel must have a different frequency and be an exact multiple of
> 1Hz. Frequency ranges are from 100Hz to 1Khz.

Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
820Hz, 1kHz.

If you started off with a 64kHz oscillator, you'd divide that by 640
to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
inside  a single programmable logic device.

If you want eight 167 times faster clocks for the switched capacitor
filters, you could multiply 64kHz by 167 giving you a clock frequency
of 10.688MHz, which is pretty much the ideal crystal frequency, and
complicate your programmable logic device appropriately.

With a higher starting frequency you could get more evenly spaced
modulation frequencies that were exact multiples of 1Hz. The
programmable logic device would start drawing lots of current if you
did.

<snip>

--
Bill Sloman, Nijmegen
```
```On Jan 26, 2:37=A0am, Tim Wescott <t...@seemywebsite.please> wrote:
> On Wed, 25 Jan 2012 21:46:51 -0800, spflanze wrote:
> > I need to design a sine wave synthesizer for six channels. Each channel
> > must have a different frequency and be an exact multiple of 1Hz.
> > Frequency ranges are from 100Hz to 1Khz.
>
> > I will do this by filtering out the harmonics of a square wave with an
> > MAX294 switched capacitor filter:
> >http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdfI will need to
> > clock each of the six filter chips at approximately 167 times the
> > frequency of the square wave to be filtered. This is to get the third
> > harmonic in the notch shown at 1.8kHz in the MAX294 frequency response
> > curve on page 4.
>
> > Before I look into programing the dividers and timers into an FPGA to
> > synthesize these 12 frequencies from a single reference frequency I am
> > looking for off the shelf logic that can do this in just a few chips.
> > What can you suggest?
>
> > The sine waves will be used to drive LEDs that illuminate optrodes. It
> > is expected there will be a small amount of light crosstalking into the
> > other channels. The crosstalk will be eliminated by FFT on the output o=
f
> > the photodiode's TIA. Maximum suppression of crosstalk will happen when
> > the channel frequencies are a multiple of 1/T where T is the length of
> > time the transform is done over. T can be 100 ms, 200 ms, 500 ms or 1 s=
.
>
> I suggest that you ditch the idea of doing it with a switched capacitor
> filters and frequency synthesis, and instead do it by direct digital
> synthesis and some ADCs. =A0One reasonably fast microprocessor (32-bit AR=
M
> Cortex) should be able to handle six channels with ease.
>
> --
> Tim Wescott
> Control system and signal processing consultingwww.wescottdesign.com- Hid=
e quoted text -
>
> - Show quoted text -

I've only used a switched cap filters once.  LTC1063.  There were
(what we called) intermodulation distortion at the ~45-50dB level.  It
took a while to identify the SCF as the source.

Switched cap filters sound so nice 'in theory'.

To the spflanze; why so low frequencies?  Wouldn't it be easier to
work up at maybe the 10kHz range... and put 1kHz (or so) between
channels?   And then forget about the harmonics.  Or one nice analog
low pass after the photodiodes to kill them all.

George H.
```
```On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman
<bill.sloman@ieee.org> wrote:

>On Jan 26, 6:46&#2013266080;am, spflanze <art...@wavenet.org> wrote:
>> I need to design a sine wave synthesizer for six channels. Each
>> channel must have a different frequency and be an exact multiple of
>> 1Hz. Frequency ranges are from 100Hz to 1Khz.
>
>Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
>820Hz, 1kHz.
>
>If you started off with a 64kHz oscillator, you'd divide that by 640
>to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
>640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
>inside  a single programmable logic device.
>
>If you want eight 167 times faster clocks for the switched capacitor
>filters, you could multiply 64kHz by 167 giving you a clock frequency
>of 10.688MHz, which is pretty much the ideal crystal frequency, and
>complicate your programmable logic device appropriately.
>
>With a higher starting frequency you could get more evenly spaced
>modulation frequencies that were exact multiples of 1Hz. The
>programmable logic device would start drawing lots of current if you
>did.
>

Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
logic at a 50 MHz clock for a few mA of Icc.

John

```
```On Thu, 26 Jan 2012 07:19:19 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman
><bill.sloman@ieee.org> wrote:
>
>>On Jan 26, 6:46&#2013266080;am, spflanze <art...@wavenet.org> wrote:
>>> I need to design a sine wave synthesizer for six channels. Each
>>> channel must have a different frequency and be an exact multiple of
>>> 1Hz. Frequency ranges are from 100Hz to 1Khz.
>>
>>Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
>>820Hz, 1kHz.
>>
>>If you started off with a 64kHz oscillator, you'd divide that by 640
>>to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
>>640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
>>inside  a single programmable logic device.
>>
>>If you want eight 167 times faster clocks for the switched capacitor
>>filters, you could multiply 64kHz by 167 giving you a clock frequency
>>of 10.688MHz, which is pretty much the ideal crystal frequency, and
>>complicate your programmable logic device appropriately.
>>
>>With a higher starting frequency you could get more evenly spaced
>>modulation frequencies that were exact multiples of 1Hz. The
>>programmable logic device would start drawing lots of current if you
>>did.
>>
>
>Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
>logic at a 50 MHz clock for a few mA of Icc.
>
>John

Yep. 50MHz is _audio_ with today's chips :-)

...Jim Thompson
--
| James E.Thompson, CTO                            |    mens     |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

I love to cook with wine.     Sometimes I even put it in the food.
```
```Tim Wescott wrote:

> On Wed, 25 Jan 2012 21:46:51 -0800, spflanze wrote:
>
>> I need to design a sine wave synthesizer for six channels. Each channel
>> must have a different frequency and be an exact multiple of 1Hz.
>> Frequency ranges are from 100Hz to 1Khz.
>>
>> I will do this by filtering out the harmonics of a square wave with an
>> MAX294 switched capacitor filter:
>> http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdf I will need to
>> clock each of the six filter chips at approximately 167 times the
>> frequency of the square wave to be filtered. This is to get the third
>> harmonic in the notch shown at 1.8kHz in the MAX294 frequency response
>> curve on page 4.
>>
>> Before I look into programing the dividers and timers into an FPGA to
>> synthesize these 12 frequencies from a single reference frequency I am
>> looking for off the shelf logic that can do this in just a few chips.
>> What can you suggest?
>>
>> The sine waves will be used to drive LEDs that illuminate optrodes. It
>> is expected there will be a small amount of light crosstalking into the
>> other channels. The crosstalk will be eliminated by FFT on the output of
>> the photodiode's TIA. Maximum suppression of crosstalk will happen when
>> the channel frequencies are a multiple of 1/T where T is the length of
>> time the transform is done over. T can be 100 ms, 200 ms, 500 ms or 1 s.
>
> I suggest that you ditch the idea of doing it with a switched capacitor
> filters and frequency synthesis, and instead do it by direct digital
> synthesis and some ADCs.  One reasonably fast microprocessor (32-bit ARM
> Cortex) should be able to handle six channels with ease.
>
Those would actually be DACs, but otherwise I completely agree.
The DDS is simple, running 6 channels might use up a lot of I/O pins
unless he uses serial DACs.  A very simple filter at the output of the
DAC will remove any quantization and other noises and result in a VERY
pure signal.

Jon
```
```On Jan 26, 4:19=A0pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman
>
>
>
>
>
>
>
>
>
> <bill.slo...@ieee.org> wrote:
> >On Jan 26, 6:46=A0am, spflanze <art...@wavenet.org> wrote:
> >> I need to design a sine wave synthesizer for six channels. Each
> >> channel must have a different frequency and be an exact multiple of
> >> 1Hz. Frequency ranges are from 100Hz to 1Khz.
>
> >Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
> >820Hz, 1kHz.
>
> >If you started off with a 64kHz oscillator, you'd divide that by 640
> >to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
> >640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
> >inside =A0a single programmable logic device.
>
> >If you want eight 167 times faster clocks for the switched capacitor
> >filters, you could multiply 64kHz by 167 giving you a clock frequency
> >of 10.688MHz, which is pretty much the ideal crystal frequency, and
> >complicate your programmable logic device appropriately.
>
> >With a higher starting frequency you could get more evenly spaced
> >modulation frequencies that were exact multiples of 1Hz. The
> >programmable logic device would start drawing lots of current if you
> >did.
>
> Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
> logic at a 50 MHz clock for a few mA of Icc.

This thing is supposed to be battery operated.

Actually, a more rational choice of frequencies is based on 10^1/6,
1.47

which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
and 1kHz which doesn't lend itself to dividing down from a single
clock, since 147 and 317 are prime numbers.

The 6-bit SN7497 binary rate multiplier could cope with this sort of
problem - it did generate an irregular pulse train, so you had to
follow it with a regular divider that reduces the pulse rate by 2^6 to
smooth out the variations.

2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
100Hz - close enough for government work.

Getting the 167-fold higher frequencies for the switched capacitor
filters means duplicating the logic from a 13.68064MHz clock, which is
entirely practical.

You can obviously duplicate the internal logic of 7497 inside the

--
Bill Sloman, Nijmegen

--
Bill Sloman, Nijmegen

```
```On Thu, 26 Jan 2012 11:51:49 -0600, Jon Elson wrote:

> Tim Wescott wrote:
>
>> On Wed, 25 Jan 2012 21:46:51 -0800, spflanze wrote:
>>
>>> I need to design a sine wave synthesizer for six channels. Each
>>> channel must have a different frequency and be an exact multiple of
>>> 1Hz. Frequency ranges are from 100Hz to 1Khz.
>>>
>>> I will do this by filtering out the harmonics of a square wave with an
>>> MAX294 switched capacitor filter:
>>> http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdf I will need to
>>> clock each of the six filter chips at approximately 167 times the
>>> frequency of the square wave to be filtered. This is to get the third
>>> harmonic in the notch shown at 1.8kHz in the MAX294 frequency response
>>> curve on page 4.
>>>
>>> Before I look into programing the dividers and timers into an FPGA to
>>> synthesize these 12 frequencies from a single reference frequency I am
>>> looking for off the shelf logic that can do this in just a few chips.
>>> What can you suggest?
>>>
>>> The sine waves will be used to drive LEDs that illuminate optrodes. It
>>> is expected there will be a small amount of light crosstalking into
>>> the other channels. The crosstalk will be eliminated by FFT on the
>>> output of the photodiode's TIA. Maximum suppression of crosstalk will
>>> happen when the channel frequencies are a multiple of 1/T where T is
>>> the length of time the transform is done over. T can be 100 ms, 200
>>> ms, 500 ms or 1 s.
>>
>> I suggest that you ditch the idea of doing it with a switched capacitor
>> filters and frequency synthesis, and instead do it by direct digital
>> synthesis and some ADCs.  One reasonably fast microprocessor (32-bit
>> ARM Cortex) should be able to handle six channels with ease.
>>
> Those would actually be DACs, but otherwise I completely agree. The DDS
> is simple, running 6 channels might use up a lot of I/O pins unless he
> uses serial DACs.  A very simple filter at the output of the DAC will
> remove any quantization and other noises and result in a VERY pure
> signal.

DDS with ADC's would be a challenge, wouldn't it?

Dyslexics Untie!!

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
```
```On 26 Jan., 18:52, Bill Sloman <bill.slo...@ieee.org> wrote:
> On Jan 26, 4:19=A0pm, John Larkin
>
>
>
>
>
>
>
>
>
> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> > On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman
>
> > <bill.slo...@ieee.org> wrote:
> > >On Jan 26, 6:46=A0am, spflanze <art...@wavenet.org> wrote:
> > >> I need to design a sine wave synthesizer for six channels. Each
> > >> channel must have a different frequency and be an exact multiple of
> > >> 1Hz. Frequency ranges are from 100Hz to 1Khz.
>
> > >Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
> > >820Hz, 1kHz.
>
> > >If you started off with a 64kHz oscillator, you'd divide that by 640
> > >to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
> > >640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
> > >inside =A0a single programmable logic device.
>
> > >If you want eight 167 times faster clocks for the switched capacitor
> > >filters, you could multiply 64kHz by 167 giving you a clock frequency
> > >of 10.688MHz, which is pretty much the ideal crystal frequency, and
> > >complicate your programmable logic device appropriately.
>
> > >With a higher starting frequency you could get more evenly spaced
> > >modulation frequencies that were exact multiples of 1Hz. The
> > >programmable logic device would start drawing lots of current if you
> > >did.
>
> > Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
> > logic at a 50 MHz clock for a few mA of Icc.
>
> This thing is supposed to be battery operated.
>
> Actually, a more rational choice of frequencies is based on 10^1/6,
> 1.47
>
> which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
> and 1kHz which doesn't lend itself to dividing down from a single
> clock, since 147 and 317 are prime numbers.
>
> The 6-bit SN7497 binary rate multiplier could cope with this sort of
> problem - it did generate an irregular pulse train, so you had to
> follow it with a regular divider that reduces the pulse rate by 2^6 to
> smooth out the variations.
>
> 2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
> multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
> would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
> 11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
> 100Hz - close enough for government work.
>
> Getting the 167-fold higher frequencies for the switched capacitor
> filters means duplicating the logic from a 13.68064MHz clock, which is
> entirely practical.
>
> You can obviously duplicate the internal logic of 7497 inside the
> programmable logic of your choice.
>
> --
> Bill Sloman, Nijmegen

instead of messing with a bunch of logic, use something like an
stm32f4xx
cortex ARM with lots of timers, capable of running at +100MHz

-Lasse
```