capacitive loading an opamp

"Jamie" <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote in 
message news:jCHLq.11599$SG3.711@newsfe11.iad...
>   What i've found is that PNP's seem to have a high failure rate, mostly
> in the loss of hfe and some times open in the base. I think some where I
> read once it was a process issue that caused the problem with some PNP 
> devices.

Failure has many causes, excess heat, breakdown, those sorts of things, 
but they are all aggravated by impurities.  Excess doping (a 5-layer PNP) 
would have lots of impurities, so much that I would think it would be 
fairly useless.  Epitaxial PNP might be acceptable (freedom in voltage 
ratings and current gain, high speed), but because epitaxy is a deposition 
process, it has more dislocations than substrate silicon.  The impurities 
and dislocations usually increase speed (more "recombination centers" for 
spare electrons and holes to get stuck on and reunite through), but they 
also worsen those other properties.

The question, are monolithic PNP as reliable as NPN on a complementary 
process, I would expect NPN are given priority on process refinements, 
because they perform slightly better and deserve those refinements.  Even 
if they are made equal, the slightly poorer performance (higher Vce(sat), 
or lower gain, allowing the NPN to desaturate the PNP) may cause it to 
fail first.  But a much wider answer would have to ask in return, what 
circuit is it in?  Often, a PNP is added where required, and the rest 
handled in NPN; this makes very asymmetrical circuits when it comes to 
balanced outputs.  Even with equal transistor parameters, a 
quasi-complementary output stage might simply be driven with more pull-up 
current than pull-down, causing the PNP to dominate under fault 
conditions.

>  As for the latch up, I thought that problem for the most part was
> relevant in CMOS only? Due to how the CMOS is done, a thyristor bipolar
> body is naturally formed as part of the CMOS design and there for will
> trigger if gate for example exceeds Vdd > .7. Maybe I got my ducks mixed
> up, but what ever.

I might be mistaken as well.  It's my recollection that NPNs are made with 
an N-well (the collector) embedded in a P-substrate, and putting two more 
junctions on top of that necessarily makes a four layer device.

It is worth noting that a regular thyristor goes PN-PN, where the first 
junction is forward-biased by the anode voltage, the second is reverse 
biased (making the common collector region between the PNP and NPN 
effective sections) and the third one by the gate (under user control). 
When a thyristor is reverse-biased, it goes P-NPN and nothing can happen, 
because even if the NPN is turned on, the top P-N junction is 
reverse-biased, requiring charge to diffuse all the way across the (wide, 
lightly doped) middle N region.  This current is going to be weak -- the 
NPN essentially has a collector on its collector, and most of the charge 
recombines in the first before any can reach the second.  I would expect 
leakage current to increase (I should try this and see), but it obviously 
won't remain on.

To get the thyristor into an active form, the NPN collector would have to 
be brought below substrate (i.e., ground), which would activate the 
substrate PNP as well.  This would be a pretty darn good way to activate 
it, and inductive loads on outputs would easily achieve this.

Lateral PNP are intended primarily to send current sideways, but 
(depending on the thickness of the N-well), they should work just dandy 
producing substrate current as well, although without latchup (they could 
induce latchup in nearby transistors due to the substrate current).

For these two reasons, I expect they go to great lengths -- deep N-wells, 
guard rings, that sort of stuff -- to prevent latchup in bipolar circuits.


Now, as for CMOS, it has the same sort of structures (now NPN and PNP 
structures are always lateral, and both N- and P-wells are required), but 
under normal operation, it's all nice and clean, signals stay within the 
rails, no minority carriers to splash around, wells can be as shallow as 
you want.  But if you need a robust process, you still need all those 
space-hogging features that bipolar requires by default.  On the upside, 
it's great for LSI/VLSI, because you can reasonably assume all your low 
level internal circuitry isn't going to be bothered by any of the nasty 
outside world.  The result, of course, is a sizable fraction of die area 
committed to pin structures (input protection diodes and isolation, output 
transistors and latchup protection), while a microscopic blob of logic 
provides the functionality.

Tim

-- 
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms 

Tim Williams wrote:

> "Jamie" <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote in 
> message news:jCHLq.11599$SG3.711@newsfe11.iad...
> 
>>  What i've found is that PNP's seem to have a high failure rate, mostly
>>in the loss of hfe and some times open in the base. I think some where I
>>read once it was a process issue that caused the problem with some PNP 
>>devices.
> 
> 
> Failure has many causes, excess heat, breakdown, those sorts of things, 
> but they are all aggravated by impurities.  Excess doping (a 5-layer PNP) 
> would have lots of impurities, so much that I would think it would be 
> fairly useless.  Epitaxial PNP might be acceptable (freedom in voltage 
> ratings and current gain, high speed), but because epitaxy is a deposition 
> process, it has more dislocations than substrate silicon.  The impurities 
> and dislocations usually increase speed (more "recombination centers" for 
> spare electrons and holes to get stuck on and reunite through), but they 
> also worsen those other properties.
> 
> The question, are monolithic PNP as reliable as NPN on a complementary 
> process, I would expect NPN are given priority on process refinements, 
> because they perform slightly better and deserve those refinements.  Even 
> if they are made equal, the slightly poorer performance (higher Vce(sat), 
> or lower gain, allowing the NPN to desaturate the PNP) may cause it to 
> fail first.  But a much wider answer would have to ask in return, what 
> circuit is it in?  Often, a PNP is added where required, and the rest 
> handled in NPN; this makes very asymmetrical circuits when it comes to 
> balanced outputs.  Even with equal transistor parameters, a 
> quasi-complementary output stage might simply be driven with more pull-up 
> current than pull-down, causing the PNP to dominate under fault 
> conditions.
> 
> 
>> As for the latch up, I thought that problem for the most part was
>>relevant in CMOS only? Due to how the CMOS is done, a thyristor bipolar
>>body is naturally formed as part of the CMOS design and there for will
>>trigger if gate for example exceeds Vdd > .7. Maybe I got my ducks mixed
>>up, but what ever.
> 
> 
> I might be mistaken as well.  It's my recollection that NPNs are made with 
> an N-well (the collector) embedded in a P-substrate, and putting two more 
> junctions on top of that necessarily makes a four layer device.
> 
> It is worth noting that a regular thyristor goes PN-PN, where the first 
> junction is forward-biased by the anode voltage, the second is reverse 
> biased (making the common collector region between the PNP and NPN 
> effective sections) and the third one by the gate (under user control). 
> When a thyristor is reverse-biased, it goes P-NPN and nothing can happen, 
> because even if the NPN is turned on, the top P-N junction is 
> reverse-biased, requiring charge to diffuse all the way across the (wide, 
> lightly doped) middle N region.  This current is going to be weak -- the 
> NPN essentially has a collector on its collector, and most of the charge 
> recombines in the first before any can reach the second.  I would expect 
> leakage current to increase (I should try this and see), but it obviously 
> won't remain on.
> 
> To get the thyristor into an active form, the NPN collector would have to 
> be brought below substrate (i.e., ground), which would activate the 
> substrate PNP as well.  This would be a pretty darn good way to activate 
> it, and inductive loads on outputs would easily achieve this.
> 
> Lateral PNP are intended primarily to send current sideways, but 
> (depending on the thickness of the N-well), they should work just dandy 
> producing substrate current as well, although without latchup (they could 
> induce latchup in nearby transistors due to the substrate current).
> 
> For these two reasons, I expect they go to great lengths -- deep N-wells, 
> guard rings, that sort of stuff -- to prevent latchup in bipolar circuits.
> 
> 
> Now, as for CMOS, it has the same sort of structures (now NPN and PNP 
> structures are always lateral, and both N- and P-wells are required), but 
> under normal operation, it's all nice and clean, signals stay within the 
> rails, no minority carriers to splash around, wells can be as shallow as 
> you want.  But if you need a robust process, you still need all those 
> space-hogging features that bipolar requires by default.  On the upside, 
> it's great for LSI/VLSI, because you can reasonably assume all your low 
> level internal circuitry isn't going to be bothered by any of the nasty 
> outside world.  The result, of course, is a sizable fraction of die area 
> committed to pin structures (input protection diodes and isolation, output 
> transistors and latchup protection), while a microscopic blob of logic 
> provides the functionality.
> 
> Tim
> 
interesting.

    I don't know if you were here in the past when I had a strange batch
of smt 2222's that exhibited what looked like self oscillation when 
testing them in a basic common emitter circuit with a high side R as the
load?
   If You carefully advance the base bias and keep a watch on the 
collect, there was a point you would see a burp in voltage at the 
collector.  Playing with the bias, I could keep it there.

  So, I was able to use the older Lecroy scope we had to took a
delayed, widen snap shot of that area. It was actually an oscillation 
taking place but it was only ~50mv p-p. Moving the bias up/down or 
waiting for beta to change due to tempco, would put this out of scope.

   We did these test because this lot was used in a  0..1 volt inverter 
stage to another section and found it not to behaving correctly.

   We tried various configs and it did not matter, other than putting a 
heavy cap on the collector, which that wasn't going to work for us.

    Dampening the base with a heavy cap only reduced it a small portion 
but did not fix it.

    We ended up getting another 100 of these units from our supplier 
after we explained the issue, they didn't have any problems replacing 
them. I kind of think that maybe I wasn't the only one? On top of that,
they are kind of cheap any way.

   The replacements were perfect.

   P.S.
     These units worked fine in a switching state, just not in linear 
mode at a precise current state.

Jamie

"Jamie" <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote in 
message news:wEJLq.46735$U16.45935@newsfe15.iad...
>    I don't know if you were here in the past when I had a strange batch
> of smt 2222's that exhibited what looked like self oscillation when 
> testing them in a basic common emitter circuit with a high side R as the
> load?
>   If You carefully advance the base bias and keep a watch on the 
> collect, there was a point you would see a burp in voltage at the 
> collector.  Playing with the bias, I could keep it there.
>
>  So, I was able to use the older Lecroy scope we had to took a
> delayed, widen snap shot of that area. It was actually an oscillation 
> taking place but it was only ~50mv p-p. Moving the bias up/down or 
> waiting for beta to change due to tempco, would put this out of scope.

Cool.

IIRC, the gist of the replies was, 2N2222 has shit for specs, so the fT 
could be pretty much...anywhere.

Base bypass is usually the last thing you want; series base resistance 
helps reduce fT a bit, particularly in followers and diff amps.  Can also 
try miller compensation, which works especially well with series input 
resistance.  This is either a small cap across B-C, or cap+resistor to 
increase phase margin.

If wiring still had no effect on the oscillation, they could very well be 
duds.  I wonder what kind of defects would even do that.  Point avalanche 
perhaps?  But then it wouldn't go away at higher bias... outside chance it 
could be a trap state or something, which only shows up at certain 
voltages, but I don't have a clue if something like that can even occur in 
a regular planar transistor.

Likely, if it is a defect, leakage might be out of spec, or the reverse 
bias curve might have kinks or something.  Of course, there's a lot more 
V-I curve to explore than is worth a hundred 2N2222s...

I never use 2N2222s because they're too old and poorly specified.  I 
always get 2N3904/6 for "high speed" duty (under 20MHz, but I seem to be 
pushing up the clock rate every month ;) ), and 4401/3 for driver / output 
/ switching purposes.  Anything more is special order, e.g. ZTX651 or 
PBSS4540 for those times when you need a big gulp of current.

Tim

-- 
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms 

On Dec 31 2011, 7:05=A0pm, Jamie
<jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> Joerg wrote:
> > Oppie wrote:
>
> >>"Spehro Pefhany" <speffS...@interlogDOTyou.knowwhat> wrote in message
> >>news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com...
>
> >>>I figured that out while I was still in high school- that app notes
> >>>were generally not written by anyone resembling a practicing engineer.
> >>>Mostly by being bitten by their example circuits.
>
> >>With a few notable exceptions like Jim Williams.
> >>I really miss his crumby scope photos and clear writing style that not
> >>only sold parts but helped us to understand WHY things worked. There ar=
e
> >>many trade-offs in a design and understanding the basics puts a value o=
n
> >>those choices.
>
> > Yep. A good engineer quickly learns to first look at the author's name.
> > If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one
> > of the other gurus I know it's good stuff.
>
> =A0 Oh boy, you know how to get brownie points. Was there something a
> mystery you've been working on lately? I am sure one of those guys will
> charm right in now :)

Jim Williams, Bob Pease and Robert Widlar are dead, Bob Widlar for
some years now.

Dan Banerjee still seems to be with us, but since he works for
National Semiconductor, Joerg probably doesn't authorise enough parts
per year to qualify for his interest.

You seem to be even more out of touch with reality than Jim Thopmson,
who does still seem to know about electronics gurus, presumably
because he's yet to lose contact with the realities of electronics.

--
Bill Sloman, Nijmegen

Tim Williams wrote:

> "Jamie" <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote in 
> message news:wEJLq.46735$U16.45935@newsfe15.iad...
> 
>>   I don't know if you were here in the past when I had a strange batch
>>of smt 2222's that exhibited what looked like self oscillation when 
>>testing them in a basic common emitter circuit with a high side R as the
>>load?
>>  If You carefully advance the base bias and keep a watch on the 
>>collect, there was a point you would see a burp in voltage at the 
>>collector.  Playing with the bias, I could keep it there.
>>
>> So, I was able to use the older Lecroy scope we had to took a
>>delayed, widen snap shot of that area. It was actually an oscillation 
>>taking place but it was only ~50mv p-p. Moving the bias up/down or 
>>waiting for beta to change due to tempco, would put this out of scope.
> 
> 
> Cool.
> 
> IIRC, the gist of the replies was, 2N2222 has shit for specs, so the fT 
> could be pretty much...anywhere.
> 
> Base bypass is usually the last thing you want; series base resistance 
> helps reduce fT a bit, particularly in followers and diff amps.  Can also 
> try miller compensation, which works especially well with series input 
> resistance.  This is either a small cap across B-C, or cap+resistor to 
> increase phase margin.
> 
> If wiring still had no effect on the oscillation, they could very well be 
> duds.  I wonder what kind of defects would even do that.  Point avalanche 
> perhaps?  But then it wouldn't go away at higher bias... outside chance it 
> could be a trap state or something, which only shows up at certain 
> voltages, but I don't have a clue if something like that can even occur in 
> a regular planar transistor.
> 
> Likely, if it is a defect, leakage might be out of spec, or the reverse 
> bias curve might have kinks or something.  Of course, there's a lot more 
> V-I curve to explore than is worth a hundred 2N2222s...
> 
> I never use 2N2222s because they're too old and poorly specified.  I 
> always get 2N3904/6 for "high speed" duty (under 20MHz, but I seem to be 
> pushing up the clock rate every month ;) ), and 4401/3 for driver / output 
> / switching purposes.  Anything more is special order, e.g. ZTX651 or 
> PBSS4540 for those times when you need a big gulp of current.
> 
> Tim
> 
Yes, they were duds, no amount of miller, base compensation was fixing 
it. one from a different lot proved that.

   Actually, I think I may have saved the remainder, IIRC, every one I 
tested in the batch had the same effect. I had one from an old batch 
that verified the defects.

   These are the smt versions, not the 92 packages. MMBT2222 SOT-23.
I used an old 92 package version to verify defect though.

   One of the guys at work seems to think the 2222 falls into the same
Q.C. category as the 2N3055/TIP3055 where many times various
runs that didn't exactly match the intended spec got a 3055 stamp on it!

  :)

Bill Sloman wrote:

> On Dec 31 2011, 7:05 pm, Jamie
> <jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> 
>>Joerg wrote:
>>
>>>Oppie wrote:
>>
>>>>"Spehro Pefhany" <speffS...@interlogDOTyou.knowwhat> wrote in message
>>>>news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com...
>>
>>>>>I figured that out while I was still in high school- that app notes
>>>>>were generally not written by anyone resembling a practicing engineer.
>>>>>Mostly by being bitten by their example circuits.
>>
>>>>With a few notable exceptions like Jim Williams.
>>>>I really miss his crumby scope photos and clear writing style that not
>>>>only sold parts but helped us to understand WHY things worked. There are
>>>>many trade-offs in a design and understanding the basics puts a value on
>>>>those choices.
>>
>>>Yep. A good engineer quickly learns to first look at the author's name.
>>>If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one
>>>of the other gurus I know it's good stuff.
>>
>>  Oh boy, you know how to get brownie points. Was there something a
>>mystery you've been working on lately? I am sure one of those guys will
>>charm right in now :)
> 
> 
> Jim Williams, Bob Pease and Robert Widlar are dead, Bob Widlar for
> some years now.
> 
> Dan Banerjee still seems to be with us, but since he works for
> National Semiconductor, Joerg probably doesn't authorise enough parts
> per year to qualify for his interest.
> 
> You seem to be even more out of touch with reality than Jim Thopmson,
> who does still seem to know about electronics gurus, presumably
> because he's yet to lose contact with the realities of electronics.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  Bill, you're in constant denial. You wish you had a tenth of 
inclination Jim has, even at is current age.

> --
> Bill Sloman, Nijmegen

Jamie

> Now, as for CMOS, it has the same sort of structures (now NPN and PNP
> structures are always lateral, and both N- and P-wells are required), but
> under normal operation, it's all nice and clean, signals stay within the
> rails, no minority carriers to splash around, wells can be as shallow as
> you want.  But if you need a robust process, you still need all those
> space-hogging features that bipolar requires by default.  On the upside,
> it's great for LSI/VLSI, because you can reasonably assume all your low
> level internal circuitry isn't going to be bothered by any of the nasty
> outside world.  The result, of course, is a sizable fraction of die area
> committed to pin structures (input protection diodes and isolation, output
> transistors and latchup protection), while a microscopic blob of logic
> provides the functionality.
>
> Tim
>

CMOS doesn't have to be twin tub.

Most companies want latch-up trigger current to be above 100ma. 
Certainly about 40ma. So you really need to abuse the chip to get it to 
latch. Often current limiting resistors will do the job.

On Sat, 31 Dec 2011 20:31:10 -0500, Jamie
<jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote:

>Bill Sloman wrote:
>
>> On Dec 31 2011, 7:05 pm, Jamie
>> <jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
>> 
>>>Joerg wrote:
>>>
>>>>Oppie wrote:
>>>
>>>>>"Spehro Pefhany" <speffS...@interlogDOTyou.knowwhat> wrote in message
>>>>>news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com...
>>>
>>>>>>I figured that out while I was still in high school- that app notes
>>>>>>were generally not written by anyone resembling a practicing engineer.
>>>>>>Mostly by being bitten by their example circuits.
>>>
>>>>>With a few notable exceptions like Jim Williams.
>>>>>I really miss his crumby scope photos and clear writing style that not
>>>>>only sold parts but helped us to understand WHY things worked. There are
>>>>>many trade-offs in a design and understanding the basics puts a value on
>>>>>those choices.
>>>
>>>>Yep. A good engineer quickly learns to first look at the author's name.
>>>>If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one
>>>>of the other gurus I know it's good stuff.
>>>
>>>  Oh boy, you know how to get brownie points. Was there something a
>>>mystery you've been working on lately? I am sure one of those guys will
>>>charm right in now :)
>> 
>> 
>> Jim Williams, Bob Pease and Robert Widlar are dead, Bob Widlar for
>> some years now.
>> 
>> Dan Banerjee still seems to be with us, but since he works for
>> National Semiconductor, Joerg probably doesn't authorise enough parts
>> per year to qualify for his interest.
>> 
>> You seem to be even more out of touch with reality than Jim Thopmson,
>> who does still seem to know about electronics gurus, presumably
>> because he's yet to lose contact with the realities of electronics.
>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>  Bill, you're in constant denial. You wish you had a tenth of 
>inclination Jim has, even at is current age.
>
>> --
>> Bill Sloman, Nijmegen
>
>Jamie
>

Now, now!  I'm about to celebrate only my 18th birthday in 2012 ;-)
		
                                        ...Jim Thompson
-- 
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

On Jan 1, 2:31=A0am, Jamie
<jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> BillSlomanwrote:
> > On Dec 31 2011, 7:05 pm, Jamie
> > <jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
>
> >>Joerg wrote:
>
> >>>Oppie wrote:
>
> >>>>"Spehro Pefhany" <speffS...@interlogDOTyou.knowwhat> wrote in message
> >>>>news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com...
>
> >>>>>I figured that out while I was still in high school- that app notes
> >>>>>were generally not written by anyone resembling a practicing enginee=
r.
> >>>>>Mostly by being bitten by their example circuits.
>
> >>>>With a few notable exceptions like Jim Williams.
> >>>>I really miss his crumby scope photos and clear writing style that no=
t
> >>>>only sold parts but helped us to understand WHY things worked. There =
are
> >>>>many trade-offs in a design and understanding the basics puts a value=
 on
> >>>>those choices.
>
> >>>Yep. A good engineer quickly learns to first look at the author's name=
.
> >>>If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or on=
e
> >>>of the other gurus I know it's good stuff.
>
> >> =A0Oh boy, you know how to get brownie points. Was there something a
> >>mystery you've been working on lately? I am sure one of those guys will
> >>charm right in now :)
>
> > Jim Williams, Bob Pease and Robert Widlar are dead, Bob Widlar for
> > some years now.
>
> > Dan Banerjee still seems to be with us, but since he works for
> > National Semiconductor, Joerg probably doesn't authorise enough parts
> > per year to qualify for his interest.
>
> > You seem to be even more out of touch with reality than Jim Thopmson,
> > who does still seem to know about electronics gurus, presumably
> > because he's yet to lose contact with the realities of electronics.
>
> =A0Bill, you're in constant denial.

Denial of what?

> You wish you had a tenth of inclination Jim has, even at is current age.

I certainly wish I had as many customers as he does - three projects a
year would make me a lot happier.

--
Bill Sloman, Nijmegen

Bill Sloman wrote:
> On Dec 31 2011, 7:05 pm, Jamie
> <jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
>> Joerg wrote:
>>> Oppie wrote:
>>>> "Spehro Pefhany" <speffS...@interlogDOTyou.knowwhat> wrote in message
>>>> news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com...
>>>>> I figured that out while I was still in high school- that app notes
>>>>> were generally not written by anyone resembling a practicing engineer.
>>>>> Mostly by being bitten by their example circuits.
>>>> With a few notable exceptions like Jim Williams.
>>>> I really miss his crumby scope photos and clear writing style that not
>>>> only sold parts but helped us to understand WHY things worked. There are
>>>> many trade-offs in a design and understanding the basics puts a value on
>>>> those choices.
>>> Yep. A good engineer quickly learns to first look at the author's name.
>>> If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one
>>> of the other gurus I know it's good stuff.
>>   Oh boy, you know how to get brownie points. Was there something a
>> mystery you've been working on lately? I am sure one of those guys will
>> charm right in now :)
> 
> Jim Williams, Bob Pease and Robert Widlar are dead, Bob Widlar for
> some years now.
> 
> Dan Banerjee still seems to be with us, but since he works for
> National Semiconductor, Joerg probably doesn't authorise enough parts
> per year to qualify for his interest.
> 

You and your premature conclusions :-)

Dean actually answered one of the more unorthodox inquiries I had in
person. National impressed the heck out of me when he did, that was good
customer service. Bob Pease did, too, by the way. The only company that
could rival that in my cases is Linear Technology, and back in the old
days Analog Devices.


> You seem to be even more out of touch with reality than Jim Thopmson,
> who does still seem to know about electronics gurus, presumably
> because he's yet to lose contact with the realities of electronics.
> 

So what kinds of products have you designed lately? Say, last year?

-- 
Regards, Joerg

http://www.analogconsultants.com/