Forums

capacitive loading an opamp

Started by John Larkin December 30, 2011

A few opamps are specifically spec's to drive any capacitive load,
like LM8261 for instance. And sometimes you'll see an opamp that is
loaded with a big cap to ground, in an appnote for example.

If an opamp has some internal compensation node, midway through,
that's the dominant pole, adding a cap on the output makes a second
pole in the loop, potentially unstable. A huge cap might be stable,
but its corner frequency (with the opamp open-loop output impedance)
would have to be absurdly low. ESR matters, too.

Lots of rail-rail opamps have common-emitter output stages, with a PNP
emitter on V+ and an NPN emitter on V-, with the collectors being the
output. Compensation is often C-B caps on both transistors (or
equivalent), so the output is basically a current source with a bunch
of Miller capacitance. In that case, and external load cap basically
parallels the Miller capacitance, reducing GBW but not adding phase
shift.

So there ought to be lots of cheap R-R opamps around that are happy
with capacitive loads. Right?

John


On Fri, 30 Dec 2011 16:24:11 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

> > >A few opamps are specifically spec's to drive any capacitive load, >like LM8261 for instance. And sometimes you'll see an opamp that is >loaded with a big cap to ground, in an appnote for example. > >If an opamp has some internal compensation node, midway through, >that's the dominant pole, adding a cap on the output makes a second >pole in the loop, potentially unstable. A huge cap might be stable, >but its corner frequency (with the opamp open-loop output impedance) >would have to be absurdly low. ESR matters, too. > >Lots of rail-rail opamps have common-emitter output stages, with a PNP >emitter on V+ and an NPN emitter on V-, with the collectors being the >output. Compensation is often C-B caps on both transistors (or >equivalent), so the output is basically a current source with a bunch >of Miller capacitance. In that case, and external load cap basically >parallels the Miller capacitance, reducing GBW but not adding phase >shift. > >So there ought to be lots of cheap R-R opamps around that are happy >with capacitive loads. Right? > >John >
My experience, right down there at the device level, is that capacitive loading of rail-to-rail OpAmps can still be a "thriller", particularly with large open-loop gains. The problem is that the "Miller", while helpful, is NOT the only internal pole of concern. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
John Larkin wrote:
> > A few opamps are specifically spec's to drive any capacitive load, > like LM8261 for instance. And sometimes you'll see an opamp that is > loaded with a big cap to ground, in an appnote for example. >
App notes are sometimes written by rookies. I learned that early on when I met a guy who got his degree at the same time as I did. We met by chance at some airport or train station, right after picking up our degrees. This guy had zero hobby experience, didn't even own a solder iron or anything in parts. "So what are you doing?" ... "Working at XYZ" ... "Oh, cool, but too big a company for me. What kind of projects?" ... "I am writing application notes". My jaw dropped.
> If an opamp has some internal compensation node, midway through, > that's the dominant pole, adding a cap on the output makes a second > pole in the loop, potentially unstable. A huge cap might be stable, > but its corner frequency (with the opamp open-loop output impedance) > would have to be absurdly low. ESR matters, too. > > Lots of rail-rail opamps have common-emitter output stages, with a PNP > emitter on V+ and an NPN emitter on V-, with the collectors being the > output. Compensation is often C-B caps on both transistors (or > equivalent), so the output is basically a current source with a bunch > of Miller capacitance. In that case, and external load cap basically > parallels the Miller capacitance, reducing GBW but not adding phase > shift. > > So there ought to be lots of cheap R-R opamps around that are happy > with capacitive loads. Right? >
It's not enough and the datasheets still have the same kind of warnings, and limit values. See section 4.3: http://ww1.microchip.com/downloads/en/DeviceDoc/21733j.pdf -- Regards, Joerg http://www.analogconsultants.com/
John Larkin wrote:

> > A few opamps are specifically spec's to drive any capacitive load, > like LM8261 for instance. And sometimes you'll see an opamp that is > loaded with a big cap to ground, in an appnote for example. > > If an opamp has some internal compensation node, midway through, > that's the dominant pole, adding a cap on the output makes a second > pole in the loop, potentially unstable. A huge cap might be stable, > but its corner frequency (with the opamp open-loop output impedance) > would have to be absurdly low. ESR matters, too. > > Lots of rail-rail opamps have common-emitter output stages, with a PNP > emitter on V+ and an NPN emitter on V-, with the collectors being the > output. Compensation is often C-B caps on both transistors (or > equivalent), so the output is basically a current source with a bunch > of Miller capacitance. In that case, and external load cap basically > parallels the Miller capacitance, reducing GBW but not adding phase > shift. > > So there ought to be lots of cheap R-R opamps around that are happy > with capacitive loads. Right? > > John > >
Actually, I like the common emitter types. If you look close at the circuit they usually have some opposite sex transistor hanging off the output collectors going back in the bias circuit. This makes it easy to quench the output if it does not agree with said bias set point. It can capture unexpected voltages being present at the output and clamp it to its desire set point. Plus they work much better for rail operations. The ones that use both NPN for both rails I find seem to have better specs for the output, not sure why that is? I do know PNP's are usually the first to go in anything power from my experience. Jamie
On Fri, 30 Dec 2011 17:15:21 -0800, the renowned Joerg
<invalid@invalid.invalid> wrote:

>John Larkin wrote: >> >> A few opamps are specifically spec's to drive any capacitive load, >> like LM8261 for instance. And sometimes you'll see an opamp that is >> loaded with a big cap to ground, in an appnote for example. >> > >App notes are sometimes written by rookies. I learned that early on when >I met a guy who got his degree at the same time as I did. We met by >chance at some airport or train station, right after picking up our >degrees. This guy had zero hobby experience, didn't even own a solder >iron or anything in parts. > >"So what are you doing?" ... "Working at XYZ" ... "Oh, cool, but too big >a company for me. What kind of projects?" ... "I am writing application >notes". > >My jaw dropped.
I figured that out while I was still in high school- that app notes were generally not written by anyone resembling a practicing engineer. Mostly by being bitten by their example circuits. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message 
news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com...
> > I figured that out while I was still in high school- that app notes > were generally not written by anyone resembling a practicing engineer. > Mostly by being bitten by their example circuits. >
With a few notable exceptions like Jim Williams. I really miss his crumby scope photos and clear writing style that not only sold parts but helped us to understand WHY things worked. There are many trade-offs in a design and understanding the basics puts a value on those choices. Oppie
"Jamie" <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote in 
message news:8nuLq.16$EO7.14@newsfe01.iad...
> The ones that use both NPN for both rails I find seem to have better > specs for the output, not sure why that is? I do know PNP's are usually > the first to go in anything power from my experience.
Minus the extra Vbe drop of course. Gist of it is, if you start with a doped substrate, then it's real easy to build all the same type transistors on it, and less easy to build the other type. Doing so requires either 1. alternate construction methods, or 2. an extra layer (masking, doping, diffusion, epitaxy, whatever). 1 is almost always preferred over 2, because 2 is very expensive (if you only need 4 masks or whatever, adding another basically increases your development cost by 25%). For NPNs, they start with a weakly doped P substrate. It's easy to over-dope this to turn it into a reasonably pure N region, without compromising leakage, breakdown voltage or resistivity very much. These become the collector junctions. Further doping pushes a spot in the collector back to P, making the base, and an even smaller, denser blob of doping pushes a spot in the base back to N, forming the emitter and completing the N-P-N transistor. Note that the substrate is P, so if you generate a substrate current, you forward bias the P-N-P-N parasitic thyristor. This is true of most fabrication processes (bipolar and CMOS), and careful design is required to degenerate this structure to provide reasonable freedom from latchup. Things like wells (extra deep diffusions), guard rings (extra junctions around transistors and wells), trench oxide (cuts into the semiconductor, plugged with glass) and other stuff come in handy here. If you want to make a PNP in the same method, you either have to settle for placing it on the substrate (substrate collectors probably aren't too handy, and pushing current into the substrate is similar to moving your toilet into your living room and flushing it), or making an additional well, inside the well you originally made, making a 5-layer transistor (P substrate, N well, PNP; just as the substrate gets connected to GND, the N-well gets connected to the highest voltage around, usually VCC). This is the expensive way, because you need another mask to dope the P emitter, and the performance is lower because you have excessive doping (the PNP collector is identical to the NPN's emitter, which might break down at 7V or so; needless to say, the PNP emitter will have even lower breakdown, just a few volts, similar to an RF transistor's E-B junction). So that said, what's usually done is, you basically take your regular N-P-N transistor, but make two bases, right next to each other. Now, the N well (that used to be the NPN collector) serves as the base. Now, the layers aren't nested like Russain dolls -- current flows sideways from emitter to collector (hence, "lateral PNP"), so the hFE is crap, but on the upside, the "collector" and "emitter" are both the same P-stuff the NPN uses for its base, in other words, it's symmetrical (Vcb = Veb) and has high breakdown (Veb = Vcb = 30V or so). This is handy for differential inputs, where you might put 30V across them in saturation. There are plenty of circuits that work nicely at low hFE. Current mirrors are the major use of PNP, just to supply a little bias current to the NPN stuff (diff amp loading, volt amps, bandgap references, etc.). hFE is low, so higher order mirrors are common (the kind with the "darlington"-esque boosted input end, Wilson mirrors, etc.), and low bias currents are common (you don't want to waste 1mA base current for every 2-3mA circuit you supply, but fortunately you don't need more than a few uA, since these are *tiny* transistors and they'll run fast, even at low currents). You'll never(??) see lateral PNPs as emitter followers or open collector outputs in ICs, since those would consume huge base currents, even if darlingtoned a stage or two. If hFE = 3, a triple darlington would only get you a total of 27 gain, while dropping over two Vbe's -- you'll get much better performance from a weak PNP pull-up (maybe 10uA) and an NPN follower (hFE = 200 gives Imax ~ 2mA), with a dropout of just over one Vbe, or an NPN darlington to increase the current to "who gives a crap" levels (>200mA, geometry limited by then). Now the dropout is two Vbe's, but the available current is huge, and the current efficiency is high (you're only wasting the 10uA pullup). Op-amps, the 555 timer, even the stepper motor driver L298 (2A output capacity) use this type of output stage. (TTL logic does not, because they didn't use lateral PNP; instead, a resistor provides the internal pull-up.) Now, if epitaxy is used, or ion implantation, one has essentially unlimited control over doping -- you aren't limited by trying to overdope an existing layer, so you could, for instance, put high voltage collectors on top of high gain base-emitter junctions, in either polarity. You're still limited on mask cost, so you'll want to optimize one type (almost always NPN), and you can always fall back on using the lateral technique in a pinch. Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms
Oppie wrote:
> "Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message > news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com... >> >> I figured that out while I was still in high school- that app notes >> were generally not written by anyone resembling a practicing engineer. >> Mostly by being bitten by their example circuits. >> > With a few notable exceptions like Jim Williams. > I really miss his crumby scope photos and clear writing style that not > only sold parts but helped us to understand WHY things worked. There are > many trade-offs in a design and understanding the basics puts a value on > those choices. >
Yep. A good engineer quickly learns to first look at the author's name. If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one of the other gurus I know it's good stuff. -- Regards, Joerg http://www.analogconsultants.com/
Tim Williams wrote:

> "Jamie" <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote in > message news:8nuLq.16$EO7.14@newsfe01.iad... > >> The ones that use both NPN for both rails I find seem to have better >>specs for the output, not sure why that is? I do know PNP's are usually >>the first to go in anything power from my experience. > > > Minus the extra Vbe drop of course. > > Gist of it is, if you start with a doped substrate, then it's real easy to > build all the same type transistors on it, and less easy to build the > other type. Doing so requires either 1. alternate construction methods, > or 2. an extra layer (masking, doping, diffusion, epitaxy, whatever). 1 > is almost always preferred over 2, because 2 is very expensive (if you > only need 4 masks or whatever, adding another basically increases your > development cost by 25%). > > For NPNs, they start with a weakly doped P substrate. It's easy to > over-dope this to turn it into a reasonably pure N region, without > compromising leakage, breakdown voltage or resistivity very much. These > become the collector junctions. Further doping pushes a spot in the > collector back to P, making the base, and an even smaller, denser blob of > doping pushes a spot in the base back to N, forming the emitter and > completing the N-P-N transistor. > > Note that the substrate is P, so if you generate a substrate current, you > forward bias the P-N-P-N parasitic thyristor. This is true of most > fabrication processes (bipolar and CMOS), and careful design is required > to degenerate this structure to provide reasonable freedom from latchup. > Things like wells (extra deep diffusions), guard rings (extra junctions > around transistors and wells), trench oxide (cuts into the semiconductor, > plugged with glass) and other stuff come in handy here. > > If you want to make a PNP in the same method, you either have to settle > for placing it on the substrate (substrate collectors probably aren't too > handy, and pushing current into the substrate is similar to moving your > toilet into your living room and flushing it), or making an additional > well, inside the well you originally made, making a 5-layer transistor (P > substrate, N well, PNP; just as the substrate gets connected to GND, the > N-well gets connected to the highest voltage around, usually VCC). This > is the expensive way, because you need another mask to dope the P emitter, > and the performance is lower because you have excessive doping (the PNP > collector is identical to the NPN's emitter, which might break down at 7V > or so; needless to say, the PNP emitter will have even lower breakdown, > just a few volts, similar to an RF transistor's E-B junction). > > So that said, what's usually done is, you basically take your regular > N-P-N transistor, but make two bases, right next to each other. Now, the > N well (that used to be the NPN collector) serves as the base. Now, the > layers aren't nested like Russain dolls -- current flows sideways from > emitter to collector (hence, "lateral PNP"), so the hFE is crap, but on > the upside, the "collector" and "emitter" are both the same P-stuff the > NPN uses for its base, in other words, it's symmetrical (Vcb = Veb) and > has high breakdown (Veb = Vcb = 30V or so). This is handy for > differential inputs, where you might put 30V across them in saturation. > > There are plenty of circuits that work nicely at low hFE. Current mirrors > are the major use of PNP, just to supply a little bias current to the NPN > stuff (diff amp loading, volt amps, bandgap references, etc.). hFE is > low, so higher order mirrors are common (the kind with the > "darlington"-esque boosted input end, Wilson mirrors, etc.), and low bias > currents are common (you don't want to waste 1mA base current for every > 2-3mA circuit you supply, but fortunately you don't need more than a few > uA, since these are *tiny* transistors and they'll run fast, even at low > currents). > > You'll never(??) see lateral PNPs as emitter followers or open collector > outputs in ICs, since those would consume huge base currents, even if > darlingtoned a stage or two. If hFE = 3, a triple darlington would only > get you a total of 27 gain, while dropping over two Vbe's -- you'll get > much better performance from a weak PNP pull-up (maybe 10uA) and an NPN > follower (hFE = 200 gives Imax ~ 2mA), with a dropout of just over one > Vbe, or an NPN darlington to increase the current to "who gives a crap" > levels (>200mA, geometry limited by then). Now the dropout is two Vbe's, > but the available current is huge, and the current efficiency is high > (you're only wasting the 10uA pullup). Op-amps, the 555 timer, even the > stepper motor driver L298 (2A output capacity) use this type of output > stage. (TTL logic does not, because they didn't use lateral PNP; instead, > a resistor provides the internal pull-up.) > > Now, if epitaxy is used, or ion implantation, one has essentially > unlimited control over doping -- you aren't limited by trying to overdope > an existing layer, so you could, for instance, put high voltage collectors > on top of high gain base-emitter junctions, in either polarity. You're > still limited on mask cost, so you'll want to optimize one type (almost > always NPN), and you can always fall back on using the lateral technique > in a pinch. > > Tim >
Tim, that was a very good break down. You may find this hard to believe but I actually understood that, being that I am a back hill Maine cow herder. It would explain the reason I see the use of PNP on some designs being frown on and needed in others due to their low hfe states. What i've found is that PNP's seem to have a high failure rate, mostly in the loss of hfe and some times open in the base. I think some where I read once it was a process issue that caused the problem with some PNP devices. As for the latch up, I thought that problem for the most part was relevant in CMOS only? Due to how the CMOS is done, a thyristor bipolar body is naturally formed as part of the CMOS design and there for will trigger if gate for example exceeds Vdd > .7. Maybe I got my ducks mixed up, but what ever. Years ago, we modified a design that used CMOS chips and one of them would go into a latch now and then and burn the chip before it was noticed, most of the time. The reason for this was external and hard to control. So we put in a thyristor circuit of our own that would trigger if this CMOS circuit did go into a latch and reverse bias, a current source that was supplying Vdd. There was also an LED placed on the panel for indication. It served to save the CMOS chip and show the event that took place. We later on did find out what was causing over input but left it that way because we used that as a control feature :) Remember, it is feature not a bug! Jamie
Joerg wrote:

> Oppie wrote: > >>"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message >>news:g3vsf7pfm1v2cbp1cmmp2lnd2jp4qugn1c@4ax.com... >> >>>I figured that out while I was still in high school- that app notes >>>were generally not written by anyone resembling a practicing engineer. >>>Mostly by being bitten by their example circuits. >>> >> >>With a few notable exceptions like Jim Williams. >>I really miss his crumby scope photos and clear writing style that not >>only sold parts but helped us to understand WHY things worked. There are >>many trade-offs in a design and understanding the basics puts a value on >>those choices. >> > > > Yep. A good engineer quickly learns to first look at the author's name. > If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one > of the other gurus I know it's good stuff. >
Oh boy, you know how to get brownie points. Was there something a mystery you've been working on lately? I am sure one of those guys will charm right in now :) Jamie