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LT Spice question

Started by John Larkin December 15, 2011
On Dec 16, 12:17=A0pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Thu, 15 Dec 2011 18:47:39 -0800 (PST), George Herold > > > > > > <gher...@teachspin.com> wrote: > >On Dec 15, 8:23=A0pm, Joerg <inva...@invalid.invalid> wrote: > >> Jim Thompson wrote: > >> > On Thu, 15 Dec 2011 19:19:21 -0500, Jamie > >> > <jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote: > > >> >> John Larkin wrote: > > >> >>> On Thu, 15 Dec 2011 13:33:06 -0800, Joerg <inva...@invalid.invalid= > > >> >>> wrote: > > >> >>>> John Larkin wrote: > > >> >>>> [SPICE netlist] > > >> >>>>> I'm trying to get the most linear ramp at OUT, from +1 to +3 vol=
ts in
> >> >>>>> 16 ns. AD8014 was probably a bad choice, and the best feedback > >> >>>>> resistor value is way below the 1K that ADI suggests for a follo=
wer.
> > >> >>>>> I had to use .lib instead of .include to make LT Spice happy. Th=
e
> >> >>>>> default pin order was ok. > > >> >>>>> If the opamp model is accurate (namely, it doesn't oscillate wit=
h the
> >> >>>>> 249 ohm resistor) it looks pretty good. My original circuit (R2=
=3D1K,
> >> >>>>> L1=3D56n) was terrible. I'll try it in real life next. > > >> >>>> Doesn't look bad at all. For snappier corners you have to pick an=
amp
> >> >>>> with a lot more bandwidth. Like this little dude: > > >> >>>>http://www.ti.com/lit/ds/symlink/ths4303.pdf > > >> >>> I need unity gain here. We have used the 4303 before, and it's ver=
y
> >> >>> nice, probably because the feedback resistors are internal. > > >> >>>> However, the AD8014 is a CFB and they really do not like this > >> >>>> configuration with just Rf and a cap from IN- to ground. Might pu=
t them
> >> >>>> close to oscillation even if SPICE says they are ok. > > >> >>> That cap just sims PCB parasitics. Things don't change much from 0=
to
> >> >>> 2 pF, and I doubt I even have 1 pF there. > > >> >>> The bad news is that there's some ringing at the early part of the > >> >>> ramp in real life, > > >> >>>ftp://jjlarkin.lmi.net/AD8014_ramp.JPG > > >> >>> not on the sim, which I ascribe to a rotten Spice model of the opa=
mp.
> >> >>> I can set Rf to zero ohms, and it still simulates nicely, which > >> >>> doesn't sound right to me. These current-mode amps usually go > >> >>> bezerkers with zero ohms of Rf. > > >> >>> I guess I'll defy the sim and change Rf some, or try another amp, =
an
> >> >>> AD8009 maybe. > > >> >>> John > > >> >> If I didn't know any better, that looks like it maybe a standing wa=
ve
> >> >> you're seeing. Have you tried a R load on the output instead of a C=
ap?
> > >> >> Jamie > > >> > Good point, the device probably needs some DC load. =A0And it seems > >> > rather squirrely at G=3D1, but nice at G=3D2. > > >> CFBs are usually ok at G=3D-1 > > >OK maybe just invert it then? =A0Or is there a power supply issue. > > Here's the circuit: > > ftp://jjlarkin.lmi.net/Ramp.JPG > > Inversion won't work - I need a high impedance load on the ramp > capacitor - and a gain of 1 makes the bootstrap current source simple > and accurate. > > It works, but I'm getting linearity errors equivalent to about 180 ps > out of a 16 ns ramp, around 1%. That's not bad for a 16 nanosecond > ramp, but the customer (unreasonably) wants better. Don't know why, > there's only a few billion dollars per year affected by this error. > > I've done 0.1% for a 40 ns ramp before, using a real current source, > so this shouldn't be all that difficult. The AD8014, while cheap and > low power, wasn't the best choice, and it sure looks like the Spice > model isn't very accurate. > > The ramp at the capacitor, seen with a fet probe, looks perfect. > > Sigh, I suppose I'll have to get in there and start soldering. I am > waiting for some software to get done that gives me better analytics > on the linearity. > > John- Hide quoted text - > > - Show quoted text -
Well this is most likey silly, but could you add a bit of gain and split off a bit a current at the top? Maybe a gain of two so you can use the same RC? how much current does the opam draw? George H.
On Fri, 16 Dec 2011 18:36:27 -0500, Jamie
<jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote:

>John Larkin wrote: > >> On Thu, 15 Dec 2011 19:19:21 -0500, Jamie >> <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote: >> >> >>>John Larkin wrote: >>> >>> >>>>On Thu, 15 Dec 2011 13:33:06 -0800, Joerg <invalid@invalid.invalid> >>>>wrote: >>>> >>>> >>>> >>>>>John Larkin wrote: >>>>> >>>>>[SPICE netlist] >>>>> >>>>> >>>>> >>>>>>I'm trying to get the most linear ramp at OUT, from +1 to +3 volts in >>>>>>16 ns. AD8014 was probably a bad choice, and the best feedback >>>>>>resistor value is way below the 1K that ADI suggests for a follower. >>>>>> >>>>>>I had to use .lib instead of .include to make LT Spice happy. The >>>>>>default pin order was ok. >>>>>> >>>>>>If the opamp model is accurate (namely, it doesn't oscillate with the >>>>>>249 ohm resistor) it looks pretty good. My original circuit (R2=1K, >>>>>>L1=56n) was terrible. I'll try it in real life next. >>>>>> >>>>> >>>>>Doesn't look bad at all. For snappier corners you have to pick an amp >>>>>with a lot more bandwidth. Like this little dude: >>>>> >>>>>http://www.ti.com/lit/ds/symlink/ths4303.pdf >>>> >>>> >>>>I need unity gain here. We have used the 4303 before, and it's very >>>>nice, probably because the feedback resistors are internal. >>>> >>>> >>>> >>>>>However, the AD8014 is a CFB and they really do not like this >>>>>configuration with just Rf and a cap from IN- to ground. Might put them >>>>>close to oscillation even if SPICE says they are ok. >>>> >>>> >>>>That cap just sims PCB parasitics. Things don't change much from 0 to >>>>2 pF, and I doubt I even have 1 pF there. >>>> >>>>The bad news is that there's some ringing at the early part of the >>>>ramp in real life, >>>> >>>>ftp://jjlarkin.lmi.net/AD8014_ramp.JPG >>>> >>>>not on the sim, which I ascribe to a rotten Spice model of the opamp. >>>>I can set Rf to zero ohms, and it still simulates nicely, which >>>>doesn't sound right to me. These current-mode amps usually go >>>>bezerkers with zero ohms of Rf. >>>> >>>>I guess I'll defy the sim and change Rf some, or try another amp, an >>>>AD8009 maybe. >>>> >>>>John >>>> >>>> >>> >>>If I didn't know any better, that looks like it maybe a standing wave >>>you're seeing. Have you tried a R load on the output instead of a Cap? >>> >>>Jamie >>> >> >> >> That's the load I have to drive! >> >> John >> >Yes, ok but still, have you tried a load R directly on the CA output ? > >Jamie
The bootstrap pullup resistor is a load, and it pushes one of the output transistors into steady-state conduction. John
On Fri, 16 Dec 2011 19:35:34 -0800 (PST), George Herold
<gherold@teachspin.com> wrote:

>On Dec 16, 12:17&#2013266080;pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Thu, 15 Dec 2011 18:47:39 -0800 (PST), George Herold >> >> >> >> >> >> <gher...@teachspin.com> wrote: >> >On Dec 15, 8:23&#2013266080;pm, Joerg <inva...@invalid.invalid> wrote: >> >> Jim Thompson wrote: >> >> > On Thu, 15 Dec 2011 19:19:21 -0500, Jamie >> >> > <jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote: >> >> >> >> John Larkin wrote: >> >> >> >>> On Thu, 15 Dec 2011 13:33:06 -0800, Joerg <inva...@invalid.invalid> >> >> >>> wrote: >> >> >> >>>> John Larkin wrote: >> >> >> >>>> [SPICE netlist] >> >> >> >>>>> I'm trying to get the most linear ramp at OUT, from +1 to +3 volts in >> >> >>>>> 16 ns. AD8014 was probably a bad choice, and the best feedback >> >> >>>>> resistor value is way below the 1K that ADI suggests for a follower. >> >> >> >>>>> I had to use .lib instead of .include to make LT Spice happy. The >> >> >>>>> default pin order was ok. >> >> >> >>>>> If the opamp model is accurate (namely, it doesn't oscillate with the >> >> >>>>> 249 ohm resistor) it looks pretty good. My original circuit (R2=1K, >> >> >>>>> L1=56n) was terrible. I'll try it in real life next. >> >> >> >>>> Doesn't look bad at all. For snappier corners you have to pick an amp >> >> >>>> with a lot more bandwidth. Like this little dude: >> >> >> >>>>http://www.ti.com/lit/ds/symlink/ths4303.pdf >> >> >> >>> I need unity gain here. We have used the 4303 before, and it's very >> >> >>> nice, probably because the feedback resistors are internal. >> >> >> >>>> However, the AD8014 is a CFB and they really do not like this >> >> >>>> configuration with just Rf and a cap from IN- to ground. Might put them >> >> >>>> close to oscillation even if SPICE says they are ok. >> >> >> >>> That cap just sims PCB parasitics. Things don't change much from 0 to >> >> >>> 2 pF, and I doubt I even have 1 pF there. >> >> >> >>> The bad news is that there's some ringing at the early part of the >> >> >>> ramp in real life, >> >> >> >>>ftp://jjlarkin.lmi.net/AD8014_ramp.JPG >> >> >> >>> not on the sim, which I ascribe to a rotten Spice model of the opamp. >> >> >>> I can set Rf to zero ohms, and it still simulates nicely, which >> >> >>> doesn't sound right to me. These current-mode amps usually go >> >> >>> bezerkers with zero ohms of Rf. >> >> >> >>> I guess I'll defy the sim and change Rf some, or try another amp, an >> >> >>> AD8009 maybe. >> >> >> >>> John >> >> >> >> If I didn't know any better, that looks like it maybe a standing wave >> >> >> you're seeing. Have you tried a R load on the output instead of a Cap? >> >> >> >> Jamie >> >> >> > Good point, the device probably needs some DC load. &#2013266080;And it seems >> >> > rather squirrely at G=1, but nice at G=2. >> >> >> CFBs are usually ok at G=-1 >> >> >OK maybe just invert it then? &#2013266080;Or is there a power supply issue. >> >> Here's the circuit: >> >> ftp://jjlarkin.lmi.net/Ramp.JPG >> >> Inversion won't work - I need a high impedance load on the ramp >> capacitor - and a gain of 1 makes the bootstrap current source simple >> and accurate. >> >> It works, but I'm getting linearity errors equivalent to about 180 ps >> out of a 16 ns ramp, around 1%. That's not bad for a 16 nanosecond >> ramp, but the customer (unreasonably) wants better. Don't know why, >> there's only a few billion dollars per year affected by this error. >> >> I've done 0.1% for a 40 ns ramp before, using a real current source, >> so this shouldn't be all that difficult. The AD8014, while cheap and >> low power, wasn't the best choice, and it sure looks like the Spice >> model isn't very accurate. >> >> The ramp at the capacitor, seen with a fet probe, looks perfect. >> >> Sigh, I suppose I'll have to get in there and start soldering. I am >> waiting for some software to get done that gives me better analytics >> on the linearity. >> >> John- Hide quoted text - >> >> - Show quoted text - > >Well this is most likey silly, but could you add a bit of gain and >split off a bit a current at the top? Maybe a gain of two so you can >use the same RC? how much current does the opam draw? > >George H.
What you can do in the bootstrap ramp circuit is make the follower opamp gain a bit more than 1, which makes the ramp curve upwards. Or add a resistor across the cap, which makes it curve down a little. One or the other of those can partially correct for any small native curvature in the output. The biggest contribution to curvature (aside from crappy opamps) is usually nonlinear junction capacitances. Actually selecting the best curve-fixer resistor tends to be tedious. The AD8014 only uses about 1.3 mA, which is maybe why it's so bad here. An AD8009-class part will yoink about 10x as much. John
John Larkin wrote:
> On Fri, 16 Dec 2011 16:53:26 -0700, Jim Thompson > <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >> On Thu, 15 Dec 2011 08:21:17 -0800, John Larkin >> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>> Hi, >>> >>> I have the AD8014 Spice model from Analog Devices, and I have LT >>> Spice. >>> >>> The model file AD8014.cir starts with... >>> >>> >>> AD8014 SPICE model >>> >>> * Node assignments >>> * non-inverting input >>> * | inverting input >>> * | | positive supply >>> * | | | negative supply >>> * | | | | output >>> * | | | | | >>> .SUBCKT AD8014 1 2 99 50 28 >>> >>> >>> So, how do I draw an LT Spice schematic, with the usual opamp symbol, >>> and plug this model into it? >>> >>> I'm having a small problem with my ramp circuit >>> >>> ftp://jjlarkin.lmi.net/Ramp.JPG >>> >>> and it would be more convenient, just now, to tweak it by simulating >>> instead of soldering. >>> >>> Yes, yes, I should know this, but I don't use Spice often enough to >>> remember all the mechanics. >>> >>> Speaking of which, we have more ideas and stuff to do than we have >>> time and energy. It would be great to have someone who could do Spice >>> setups and simulations and parts research and maybe a little >>> breadboarding for us occasionally, for pay of course. >>> >>> John >> The AD8014 Spice model is crap... pure behavioral. > > But it doesn't behave right! >
That's just the problem with behavioral models. Even some LT parts which are nearly all behavioral with some secret hooks don't. I found numerous discrepancies, some rather serious. Synchronizable switchers that didn't synchronize correctly, a comparator where I discovered a real bug in the silicon, things like that. That is not to diss LTSpice or the models, one just has to not expect too much. If you got the full model, warts and all, the simulation would take a very long time. On a start process of a switcher it can easily take a whole hour, the PC fans come on hard and the office temp inches up a degree or two. Not so great in the summer but right now that's ok. -- Regards, Joerg http://www.analogconsultants.com/
On Sat, 17 Dec 2011 10:26:28 -0800, Joerg <invalid@invalid.invalid> wrote:

>John Larkin wrote: >> On Fri, 16 Dec 2011 16:53:26 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>> On Thu, 15 Dec 2011 08:21:17 -0800, John Larkin >>> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>> >>>> Hi, >>>> >>>> I have the AD8014 Spice model from Analog Devices, and I have LT >>>> Spice. >>>> >>>> The model file AD8014.cir starts with... >>>> >>>> >>>> AD8014 SPICE model >>>> >>>> * Node assignments >>>> * non-inverting input >>>> * | inverting input >>>> * | | positive supply >>>> * | | | negative supply >>>> * | | | | output >>>> * | | | | | >>>> .SUBCKT AD8014 1 2 99 50 28 >>>> >>>> >>>> So, how do I draw an LT Spice schematic, with the usual opamp symbol, >>>> and plug this model into it? >>>> >>>> I'm having a small problem with my ramp circuit >>>> >>>> ftp://jjlarkin.lmi.net/Ramp.JPG >>>> >>>> and it would be more convenient, just now, to tweak it by simulating >>>> instead of soldering. >>>> >>>> Yes, yes, I should know this, but I don't use Spice often enough to >>>> remember all the mechanics. >>>> >>>> Speaking of which, we have more ideas and stuff to do than we have >>>> time and energy. It would be great to have someone who could do Spice >>>> setups and simulations and parts research and maybe a little >>>> breadboarding for us occasionally, for pay of course. >>>> >>>> John >>> The AD8014 Spice model is crap... pure behavioral. >> >> But it doesn't behave right! >> > >That's just the problem with behavioral models. Even some LT parts which >are nearly all behavioral with some secret hooks don't. I found numerous >discrepancies, some rather serious. Synchronizable switchers that didn't >synchronize correctly, a comparator where I discovered a real bug in the >silicon, things like that.
At the LT Spice seminar a few months ago, they warned about synchronous switchers. The netlists include warnings that the models don't allow synchronization. Yes, that's the problem I've found using Spice. Its utility is severely compromised by lousy models. I guess I was spoiled by good models. ;-)
>That is not to diss LTSpice or the models, one just has to not expect >too much.
Like correct operation? ;-)
>If you got the full model, warts and all, the simulation would take a >very long time. On a start process of a switcher it can easily take a >whole hour, the PC fans come on hard and the office temp inches up a >degree or two. Not so great in the summer but right now that's ok.
A whole hour? I remember overnight simulations. A cow-orker ran simulations that sucked down an entire mainframe for weeks (statistical runs). Better a long time than "phut". Right? ;-)
krw@att.bizzzzzzzzzzzz wrote:
> On Sat, 17 Dec 2011 10:26:28 -0800, Joerg <invalid@invalid.invalid> wrote: > >> John Larkin wrote: >>> On Fri, 16 Dec 2011 16:53:26 -0700, Jim Thompson >>> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> >>>> On Thu, 15 Dec 2011 08:21:17 -0800, John Larkin >>>> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>> Hi, >>>>> >>>>> I have the AD8014 Spice model from Analog Devices, and I have LT >>>>> Spice. >>>>> >>>>> The model file AD8014.cir starts with... >>>>> >>>>> >>>>> AD8014 SPICE model >>>>> >>>>> * Node assignments >>>>> * non-inverting input >>>>> * | inverting input >>>>> * | | positive supply >>>>> * | | | negative supply >>>>> * | | | | output >>>>> * | | | | | >>>>> .SUBCKT AD8014 1 2 99 50 28 >>>>> >>>>> >>>>> So, how do I draw an LT Spice schematic, with the usual opamp symbol, >>>>> and plug this model into it? >>>>> >>>>> I'm having a small problem with my ramp circuit >>>>> >>>>> ftp://jjlarkin.lmi.net/Ramp.JPG >>>>> >>>>> and it would be more convenient, just now, to tweak it by simulating >>>>> instead of soldering. >>>>> >>>>> Yes, yes, I should know this, but I don't use Spice often enough to >>>>> remember all the mechanics. >>>>> >>>>> Speaking of which, we have more ideas and stuff to do than we have >>>>> time and energy. It would be great to have someone who could do Spice >>>>> setups and simulations and parts research and maybe a little >>>>> breadboarding for us occasionally, for pay of course. >>>>> >>>>> John >>>> The AD8014 Spice model is crap... pure behavioral. >>> But it doesn't behave right! >>> >> That's just the problem with behavioral models. Even some LT parts which >> are nearly all behavioral with some secret hooks don't. I found numerous >> discrepancies, some rather serious. Synchronizable switchers that didn't >> synchronize correctly, a comparator where I discovered a real bug in the >> silicon, things like that. > > At the LT Spice seminar a few months ago, they warned about synchronous > switchers. The netlists include warnings that the models don't allow > synchronization. >
It would be kind of nice if their jig schematics contained a warning about that.
> Yes, that's the problem I've found using Spice. Its utility is severely > compromised by lousy models. I guess I was spoiled by good models. ;-) >
The ones in bikinis? :-)
>> That is not to diss LTSpice or the models, one just has to not expect >> too much. > > Like correct operation? ;-) >
It can be an issue. For example, a comparator had an undocumented flaw after power-up. I was the guy who found out, and only after layouts and prototype build :-( This was a classic case of a behavioral model not telling the whole story. Wouldn't have happened with a full model because it was a chip design bug. If they ad full models I'd have found out at sim time.
>> If you got the full model, warts and all, the simulation would take a >> very long time. On a start process of a switcher it can easily take a >> whole hour, the PC fans come on hard and the office temp inches up a >> degree or two. Not so great in the summer but right now that's ok. > > A whole hour? I remember overnight simulations. A cow-orker ran simulations > that sucked down an entire mainframe for weeks (statistical runs). Better a > long time than "phut". Right? ;-)
I remember those days. Had to run the computer overnight a lot. But now I try to break circuits into palatable chunks. -- Regards, Joerg http://www.analogconsultants.com/
On Sat, 17 Dec 2011 11:37:01 -0800, Joerg <invalid@invalid.invalid> wrote:

>krw@att.bizzzzzzzzzzzz wrote: >> On Sat, 17 Dec 2011 10:26:28 -0800, Joerg <invalid@invalid.invalid> wrote: >> >>> John Larkin wrote: >>>> On Fri, 16 Dec 2011 16:53:26 -0700, Jim Thompson >>>> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> >>>>> On Thu, 15 Dec 2011 08:21:17 -0800, John Larkin >>>>> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>> Hi, >>>>>> >>>>>> I have the AD8014 Spice model from Analog Devices, and I have LT >>>>>> Spice. >>>>>> >>>>>> The model file AD8014.cir starts with... >>>>>> >>>>>> >>>>>> AD8014 SPICE model >>>>>> >>>>>> * Node assignments >>>>>> * non-inverting input >>>>>> * | inverting input >>>>>> * | | positive supply >>>>>> * | | | negative supply >>>>>> * | | | | output >>>>>> * | | | | | >>>>>> .SUBCKT AD8014 1 2 99 50 28 >>>>>> >>>>>> >>>>>> So, how do I draw an LT Spice schematic, with the usual opamp symbol, >>>>>> and plug this model into it? >>>>>> >>>>>> I'm having a small problem with my ramp circuit >>>>>> >>>>>> ftp://jjlarkin.lmi.net/Ramp.JPG >>>>>> >>>>>> and it would be more convenient, just now, to tweak it by simulating >>>>>> instead of soldering. >>>>>> >>>>>> Yes, yes, I should know this, but I don't use Spice often enough to >>>>>> remember all the mechanics. >>>>>> >>>>>> Speaking of which, we have more ideas and stuff to do than we have >>>>>> time and energy. It would be great to have someone who could do Spice >>>>>> setups and simulations and parts research and maybe a little >>>>>> breadboarding for us occasionally, for pay of course. >>>>>> >>>>>> John >>>>> The AD8014 Spice model is crap... pure behavioral. >>>> But it doesn't behave right! >>>> >>> That's just the problem with behavioral models. Even some LT parts which >>> are nearly all behavioral with some secret hooks don't. I found numerous >>> discrepancies, some rather serious. Synchronizable switchers that didn't >>> synchronize correctly, a comparator where I discovered a real bug in the >>> silicon, things like that. >> >> At the LT Spice seminar a few months ago, they warned about synchronous >> switchers. The netlists include warnings that the models don't allow >> synchronization. >> > >It would be kind of nice if their jig schematics contained a warning >about that.
You don't read the Surgeon General's warning on all the models you use? ;-)
>> Yes, that's the problem I've found using Spice. Its utility is severely >> compromised by lousy models. I guess I was spoiled by good models. ;-) >> > >The ones in bikinis? :-)
Nah, they've been bad for my health for >40 years.
>>> That is not to diss LTSpice or the models, one just has to not expect >>> too much. >> >> Like correct operation? ;-) >> > >It can be an issue. For example, a comparator had an undocumented flaw >after power-up. I was the guy who found out, and only after layouts and >prototype build :-(
Someone has to find those sorts of problems. It's one reason I don't like to do my own verification. Bad assumptions often get passed from design right through to the customer.
>This was a classic case of a behavioral model not telling the whole >story. Wouldn't have happened with a full model because it was a chip >design bug. If they ad full models I'd have found out at sim time.
"But the computer said..."
>>> If you got the full model, warts and all, the simulation would take a >>> very long time. On a start process of a switcher it can easily take a >>> whole hour, the PC fans come on hard and the office temp inches up a >>> degree or two. Not so great in the summer but right now that's ok. >> >> A whole hour? I remember overnight simulations. A cow-orker ran simulations >> that sucked down an entire mainframe for weeks (statistical runs). Better a >> long time than "phut". Right? ;-) > > >I remember those days. Had to run the computer overnight a lot. But now >I try to break circuits into palatable chunks.
Well, those *were* the palatable chunks.
On Fri, 16 Dec 2011 09:17:50 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Thu, 15 Dec 2011 18:47:39 -0800 (PST), George Herold ><gherold@teachspin.com> wrote: > >>On Dec 15, 8:23=A0pm, Joerg <inva...@invalid.invalid> wrote: >>> Jim Thompson wrote:
<snip>
>>> >>> CFBs are usually ok at G=3D-1 >> >>OK maybe just invert it then? Or is there a power supply issue. > > >Here's the circuit: > >ftp://jjlarkin.lmi.net/Ramp.JPG > >Inversion won't work - I need a high impedance load on the ramp >capacitor - and a gain of 1 makes the bootstrap current source simple >and accurate. > >It works, but I'm getting linearity errors equivalent to about 180 ps >out of a 16 ns ramp, around 1%. That's not bad for a 16 nanosecond >ramp, but the customer (unreasonably) wants better. Don't know why, >there's only a few billion dollars per year affected by this error. > >I've done 0.1% for a 40 ns ramp before, using a real current source, >so this shouldn't be all that difficult. The AD8014, while cheap and >low power, wasn't the best choice, and it sure looks like the Spice >model isn't very accurate. > >The ramp at the capacitor, seen with a fet probe, looks perfect. > >Sigh, I suppose I'll have to get in there and start soldering. I am >waiting for some software to get done that gives me better analytics >on the linearity. > >John >
I played with your circuit a bit and i am not getting as fast a ramp, but i am a little closer to the described / shown physical circuit. Version 4 SHEET 1 916 680 WIRE 656 -304 608 -304 WIRE 704 -304 656 -304 WIRE 608 -256 608 -304 WIRE 560 -240 -272 -240 WIRE 192 -224 96 -224 WIRE 96 -208 96 -224 WIRE 192 -192 192 -224 WIRE 608 -128 608 -176 WIRE 96 -112 96 -128 WIRE 192 -112 96 -112 WIRE 304 -112 272 -112 WIRE 304 -96 304 -112 WIRE 416 -96 304 -96 WIRE 304 -80 304 -96 WIRE 304 -80 176 -80 WIRE -272 -64 -272 -240 WIRE -224 -64 -272 -64 WIRE 176 -64 176 -80 WIRE 176 -64 -144 -64 WIRE 176 -48 176 -64 WIRE 208 -48 176 -48 WIRE 336 -48 272 -48 WIRE 336 -32 336 -48 WIRE 416 -32 336 -32 WIRE 560 -16 560 -192 WIRE -128 16 -192 16 WIRE 16 16 -48 16 WIRE 144 16 16 16 WIRE 272 16 224 16 WIRE 336 16 336 -32 WIRE 336 16 272 16 WIRE -192 48 -192 16 WIRE 96 64 96 -112 WIRE 16 80 16 16 WIRE 64 80 16 80 WIRE 272 96 272 16 WIRE 272 96 128 96 WIRE 336 96 272 96 WIRE 448 96 416 96 WIRE 560 96 560 -16 WIRE 560 96 528 96 WIRE -352 112 -416 112 WIRE -272 112 -272 -64 WIRE -272 112 -352 112 WIRE 64 112 -272 112 WIRE 560 112 560 96 WIRE 704 112 560 112 WIRE 560 128 560 112 WIRE 704 128 704 112 WIRE -272 144 -272 112 WIRE 560 208 560 192 WIRE 704 208 560 208 WIRE 560 224 560 208 WIRE -272 240 -272 208 WIRE 96 240 96 128 WIRE 96 368 96 320 =46LAG -272 240 0 =46LAG 560 224 0 =46LAG 192 -192 0 =46LAG 96 368 0 =46LAG -192 48 0 =46LAG 608 -128 0 =46LAG 656 -304 ERROR =46LAG -352 112 RAMP =46LAG 272 16 AMP =46LAG 560 -16 OUT SYMBOL cap -288 144 R0 WINDOW 0 71 15 Left 0 WINDOW 3 64 50 Left 0 SYMATTR InstName C1 SYMATTR Value 47p SYMBOL cap 544 128 R0 WINDOW 0 71 11 Left 0 WINDOW 3 65 47 Left 0 SYMATTR InstName C2 SYMATTR Value 47p SYMBOL ind 432 112 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 1n SYMBOL res 432 80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL Opamps\\opamp2 96 32 R0 WINDOW 0 45 101 Left 0 WINDOW 3 30 139 Left 0 SYMATTR InstName U1 SYMATTR Value AD8014 SYMBOL voltage 96 -112 R180 WINDOW 0 53 71 Left 0 WINDOW 3 61 36 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 5 SYMBOL voltage 96 336 R180 WINDOW 0 69 70 Left 0 WINDOW 3 75 33 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL res 240 0 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 249 SYMBOL e 608 -272 R0 WINDOW 0 66 42 Left 0 WINDOW 3 64 76 Left 0 SYMATTR InstName E1 SYMATTR Value 10 SYMBOL res -32 0 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 500g SYMBOL res 288 -128 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 330 SYMBOL res -128 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R6 SYMATTR Value 330 SYMBOL res 688 112 R0 SYMATTR InstName R7 SYMATTR Value 100g SYMBOL zener 272 -64 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName D1 SYMATTR Value 1N750 SYMATTR Description Diode SYMATTR Type diode SYMBOL cap 400 -96 R0 SYMATTR InstName C3 SYMATTR Value 100p TEXT -184 -176 Left 0 !.tran 0 30n 0 TEXT -200 -120 Left 0 !.lib AD8014.CIR TEXT -464 144 Left 0 !.ic v(RAMP)=3D0 ?-)
On Sat, 17 Dec 2011 15:43:53 -0800, josephkk
<joseph_barrett@sbcglobal.net> wrote:

>On Fri, 16 Dec 2011 09:17:50 -0800, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Thu, 15 Dec 2011 18:47:39 -0800 (PST), George Herold >><gherold@teachspin.com> wrote: >> >>>On Dec 15, 8:23&#2013266080;pm, Joerg <inva...@invalid.invalid> wrote: >>>> Jim Thompson wrote: ><snip> >>>> >>>> CFBs are usually ok at G=-1 >>> >>>OK maybe just invert it then? Or is there a power supply issue. >> >> >>Here's the circuit: >> >>ftp://jjlarkin.lmi.net/Ramp.JPG >> >>Inversion won't work - I need a high impedance load on the ramp >>capacitor - and a gain of 1 makes the bootstrap current source simple >>and accurate. >> >>It works, but I'm getting linearity errors equivalent to about 180 ps >>out of a 16 ns ramp, around 1%. That's not bad for a 16 nanosecond >>ramp, but the customer (unreasonably) wants better. Don't know why, >>there's only a few billion dollars per year affected by this error. >> >>I've done 0.1% for a 40 ns ramp before, using a real current source, >>so this shouldn't be all that difficult. The AD8014, while cheap and >>low power, wasn't the best choice, and it sure looks like the Spice >>model isn't very accurate. >> >>The ramp at the capacitor, seen with a fet probe, looks perfect. >> >>Sigh, I suppose I'll have to get in there and start soldering. I am >>waiting for some software to get done that gives me better analytics >>on the linearity. >> >>John >> > >I played with your circuit a bit and i am not getting as fast a ramp, but >i am a little closer to the described / shown physical circuit. > >Version 4 >SHEET 1 916 680 >WIRE 656 -304 608 -304 >WIRE 704 -304 656 -304 >WIRE 608 -256 608 -304 >WIRE 560 -240 -272 -240 >WIRE 192 -224 96 -224 >WIRE 96 -208 96 -224 >WIRE 192 -192 192 -224 >WIRE 608 -128 608 -176 >WIRE 96 -112 96 -128 >WIRE 192 -112 96 -112 >WIRE 304 -112 272 -112 >WIRE 304 -96 304 -112 >WIRE 416 -96 304 -96 >WIRE 304 -80 304 -96 >WIRE 304 -80 176 -80 >WIRE -272 -64 -272 -240 >WIRE -224 -64 -272 -64 >WIRE 176 -64 176 -80 >WIRE 176 -64 -144 -64 >WIRE 176 -48 176 -64 >WIRE 208 -48 176 -48 >WIRE 336 -48 272 -48 >WIRE 336 -32 336 -48 >WIRE 416 -32 336 -32 >WIRE 560 -16 560 -192 >WIRE -128 16 -192 16 >WIRE 16 16 -48 16 >WIRE 144 16 16 16 >WIRE 272 16 224 16 >WIRE 336 16 336 -32 >WIRE 336 16 272 16 >WIRE -192 48 -192 16 >WIRE 96 64 96 -112 >WIRE 16 80 16 16 >WIRE 64 80 16 80 >WIRE 272 96 272 16 >WIRE 272 96 128 96 >WIRE 336 96 272 96 >WIRE 448 96 416 96 >WIRE 560 96 560 -16 >WIRE 560 96 528 96 >WIRE -352 112 -416 112 >WIRE -272 112 -272 -64 >WIRE -272 112 -352 112 >WIRE 64 112 -272 112 >WIRE 560 112 560 96 >WIRE 704 112 560 112 >WIRE 560 128 560 112 >WIRE 704 128 704 112 >WIRE -272 144 -272 112 >WIRE 560 208 560 192 >WIRE 704 208 560 208 >WIRE 560 224 560 208 >WIRE -272 240 -272 208 >WIRE 96 240 96 128 >WIRE 96 368 96 320 >FLAG -272 240 0 >FLAG 560 224 0 >FLAG 192 -192 0 >FLAG 96 368 0 >FLAG -192 48 0 >FLAG 608 -128 0 >FLAG 656 -304 ERROR >FLAG -352 112 RAMP >FLAG 272 16 AMP >FLAG 560 -16 OUT >SYMBOL cap -288 144 R0 >WINDOW 0 71 15 Left 0 >WINDOW 3 64 50 Left 0 >SYMATTR InstName C1 >SYMATTR Value 47p >SYMBOL cap 544 128 R0 >WINDOW 0 71 11 Left 0 >WINDOW 3 65 47 Left 0 >SYMATTR InstName C2 >SYMATTR Value 47p >SYMBOL ind 432 112 R270 >WINDOW 0 32 56 VTop 0 >WINDOW 3 5 56 VBottom 0 >SYMATTR InstName L1 >SYMATTR Value 1n >SYMBOL res 432 80 R90 >WINDOW 0 0 56 VBottom 0 >WINDOW 3 32 56 VTop 0 >SYMATTR InstName R1 >SYMATTR Value 50 >SYMBOL Opamps\\opamp2 96 32 R0 >WINDOW 0 45 101 Left 0 >WINDOW 3 30 139 Left 0 >SYMATTR InstName U1 >SYMATTR Value AD8014 >SYMBOL voltage 96 -112 R180 >WINDOW 0 53 71 Left 0 >WINDOW 3 61 36 Left 0 >WINDOW 123 0 0 Left 0 >WINDOW 39 0 0 Left 0 >SYMATTR InstName V1 >SYMATTR Value 5 >SYMBOL voltage 96 336 R180 >WINDOW 0 69 70 Left 0 >WINDOW 3 75 33 Left 0 >WINDOW 123 0 0 Left 0 >WINDOW 39 0 0 Left 0 >SYMATTR InstName V2 >SYMATTR Value 5 >SYMBOL res 240 0 R90 >WINDOW 0 0 56 VBottom 0 >WINDOW 3 32 56 VTop 0 >SYMATTR InstName R2 >SYMATTR Value 249 >SYMBOL e 608 -272 R0 >WINDOW 0 66 42 Left 0 >WINDOW 3 64 76 Left 0 >SYMATTR InstName E1 >SYMATTR Value 10 >SYMBOL res -32 0 R90 >WINDOW 0 0 56 VBottom 0 >WINDOW 3 32 56 VTop 0 >SYMATTR InstName R3 >SYMATTR Value 500g >SYMBOL res 288 -128 R90 >WINDOW 0 0 56 VBottom 0 >WINDOW 3 32 56 VTop 0 >SYMATTR InstName R4 >SYMATTR Value 330 >SYMBOL res -128 -80 R90 >WINDOW 0 0 56 VBottom 0 >WINDOW 3 32 56 VTop 0 >SYMATTR InstName R6 >SYMATTR Value 330 >SYMBOL res 688 112 R0 >SYMATTR InstName R7 >SYMATTR Value 100g >SYMBOL zener 272 -64 R90 >WINDOW 0 0 32 VBottom 0 >WINDOW 3 32 32 VTop 0 >SYMATTR InstName D1 >SYMATTR Value 1N750 >SYMATTR Description Diode >SYMATTR Type diode >SYMBOL cap 400 -96 R0 >SYMATTR InstName C3 >SYMATTR Value 100p >TEXT -184 -176 Left 0 !.tran 0 30n 0 >TEXT -200 -120 Left 0 !.lib AD8014.CIR >TEXT -464 144 Left 0 !.ic v(RAMP)=0 > >?-)
The zener is not in conduction. John
On Sat, 17 Dec 2011 16:14:05 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

> > >The zener is not in conduction. > >John
You are right. This one uses a lower voltage "zener". Version 4 SHEET 1 916 680 WIRE 560 -304 -272 -304 WIRE 656 -304 608 -304 WIRE 704 -304 656 -304 WIRE 192 -288 96 -288 WIRE 96 -256 96 -288 WIRE 192 -256 192 -288 WIRE 608 -256 608 -304 WIRE 560 -240 560 -304 WIRE 96 -224 96 -256 WIRE 96 -160 96 -176 WIRE 192 -160 96 -160 WIRE 304 -160 272 -160 WIRE 304 -144 304 -160 WIRE 416 -144 304 -144 WIRE 608 -128 608 -176 WIRE 304 -112 304 -144 WIRE 304 -112 176 -112 WIRE 416 -96 416 -144 WIRE -272 -64 -272 -304 WIRE -224 -64 -272 -64 WIRE 176 -64 176 -112 WIRE 176 -64 -144 -64 WIRE 416 -32 336 -32 WIRE 176 -16 176 -64 WIRE 224 -16 176 -16 WIRE 336 -16 336 -32 WIRE 336 -16 288 -16 WIRE 560 -16 560 -192 WIRE -128 16 -192 16 WIRE 16 16 -48 16 WIRE 112 16 16 16 WIRE 336 16 336 -16 WIRE 336 16 192 16 WIRE 400 16 336 16 WIRE 416 16 400 16 WIRE -192 48 -192 16 WIRE 96 64 96 -160 WIRE 16 80 16 16 WIRE 64 80 16 80 WIRE 336 96 128 96 WIRE 416 96 416 16 WIRE 448 96 416 96 WIRE 560 96 560 -16 WIRE 560 96 528 96 WIRE -352 112 -416 112 WIRE -272 112 -272 -64 WIRE -272 112 -352 112 WIRE 64 112 -272 112 WIRE 560 112 560 96 WIRE 704 112 560 112 WIRE 560 128 560 112 WIRE 704 128 704 112 WIRE -272 144 -272 112 WIRE 560 208 560 192 WIRE 704 208 560 208 WIRE 560 224 560 208 WIRE -272 240 -272 208 WIRE 96 240 96 128 WIRE 96 368 96 320 =46LAG -272 240 0 =46LAG 560 224 0 =46LAG 192 -256 0 =46LAG 96 368 0 =46LAG -192 48 0 =46LAG 608 -128 0 =46LAG 656 -304 ERROR =46LAG -352 112 RAMP =46LAG 400 16 AMP =46LAG 560 -16 OUT SYMBOL cap -288 144 R0 WINDOW 0 71 15 Left 0 WINDOW 3 64 50 Left 0 SYMATTR InstName C1 SYMATTR Value 47p SYMBOL cap 544 128 R0 WINDOW 0 71 11 Left 0 WINDOW 3 65 47 Left 0 SYMATTR InstName C2 SYMATTR Value 47p SYMBOL ind 432 112 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 1n SYMBOL res 432 80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL Opamps\\opamp2 96 32 R0 WINDOW 0 45 101 Left 0 WINDOW 3 30 139 Left 0 SYMATTR InstName U1 SYMATTR Value AD8014 SYMBOL voltage 96 -160 R180 WINDOW 0 53 71 Left 0 WINDOW 3 61 36 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 5 SYMBOL voltage 96 336 R180 WINDOW 0 69 70 Left 0 WINDOW 3 75 33 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL res 208 0 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 249 SYMBOL e 608 -272 R0 WINDOW 0 66 42 Left 0 WINDOW 3 64 76 Left 0 SYMATTR InstName E1 SYMATTR Value 10 SYMBOL res -32 0 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 500g SYMBOL res 288 -176 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 249 SYMBOL res -128 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R6 SYMATTR Value 500 SYMBOL res 688 112 R0 SYMATTR InstName R7 SYMATTR Value 100g SYMBOL cap 400 -96 R0 SYMATTR InstName C3 SYMATTR Value 470p SYMBOL References\\LT1009 256 -16 R270 WINDOW 3 5 46 Left 0 SYMATTR InstName U2 TEXT -184 -176 Left 0 !.tran 0 30n 0 TEXT -200 -120 Left 0 !.lib AD8014.CIR TEXT -464 144 Left 0 !.ic v(RAMP)=3D0 ?-)