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Unconnected part LTSpice seems to need (weird ...)

Started by Joerg August 14, 2011
On Fri, 19 Aug 2011 08:03:25 -0700, Joerg <invalid@invalid.invalid> =
wrote:

>josephkk wrote: >> On Mon, 15 Aug 2011 07:29:01 -0700, Joerg <invalid@invalid.invalid> =
wrote:
>>=20 >>> nuny@bid.nes wrote: >>>> On Aug 14, 3:33 pm, Joerg <inva...@invalid.invalid> wrote: >>>>> Folks, >>>>> >>>>> This is close to voodoo but repeatable. Unfortunately I can't =
disclose
>>>>> the schematic since it is for a client. Just wondering , anyone had=
this
>>>>> before? >>>>> >>>>> At the far end of a TX line I used to have a diode connected across >>>>> because a previous version of a chip would have such a substrat =
path.
>>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now =
the
>>>>> new iteration of the chip design won't have this diode path so I =
chopped
>>>>> off its cathode connection. Sims fine. So I deleted the diode -> >>>>> ka-crunch ... sim slows down and the ouput is junk. >>>>> >>>>> If I put the diode back in and connect only its anode -> fine. If I >>>>> leave the anode open and only connect the cathode it still sims but=
the
>>>>> results are different. >>>>> >>>>> <scratching head> >>>> I really hate to ask this, but have you "simulated" your LTSpice >>>> results in hardware yet? >>>> >>> No, can't do that yet. It's an IC and that is not taped out yet. >>> >> Is someone of crazy here (very possibly me, i have not done an actual =
IC
>> design)? How can you dare try tapeout before having a believable >> simulation? Can't you get adequate device models without tapeout? ... > > >The IC is completely simulated out on the big Mentor simulator, not >LTSpice It's about the system interface, not the IC. > > >> ... Do >> they even know which fab and process they are going to use? > > >Oh yes, they do and I do :-) > >When you do an IC of this complexity you tailor it to a specific process >right from the beginning. > >[...]
Thanks, i am glad that neither of us is all that crazy. I guess i only scared myself. ?-/
Charlie E. expounded in
news:3epq47d5rekuofkfafh0qseeodajeuc4od@4ax.com: 

> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg > <invalid@invalid.invalid> wrote:
>>I find this sim behavior odd. It seems only naturaly that, >>in a "what-if" scenario, an engineer disconnects just one >>leg of a part. After all, that's how we also do it in real >>life. SPICE is not supposed to "partially smoosh that" and >>then not tell anyone. > > Hi Joerg, > Yes, it looks like you have hit another of those > 'interesting assumptions' that always come up and bite us > on the posterior. > > Spice has to have everything connected Somewhere, and have > a path to ground from that connection. ... I am afraid it is > just a part of learning the capabilities of the tools... > 8-) > > Charlie
I have seen LTspice compain about a missing ground. But in other circuits the problem remained unreported. So this is likey a software correctness issue. Warren