On Sun, 14 Aug 2011 16:06:33 -0700, Joerg wrote:> Ok, it's attached, I cut our the proprietary swaths. The results are > very different but the basic effect is still there: > > Note that D2 is connected at the anode only. Run the sim, look at > V(n001), three nice clean pulses. Now delete the anode connection and > the diode D2 -> first pulse is hosed.Won't run as-is for me; I get "D2, missing diode nodes" A 1T resistor across the diode (useful kludge when Spice barfs at floating nodes and things), allows it to run. I get three clean pulses with either anode connected, cathode connected, or both. No diode screws up the first pulse. Interestingly, changing diode type to 1N4148 (higher Cjo, higher tt) modifies this behavior. Substituting an "O" lossy transmission line model for the "T" model regularizes things. No difference with either or both ends of the diode disconnected or no diode at all. First pulse mangled in all cases. Adding the fully-connected diode cleans things up. I guess we are seeing a peculiarity of how the "O" (ideal) model works, the "T" model appears to be more tractable. Try a lossy line model using: .model RG179 LTRA (len=4.0581 L=0.077u R=107.7m C=30.8p) (Constants are per foot from Belden data), which gives an approximate 6.25 nanosecond delay. It appears that the screwed up first pulse is down to source termination mismatch. You have effectively 51 ohms, 50 external and 1 ohm in V1. Take the 1 ohm out of the source, or make R1 49 ohms, and all the anomalies go away. -- "For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
Unconnected part LTSpice seems to need (weird ...)
Started by ●August 14, 2011
Reply by ●August 15, 20112011-08-15
Reply by ●August 15, 20112011-08-15
nuny@bid.nes wrote:> On 8/15/2011 7:29 AM, Joerg wrote: >> nuny@bid.nes wrote: >>> On Aug 14, 3:33 pm, Joerg<inva...@invalid.invalid> wrote: >>>> Folks, >>>> >>>> This is close to voodoo but repeatable. Unfortunately I can't disclose >>>> the schematic since it is for a client. Just wondering , anyone had >>>> this >>>> before? >>>> >>>> At the far end of a TX line I used to have a diode connected across >>>> because a previous version of a chip would have such a substrat path. >>>> Nice waveforms, fast sims. Everything as expected and peachy. Now the >>>> new iteration of the chip design won't have this diode path so I >>>> chopped >>>> off its cathode connection. Sims fine. So I deleted the diode -> >>>> ka-crunch ... sim slows down and the ouput is junk. >>>> >>>> If I put the diode back in and connect only its anode -> fine. If I >>>> leave the anode open and only connect the cathode it still sims but the >>>> results are different. >>>> >>>> <scratching head> >>> >>> I really hate to ask this, but have you "simulated" your LTSpice >>> results in hardware yet? >> >> No, can't do that yet. It's an IC and that is not taped out yet. > > Dang. Do you have an example of the old setup handy on which you can > try your diode changes as above? >No, this IC will be totally new turf. Reason for my sims is the we now have to take care of the design of the connecting electronics while it'll be in production. That way it'll all come together at roughly the same time.>>> Also, what's the RF voltage level on the line? >> >> About 100V, and then from microvolts up to a volt during receive >> depending on signal strength coming in. > > I thought it might be high. Think; what happens with a real diode > connected as described above in such a field? >In the end we'll have to live with whatever the IC has, there is practically no space for any other parts to the right of the TX line.> Anyway, if it were me I'd stop fiddling with the diode and just use a > terminating resistor. > > Of course, once the chip was ready I'd try it with the diode, just to > see. ;>) >I might. But we can't place diodes because it's multi-channel and that would be lots of parts in a space that isn't there :-) It's no problem because the signals going up can be shaped accordingly. I was just wondering why LTSpice is producing inconsistent results here. It's ok if it runs into a dead end with some calcs but I'd have thought that would caused the usual error messages. Yet I get none of those. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●August 15, 20112011-08-15
Fred Abse wrote:> On Sun, 14 Aug 2011 16:06:33 -0700, Joerg wrote: > >> Ok, it's attached, I cut our the proprietary swaths. The results are >> very different but the basic effect is still there: >> >> Note that D2 is connected at the anode only. Run the sim, look at >> V(n001), three nice clean pulses. Now delete the anode connection and >> the diode D2 -> first pulse is hosed. > > Won't run as-is for me; I get "D2, missing diode nodes" > > A 1T resistor across the diode (useful kludge when Spice barfs at floating > nodes and things), allows it to run. > > I get three clean pulses with either anode connected, cathode connected, > or both. No diode screws up the first pulse. Interestingly, changing diode > type to 1N4148 (higher Cjo, higher tt) modifies this behavior. > > Substituting an "O" lossy transmission line model for the "T" model > regularizes things. No difference with either or both ends of the diode > disconnected or no diode at all. First pulse mangled in all cases. Adding > the fully-connected diode cleans things up. > > > I guess we are seeing a peculiarity of how the "O" (ideal) model works, > the "T" model appears to be more tractable. > > Try a lossy line model using: > > .model RG179 LTRA (len=4.0581 L=0.077u R=107.7m C=30.8p) > (Constants are per foot from Belden data), which gives an approximate 6.25 > nanosecond delay. > > It appears that the screwed up first pulse is down to source termination mismatch. > You have effectively 51 ohms, 50 external and 1 ohm in V1. Take the 1 ohm out of > the source, or make R1 49 ohms, and all the anomalies go away. > >Strange thing is, with the non-lossy TX line and disconnected diode I do not get any mangled pulses. Only when I remove the disconnected diode the first pulse gets mangled. Since it was already disconnected to begin with that should not make one iota of a difference. But it does. Maybe it's all different between versions, I use 4.07e. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●August 15, 20112011-08-15
On Mon, 15 Aug 2011 09:49:37 -0700, Joerg wrote:> Strange thing is, with the non-lossy TX line and disconnected diode I do > not get any mangled pulses. Only when I remove the disconnected diode > the first pulse gets mangled.That's what I saw, maybe I didn't make it clear enough.> Since it was already disconnected to begin > with that should not make one iota of a difference. But it does. Maybe > it's all different between versions, I use 4.07e.This is 4.00C I'll try extracting the Spice netlist and see if I can get it to run in good ol' Spice 3f4. All I got left with using the lossy line model was all on the first pulse, and was traceable to source termination. With 100% absorption of reflected energy it was all clean. -- "For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
Reply by ●August 15, 20112011-08-15
Fred Abse wrote:> On Mon, 15 Aug 2011 09:49:37 -0700, Joerg wrote: > >> Strange thing is, with the non-lossy TX line and disconnected diode I do >> not get any mangled pulses. Only when I remove the disconnected diode >> the first pulse gets mangled. > > That's what I saw, maybe I didn't make it clear enough. > >> Since it was already disconnected to begin >> with that should not make one iota of a difference. But it does. Maybe >> it's all different between versions, I use 4.07e. > > This is 4.00C > > I'll try extracting the Spice netlist and see if I can get it to run in > good ol' Spice 3f4. > > All I got left with using the lossy line model was all on the first pulse, > and was traceable to source termination. With 100% absorption of reflected > energy it was all clean. >Thing is, that won't be realistic in real life. Small transmission lines such as coaxes have quite a bit of tolerance on the impedance, sometimes as much as +/-10%. We'll have to live with that. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●August 15, 20112011-08-15
On Mon, 15 Aug 2011 10:07:35 -0700, Joerg wrote:> Thing is, that won't be realistic in real life. Small transmission lines > such as coaxes have quite a bit of tolerance on the impedance, sometimes > as much as +/-10%. We'll have to live with that.Stepping the source resistance or the line Zo +/-10% don't look good. -- "For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
Reply by ●August 15, 20112011-08-15
Fred Abse wrote:> On Mon, 15 Aug 2011 10:07:35 -0700, Joerg wrote: > >> Thing is, that won't be realistic in real life. Small transmission lines >> such as coaxes have quite a bit of tolerance on the impedance, sometimes >> as much as +/-10%. We'll have to live with that. > > Stepping the source resistance or the line Zo +/-10% don't look good. >I did that and it looks quite ok. The main thing in any IC is to not exceed abs max for peak voltage because then ... pop ... *PHUT* -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●August 15, 20112011-08-15
"Joerg" <invalid@invalid.invalid> a �crit dans le message de news:9asobhFipoU1@mid.individual.net...> petrus bitbyter wrote: >> "Joerg" <invalid@invalid.invalid> schreef in bericht >> news:9ar2nqF3ocU1@mid.individual.net... >>> Jim Thompson wrote: >>>> On Sun, 14 Aug 2011 15:33:20 -0700, Joerg <invalid@invalid.invalid> >>>> wrote: >>>> >>>>> Folks, >>>>> >>>>> This is close to voodoo but repeatable. Unfortunately I can't disclose >>>>> the schematic since it is for a client. Just wondering , anyone had >>>>> this >>>>> before? >>>>> >>>>> At the far end of a TX line I used to have a diode connected across >>>>> because a previous version of a chip would have such a substrat path. >>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now the >>>>> new iteration of the chip design won't have this diode path so I >>>>> chopped >>>>> off its cathode connection. Sims fine. So I deleted the diode -> >>>>> ka-crunch ... sim slows down and the ouput is junk. >>>>> >>>>> If I put the diode back in and connect only its anode -> fine. If I >>>>> leave the anode open and only connect the cathode it still sims but >>>>> the >>>>> results are different. >>>>> >>>>> <scratching head> >>>> Show just the netlist of that portion. Diode? In CMOS? The "diode" >>>> has >>>> other parts ;-) >>>> >>> Ok, it's attached, I cut our the proprietary swaths. The results are >>> very different but the basic effect is still there: >>> >>> Note that D2 is connected at the anode only. Run the sim, look at >>> V(n001), three nice clean pulses. Now delete the anode connection and >>> the diode D2 -> first pulse is hosed. >>> >>> -- >>> Regards, Joerg >>> >>> http://www.analogconsultants.com/ >> >> <snip> >> >> I got an extra 120V peak on the second pulse and a sharp dip in the third >> though not after removing the diode but before removing it. (See abse) >> Removing the diode makes the extra's disappear. Connecting the diode >> gives >> the weird pulses back. It make's a difference what type diode is chosen. >> A >> 1N914 and a 1N4148 give the same results. Several Schottkys and other >> silicons however seem to do no harm. >> > > I have no access to abse, but that kind behavior is exactly what I > meant. Different sim results while the netlist should not have caused a > difference.of course it should! You floating node makes for an ill conditionned matrix. Be thankful to Ltspice that it gives you some not too idiotic result. Most others would simply have returned an error message. You can circumvent that in most spices with either a gmin or an rshunt option which will make you node non floating. I suppose that ltspice just do that silently (or it coud not give you any result). Now, default gmin or rshunt are set to 10^12 ohm and solving such extrem matrices can lead to spurious errors. That coupled with the 1000k resistor that ties your tline to ground gives you the bad spikes. Delete the diode and, since you have no more dangling node, the matrix is much better conditionned and the solver has no reason to invent anything anymore. With your circuit, just reduce your 1000K to 1K, or replace it by a short - which changes nothing since a spice tline is all but your expected 4 feets coax (you need 2 tlines for that) - and your spike vanishes. Another way is to set reltol (from the spice tab, not the compression tab) to 100u or better. Yet another way is to change the integration method from trapezoidal to gear which, as a general rule, is slightly less accurate but provides some natural damping to the solving process and most of the times prevents such artefacts to occur. Maybe I stumbled upon a bug here and if this is corroborated Not at all. That's classic spice stuff :-)> by others I should send it in for Mike's crew. > > -- > Regards, Joerg > > http://www.analogconsultants.com/
Reply by ●August 15, 20112011-08-15
Fred_Bartoli wrote:> > "Joerg" <invalid@invalid.invalid> a �crit dans le message de > news:9asobhFipoU1@mid.individual.net... >> petrus bitbyter wrote: >>> "Joerg" <invalid@invalid.invalid> schreef in bericht >>> news:9ar2nqF3ocU1@mid.individual.net... >>>> Jim Thompson wrote: >>>>> On Sun, 14 Aug 2011 15:33:20 -0700, Joerg <invalid@invalid.invalid> >>>>> wrote: >>>>> >>>>>> Folks, >>>>>> >>>>>> This is close to voodoo but repeatable. Unfortunately I can't >>>>>> disclose >>>>>> the schematic since it is for a client. Just wondering , anyone >>>>>> had this >>>>>> before? >>>>>> >>>>>> At the far end of a TX line I used to have a diode connected across >>>>>> because a previous version of a chip would have such a substrat path. >>>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now the >>>>>> new iteration of the chip design won't have this diode path so I >>>>>> chopped >>>>>> off its cathode connection. Sims fine. So I deleted the diode -> >>>>>> ka-crunch ... sim slows down and the ouput is junk. >>>>>> >>>>>> If I put the diode back in and connect only its anode -> fine. If I >>>>>> leave the anode open and only connect the cathode it still sims >>>>>> but the >>>>>> results are different. >>>>>> >>>>>> <scratching head> >>>>> Show just the netlist of that portion. Diode? In CMOS? The >>>>> "diode" has >>>>> other parts ;-) >>>>> >>>> Ok, it's attached, I cut our the proprietary swaths. The results are >>>> very different but the basic effect is still there: >>>> >>>> Note that D2 is connected at the anode only. Run the sim, look at >>>> V(n001), three nice clean pulses. Now delete the anode connection and >>>> the diode D2 -> first pulse is hosed. >>>> >>>> -- >>>> Regards, Joerg >>>> >>>> http://www.analogconsultants.com/ >>> >>> <snip> >>> >>> I got an extra 120V peak on the second pulse and a sharp dip in the >>> third >>> though not after removing the diode but before removing it. (See abse) >>> Removing the diode makes the extra's disappear. Connecting the diode >>> gives >>> the weird pulses back. It make's a difference what type diode is >>> chosen. A >>> 1N914 and a 1N4148 give the same results. Several Schottkys and other >>> silicons however seem to do no harm. >>> >> >> I have no access to abse, but that kind behavior is exactly what I >> meant. Different sim results while the netlist should not have caused a >> difference. > > of course it should! > You floating node makes for an ill conditionned matrix. Be thankful to > Ltspice that it gives you some not too idiotic result. Most others would > simply have returned an error message. > You can circumvent that in most spices with either a gmin or an rshunt > option which will make you node non floating. > > I suppose that ltspice just do that silently (or it coud not give you > any result). >That is what a simulator should never do, silently adding stuff or connections. Very dangerous turf. It was supposed to give an error with the open diode. But it didn't.> Now, default gmin or rshunt are set to 10^12 ohm and solving such extrem > matrices can lead to spurious errors. > That coupled with the 1000k resistor that ties your tline to ground > gives you the bad spikes. > Delete the diode and, since you have no more dangling node, the matrix > is much better conditionned and the solver has no reason to invent > anything anymore. >All that is what I also thought. Until I deleted that diode, upon which the simulator fell flat on its belly. Rather unexpectedly.> With your circuit, just reduce your 1000K to 1K, or replace it by a > short - which changes nothing since a spice tline is all but your > expected 4 feets coax (you need 2 tlines for that) - and your spike > vanishes. Another way is to set reltol (from the spice tab, not the > compression tab) to 100u or better. Yet another way is to change the > integration method from trapezoidal to gear which, as a general rule, is > slightly less accurate but provides some natural damping to the solving > process and most of the times prevents such artefacts to occur. >Indeed, thanks! If I reduce it to 100K it works.> > > Maybe I stumbled upon a bug here and if this is corroborated > > Not at all. That's classic spice stuff :-) >Strange, I purposely chose 1M instead of several G. Wouldn't have thought 1M is too extreme for SPICE. But it looks like in this case it is. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●August 15, 20112011-08-15
"Joerg" <invalid@invalid.invalid> a �crit dans le message de news:9atfdtF8s5U1@mid.individual.net...> Fred_Bartoli wrote: >> >> "Joerg" <invalid@invalid.invalid> a �crit dans le message de >> news:9asobhFipoU1@mid.individual.net... >>> petrus bitbyter wrote: >>>> "Joerg" <invalid@invalid.invalid> schreef in bericht >>>> news:9ar2nqF3ocU1@mid.individual.net... >>>>> Jim Thompson wrote: >>>>>> On Sun, 14 Aug 2011 15:33:20 -0700, Joerg <invalid@invalid.invalid> >>>>>> wrote: >>>>>> >>>>>>> Folks, >>>>>>> >>>>>>> This is close to voodoo but repeatable. Unfortunately I can't >>>>>>> disclose >>>>>>> the schematic since it is for a client. Just wondering , anyone >>>>>>> had this >>>>>>> before? >>>>>>> >>>>>>> At the far end of a TX line I used to have a diode connected across >>>>>>> because a previous version of a chip would have such a substrat >>>>>>> path. >>>>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now >>>>>>> the >>>>>>> new iteration of the chip design won't have this diode path so I >>>>>>> chopped >>>>>>> off its cathode connection. Sims fine. So I deleted the diode -> >>>>>>> ka-crunch ... sim slows down and the ouput is junk. >>>>>>> >>>>>>> If I put the diode back in and connect only its anode -> fine. If I >>>>>>> leave the anode open and only connect the cathode it still sims >>>>>>> but the >>>>>>> results are different. >>>>>>> >>>>>>> <scratching head> >>>>>> Show just the netlist of that portion. Diode? In CMOS? The >>>>>> "diode" has >>>>>> other parts ;-) >>>>>> >>>>> Ok, it's attached, I cut our the proprietary swaths. The results are >>>>> very different but the basic effect is still there: >>>>> >>>>> Note that D2 is connected at the anode only. Run the sim, look at >>>>> V(n001), three nice clean pulses. Now delete the anode connection and >>>>> the diode D2 -> first pulse is hosed. >>>>> >>>>> -- >>>>> Regards, Joerg >>>>> >>>>> http://www.analogconsultants.com/ >>>> >>>> <snip> >>>> >>>> I got an extra 120V peak on the second pulse and a sharp dip in the >>>> third >>>> though not after removing the diode but before removing it. (See abse) >>>> Removing the diode makes the extra's disappear. Connecting the diode >>>> gives >>>> the weird pulses back. It make's a difference what type diode is >>>> chosen. A >>>> 1N914 and a 1N4148 give the same results. Several Schottkys and other >>>> silicons however seem to do no harm. >>>> >>> >>> I have no access to abse, but that kind behavior is exactly what I >>> meant. Different sim results while the netlist should not have caused a >>> difference. >> >> of course it should! >> You floating node makes for an ill conditionned matrix. Be thankful to >> Ltspice that it gives you some not too idiotic result. Most others would >> simply have returned an error message. >> You can circumvent that in most spices with either a gmin or an rshunt >> option which will make you node non floating. >> >> I suppose that ltspice just do that silently (or it coud not give you >> any result). >> > > That is what a simulator should never do, silently adding stuff or > connections. Very dangerous turf. It was supposed to give an error with > the open diode. But it didn't. > > >> Now, default gmin or rshunt are set to 10^12 ohm and solving such extrem >> matrices can lead to spurious errors. >> That coupled with the 1000k resistor that ties your tline to ground >> gives you the bad spikes. >> Delete the diode and, since you have no more dangling node, the matrix >> is much better conditionned and the solver has no reason to invent >> anything anymore. >> > > All that is what I also thought. Until I deleted that diode, upon which > the simulator fell flat on its belly. Rather unexpectedly. > > >> With your circuit, just reduce your 1000K to 1K, or replace it by a >> short - which changes nothing since a spice tline is all but your >> expected 4 feets coax (you need 2 tlines for that) - and your spike >> vanishes. Another way is to set reltol (from the spice tab, not the >> compression tab) to 100u or better. Yet another way is to change the >> integration method from trapezoidal to gear which, as a general rule, is >> slightly less accurate but provides some natural damping to the solving >> process and most of the times prevents such artefacts to occur. >> > > Indeed, thanks! If I reduce it to 100K it works. > >> >> >> Maybe I stumbled upon a bug here and if this is corroborated >> >> Not at all. That's classic spice stuff :-) >> > > Strange, I purposely chose 1M instead of several G. Wouldn't have > thought 1M is too extreme for SPICE. But it looks like in this case it is. >It's not the 1M resistor on its own. Your circuit is extremly weird, spice wise... You combine a lossless tline, extremely fast switching (sw switched are particularly weird), no damping anywhere, floating nodes, and so on. What do you expect? For example, just load your tline with a 0.1p cap and all returns to normal. Ideal, non physical schematics are often a clear path to funny results... You obviously haven't lived enough with spice ;-) -- thanks, Fred.
