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"Faking" extra resolution with an 8 bit DAC

Started by Bitrex February 12, 2011
I remember seeing an article online in one of the design mags a while 
back about how to "fake" extra resolution in a DAC by PWMing between 
adjacent values; I think there were code examples as well.  Does anyone 
that knows what I'm talking about maybe have a link to said article? 
Thanks.
Bitrex wrote:
> I remember seeing an article online in one of the design mags a while > back about how to "fake" extra resolution in a DAC by PWMing between > adjacent values; I think there were code examples as well. Does anyone > that knows what I'm talking about maybe have a link to said article? > Thanks.
One method is to use a timer interrupt and an auxiliary variable. Say your desired value is X.Y, where X is between 0 and 255, and Y is the fractional part (another 8 bits for the sake of argument). Using appropriate serialization, set X and Y someplace. Each time through your timer tick interrupt handler, increment an 8-bit static variable Z. If Z >= Y, set the DAC to X, otherwise set it to X+1. This won't improve the nonlinearity of the DAC, however. The INL you're more or less stuck with unless you can make a calibration table. To get rid of the DNL well enough that you don't have missing codes in your compound DAC/PWM, you can change the DAC in steps big enough to be guaranteed monotonic--in other words, if you have 2 LSB DNL, just use the upper 6 bits of the DAC, and PWM between X and X+4. You can also do simple noise-shaping things such as making Y a pseudorandom bit sequence instead of a counter, but there are a few subtleties with that, e.g. you lose the Y=0 code. Another approach is to use a coarse-fine strategy, summing a DAC output with a normal PWM. That'll make the ripple frequency much higher, but it's harder to get it accurate when you're done. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 email: hobbs (atsign) electrooptical (period) net http://electrooptical.net
On Sat, 12 Feb 2011 08:47:18 -0500, Bitrex
<bitrex@de.lete.earthlink.net> wrote:

>I remember seeing an article online in one of the design mags a while >back about how to "fake" extra resolution in a DAC by PWMing between >adjacent values; I think there were code examples as well. Does anyone >that knows what I'm talking about maybe have a link to said article? >Thanks.
You can apply the standard delta-sigma algorithm to an 8-bit DAC and extend its resolution. Lots of modern audio uses 1-bit DACs. The problem with extending an 8-bit dac to more bits, using delta-sigma or pwm, is the the differential linearity of an 8-bit dac is likely poor, so the resulting, say, 16-bit dac will have an ugly transfer function. You can fix that by adding some noise dithering to smooth out the codes. A 1-bit dac doesn't have that DNL problem. John
On 2/12/2011 9:27 AM, Phil Hobbs wrote:
> Bitrex wrote: >> I remember seeing an article online in one of the design mags a while >> back about how to "fake" extra resolution in a DAC by PWMing between >> adjacent values; I think there were code examples as well. Does anyone >> that knows what I'm talking about maybe have a link to said article? >> Thanks. > > > One method is to use a timer interrupt and an auxiliary variable. Say > your desired value is X.Y, where X is between 0 and 255, and Y is the > fractional part (another 8 bits for the sake of argument). Using > appropriate serialization, set X and Y someplace. > > Each time through your timer tick interrupt handler, increment an 8-bit > static variable Z. If Z >= Y, set the DAC to X, otherwise set it to X+1. > > This won't improve the nonlinearity of the DAC, however. The INL you're > more or less stuck with unless you can make a calibration table. To get > rid of the DNL well enough that you don't have missing codes in your > compound DAC/PWM, you can change the DAC in steps big enough to be > guaranteed monotonic--in other words, if you have 2 LSB DNL, just use > the upper 6 bits of the DAC, and PWM between X and X+4. > > You can also do simple noise-shaping things such as making Y a > pseudorandom bit sequence instead of a counter, but there are a few > subtleties with that, e.g. you lose the Y=0 code. > > Another approach is to use a coarse-fine strategy, summing a DAC output > with a normal PWM. That'll make the ripple frequency much higher, but > it's harder to get it accurate when you're done. > > Cheers > > Phil Hobbs >
Thanks for your reply - I think both approaches might be a viable option for my project. I do like the idea of summing a PWM output to obtain the fractional part, since the microcontroller I'm using already has a hardware PWM output available. I'll do some experimenting with that first, and the first method will be the fallback. The accuracy doesn't need to be great, I just need some "fill in" values to prevent the DAC output "zippering" when ramping up and down.
On 02/12/2011 06:27 AM, Phil Hobbs wrote:
> Bitrex wrote: >> I remember seeing an article online in one of the design mags a while >> back about how to "fake" extra resolution in a DAC by PWMing between >> adjacent values; I think there were code examples as well. Does anyone >> that knows what I'm talking about maybe have a link to said article? >> Thanks. > > > One method is to use a timer interrupt and an auxiliary variable. Say > your desired value is X.Y, where X is between 0 and 255, and Y is the > fractional part (another 8 bits for the sake of argument). Using > appropriate serialization, set X and Y someplace. > > Each time through your timer tick interrupt handler, increment an 8-bit > static variable Z. If Z >= Y, set the DAC to X, otherwise set it to X+1. > > This won't improve the nonlinearity of the DAC, however. The INL you're > more or less stuck with unless you can make a calibration table. To get > rid of the DNL well enough that you don't have missing codes in your > compound DAC/PWM, you can change the DAC in steps big enough to be > guaranteed monotonic--in other words, if you have 2 LSB DNL, just use > the upper 6 bits of the DAC, and PWM between X and X+4. > > You can also do simple noise-shaping things such as making Y a > pseudorandom bit sequence instead of a counter, but there are a few > subtleties with that, e.g. you lose the Y=0 code. > > Another approach is to use a coarse-fine strategy, summing a DAC output > with a normal PWM. That'll make the ripple frequency much higher, but > it's harder to get it accurate when you're done.
A first-order sigma-delta modulator is easy-peasy, doesn't take any more code than Phil's first PWM'd version and gives you as much resolution as you want. You're still left with the issues of DNL, so check your data sheets. For control loops all you really need is monotonicity, and I think most 8-bit DACs have that these days unless they're really fast. Most of the time that I use this technique it's for a PWM output that just needs a bit of extra resolution, so DNL simply isn't an issue -- the issues that come next are usually power consumption and residual noise, and they're usually not a big deal if you were coming close with your PWM output. I've even used this technique to get an audio output from a single FPGA pin -- all that I was shooting for was something as good as a monitor speaker on a modem, and I got better than that so I stopped. If I really needed good quality I'd do two things: first, I'd use at least a 2nd-order modulator, and maybe 3rd-order or 2nd-order with some noise injection to break up tones; second, I'd seriously consider having the FPGA drive an analog switch or whatever the coolest CMOS single-gate logic was, as a buffer, with its own super-clean supply and a very light resistive load into the low-pass filter. Here's an article. I wrote it, so it must be good :-) : http://www.eetimes.com/design/embedded/4006431/Sigma-delta-techniques-extend-DAC-resolution If that link's too long, here's a page on my site pointing to the article: http://www.wescottdesign.com/articles/sigmadelta.html And some other articles that you may find interesting: http://www.wescottdesign.com/articles.html -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Tim Wescott wrote:
> On 02/12/2011 06:27 AM, Phil Hobbs wrote: >> Bitrex wrote: >>> I remember seeing an article online in one of the design mags a while >>> back about how to "fake" extra resolution in a DAC by PWMing between >>> adjacent values; I think there were code examples as well. Does anyone >>> that knows what I'm talking about maybe have a link to said article? >>> Thanks. >> >> >> One method is to use a timer interrupt and an auxiliary variable. Say >> your desired value is X.Y, where X is between 0 and 255, and Y is the >> fractional part (another 8 bits for the sake of argument). Using >> appropriate serialization, set X and Y someplace. >> >> Each time through your timer tick interrupt handler, increment an 8-bit >> static variable Z. If Z >= Y, set the DAC to X, otherwise set it to X+1. >> >> This won't improve the nonlinearity of the DAC, however. The INL you're >> more or less stuck with unless you can make a calibration table. To get >> rid of the DNL well enough that you don't have missing codes in your >> compound DAC/PWM, you can change the DAC in steps big enough to be >> guaranteed monotonic--in other words, if you have 2 LSB DNL, just use >> the upper 6 bits of the DAC, and PWM between X and X+4. >> >> You can also do simple noise-shaping things such as making Y a >> pseudorandom bit sequence instead of a counter, but there are a few >> subtleties with that, e.g. you lose the Y=0 code. >> >> Another approach is to use a coarse-fine strategy, summing a DAC output >> with a normal PWM. That'll make the ripple frequency much higher, but >> it's harder to get it accurate when you're done. > > A first-order sigma-delta modulator is easy-peasy, doesn't take any more > code than Phil's first PWM'd version and gives you as much resolution as > you want.
> > You're still left with the issues of DNL, so check your data sheets. For > control loops all you really need is monotonicity, and I think most > 8-bit DACs have that these days unless they're really fast. > > Most of the time that I use this technique it's for a PWM output that > just needs a bit of extra resolution, so DNL simply isn't an issue -- > the issues that come next are usually power consumption and residual > noise, and they're usually not a big deal if you were coming close with > your PWM output. > > I've even used this technique to get an audio output from a single FPGA > pin -- all that I was shooting for was something as good as a monitor > speaker on a modem, and I got better than that so I stopped. If I really > needed good quality I'd do two things: first, I'd use at least a > 2nd-order modulator, and maybe 3rd-order or 2nd-order with some noise > injection to break up tones; second, I'd seriously consider having the > FPGA drive an analog switch or whatever the coolest CMOS single-gate > logic was, as a buffer, with its own super-clean supply and a very light > resistive load into the low-pass filter. > > Here's an article. I wrote it, so it must be good :-) : > > http://www.eetimes.com/design/embedded/4006431/Sigma-delta-techniques-extend-DAC-resolution >
Nice article. I've been wanting to try that out, and I actually have the opportunity this coming week, assuming my head clears up enough to do coding. (This is the first bad cold I've had in two or three years, so I can't complain too loudly. Slagging people off on Usenet takes many fewer coordinated brain cells, fortunately.) ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 email: hobbs (atsign) electrooptical (period) net http://electrooptical.net
On Feb 12, 5:25=A0pm, Bitrex <bit...@de.lete.earthlink.net> wrote:
> On 2/12/2011 9:27 AM, Phil Hobbs wrote: > > > > > Bitrex wrote: > >> I remember seeing an article online in one of the design mags a while > >> back about how to "fake" extra resolution in a DAC by PWMing between > >> adjacent values; I think there were code examples as well. Does anyone > >> that knows what I'm talking about maybe have a link to said article? > >> Thanks. > > > One method is to use a timer interrupt and an auxiliary variable. Say > > your desired value is X.Y, where X is between 0 and 255, and Y is the > > fractional part (another 8 bits for the sake of argument). Using > > appropriate serialization, set X and Y someplace. > > > Each time through your timer tick interrupt handler, increment an 8-bit > > static variable Z. If Z >=3D Y, set the DAC to X, otherwise set it to X=
+1.
> > > This won't improve the nonlinearity of the DAC, however. The INL you're > > more or less stuck with unless you can make a calibration table. To get > > rid of the DNL well enough that you don't have missing codes in your > > compound DAC/PWM, you can change the DAC in steps big enough to be > > guaranteed monotonic--in other words, if you have 2 LSB DNL, just use > > the upper 6 bits of the DAC, and PWM between X and X+4. > > > You can also do simple noise-shaping things such as making Y a > > pseudorandom bit sequence instead of a counter, but there are a few > > subtleties with that, e.g. you lose the Y=3D0 code. > > > Another approach is to use a coarse-fine strategy, summing a DAC output > > with a normal PWM. That'll make the ripple frequency much higher, but > > it's harder to get it accurate when you're done. > > > Cheers > > > Phil Hobbs > > Thanks for your reply - I think both approaches might be a viable option > for my project. =A0I do like the idea of summing a PWM output to obtain > the fractional part, since the microcontroller I'm using already has a > hardware PWM output available. I'll do some experimenting with that > first, and the first method will be the fallback. =A0The accuracy doesn't > need to be great, I just need some "fill in" values to prevent the DAC > output "zippering" when ramping up and down.
You'd be better off using the PWM output for the most significant bits, and using the eight-bit DAC for the lower order bits. It isn't all that difficult to to make an eight-bit PWM output where the individual levels are accurate to 12-bits or better, and the advantage of limiting the PWM to coarse quantisation is that low pass filter required to get rid of the switching noise has a realitively high 3dB point, which measn that you can use small capacitors - polypropylene or poly-styrene - with good stability and very little charge soak. -- Bill Sloman, Nijmegen
On Sat, 12 Feb 2011 10:19:12 -0800, Tim Wescott <tim@seemywebsite.com>
wrote:

[snip]
> >A first-order sigma-delta modulator is easy-peasy, doesn't take any more >code than Phil's first PWM'd version and gives you as much resolution as >you want. > >You're still left with the issues of DNL, so check your data sheets. >For control loops all you really need is monotonicity, and I think most >8-bit DACs have that these days unless they're really fast. >
[snip] I would hope so. I was building monolithic 8-bit DAC's in the '60's with guaranteed monotonicity.
> >Here's an article. I wrote it, so it must be good :-) : > >http://www.eetimes.com/design/embedded/4006431/Sigma-delta-techniques-extend-DAC-resolution > >If that link's too long, here's a page on my site pointing to the article: > >http://www.wescottdesign.com/articles/sigmadelta.html > >And some other articles that you may find interesting: > >http://www.wescottdesign.com/articles.html
...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Remember: Once you go over the hill, you pick up speed
On Sat, 12 Feb 2011 11:05:56 -0800 (PST), Bill Sloman
<bill.sloman@ieee.org> wrote:

>On Feb 12, 5:25&#2013266080;pm, Bitrex <bit...@de.lete.earthlink.net> wrote: >> On 2/12/2011 9:27 AM, Phil Hobbs wrote: >> >> >> >> > Bitrex wrote: >> >> I remember seeing an article online in one of the design mags a while >> >> back about how to "fake" extra resolution in a DAC by PWMing between >> >> adjacent values; I think there were code examples as well. Does anyone >> >> that knows what I'm talking about maybe have a link to said article? >> >> Thanks. >> >> > One method is to use a timer interrupt and an auxiliary variable. Say >> > your desired value is X.Y, where X is between 0 and 255, and Y is the >> > fractional part (another 8 bits for the sake of argument). Using >> > appropriate serialization, set X and Y someplace. >> >> > Each time through your timer tick interrupt handler, increment an 8-bit >> > static variable Z. If Z >= Y, set the DAC to X, otherwise set it to X+1. >> >> > This won't improve the nonlinearity of the DAC, however. The INL you're >> > more or less stuck with unless you can make a calibration table. To get >> > rid of the DNL well enough that you don't have missing codes in your >> > compound DAC/PWM, you can change the DAC in steps big enough to be >> > guaranteed monotonic--in other words, if you have 2 LSB DNL, just use >> > the upper 6 bits of the DAC, and PWM between X and X+4. >> >> > You can also do simple noise-shaping things such as making Y a >> > pseudorandom bit sequence instead of a counter, but there are a few >> > subtleties with that, e.g. you lose the Y=0 code. >> >> > Another approach is to use a coarse-fine strategy, summing a DAC output >> > with a normal PWM. That'll make the ripple frequency much higher, but >> > it's harder to get it accurate when you're done. >> >> > Cheers >> >> > Phil Hobbs >> >> Thanks for your reply - I think both approaches might be a viable option >> for my project. &#2013266080;I do like the idea of summing a PWM output to obtain >> the fractional part, since the microcontroller I'm using already has a >> hardware PWM output available. I'll do some experimenting with that >> first, and the first method will be the fallback. &#2013266080;The accuracy doesn't >> need to be great, I just need some "fill in" values to prevent the DAC >> output "zippering" when ramping up and down. > >You'd be better off using the PWM output for the most significant >bits, and using the eight-bit DAC for the lower order bits. It isn't >all that difficult to to make an eight-bit PWM output where the >individual levels are accurate to 12-bits or better, and the advantage >of limiting the PWM to coarse quantisation is that low pass filter >required to get rid of the switching noise has a realitively high 3dB >point, which measn that you can use small capacitors - polypropylene >or poly-styrene - with good stability and very little charge soak.
What about ripple? John
In article <qt-dndfwX6wREsvQnZ2dnUVZ_oadnZ2d@earthlink.com>,
Bitrex  <bitrex@de.lete.earthlink.net> wrote:

>I remember seeing an article online in one of the design mags a while >back about how to "fake" extra resolution in a DAC by PWMing between >adjacent values; I think there were code examples as well. Does anyone >that knows what I'm talking about maybe have a link to said article?
As a practical example, you could take a look at the PWM code used by the VE2ZAZ frequency controller (which disciplines a 10 MHz VXCO based on the pulse-per-second output from a GPS receiver). It extends the precision of a PIC's PWM output by a couple of bits, by alternating between values. The resulting output goes through a low-pass filter to average out the signal. http://ve2zaz.net/GPS_Std/GPS_Std.htm The same basic trick can be used for non-PWM DACs... just alternate between values periodically, and feed the output through a low-pass filter whose time constant is comfortably longer than your alternation cycle time. If you extend this approach to its extremes, you get a "1-bit DAC" such as are used in many modern CD players. At that point, the algorithm you use to derive the value-alternation pattern becomes quite important, as the proper "noise shaping" algorithm will move the noise created by this process up to high frequencies where it's more easily eliminated by the low-pass filter. -- Dave Platt <dplatt@radagast.org> AE6EO Friends of Jade Warrior home page: http://www.radagast.org/jade-warrior I do _not_ wish to receive unsolicited commercial email, and I will boycott any company which has the gall to send me such ads!