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I2S Audio DAC : Master Clock relationship

Started by Mahen K August 27, 2010
I amd trying to interface I2S audio from MCU connected to the DAC. Is
it OK if I just use the LRCLK, BCLK and SDATA from teh MCU and connect
the clean external Master clock (128-512Fs)to the DAC ignoring the
MCLK from the MCU. What does the following statement from PCM1798
datasheet mean? Is it necessary to supply th same master clock that
was used by the source (MCU) to generate LRCLK and BCLK and SDATA?



"The PCM1794 requires the synchronization of LRCK and the system
clock, but does not need a specific phase relation between LRCK and
the system clock. If the relationship between LRCK and the system
clock changes more than +/-6 BCLK, internal operation is initialized
within 1/fS"

m.j

Mahen K wrote:
> I amd trying to interface I2S audio from MCU connected to the DAC. Is > it OK if I just use the LRCLK, BCLK and SDATA from teh MCU and connect > the clean external Master clock (128-512Fs)to the DAC ignoring the > MCLK from the MCU. What does the following statement from PCM1798 > datasheet mean? Is it necessary to supply th same master clock that > was used by the source (MCU) to generate LRCLK and BCLK and SDATA?
All DAC clocks must be derived from the same source. The exact timing relationship between MCLK and BCLK doesn't matter as long as those clocks are not sliding one against the other. If your MCU is using the different clock source then the DAC, then you should set the DAC in the I2S master mode. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
On Aug 27, 10:27=A0pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
> Mahen K wrote: > > I amd trying to interface I2S audio from MCU connected to the DAC. Is > > it OK if I just use the LRCLK, BCLK and SDATA from teh MCU and connect > > the clean external Master clock (128-512Fs)to the DAC ignoring the > > MCLK from the MCU. What does the following statement from PCM1798 > > datasheet mean? Is it necessary to supply th same master clock that > > was used by the source (MCU) to generate LRCLK and BCLK and SDATA? > > All DAC clocks must be derived from the same source. The exact timing > relationship between MCLK and BCLK doesn't matter as long as those > clocks are not sliding one against the other. If your MCU is using the > different clock source then the DAC, then you should set the DAC in the > I2S master mode. > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultanthttp://www.abvolt.com
Thanks Vladimir. My MCU outputs I2S only in Master mode. So the DAC has to be in Slave mode. m.j