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"Random" Circuit Needed.

Started by Jim Thompson April 1, 2015
(On Fri, 03 Apr 2015 10:20:47 +1000, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

> On Thu, 02 Apr 2015 18:52:57 -0500, John Fields > <jfields@austininstruments.com> wrote: > >> On 2 Apr 2015 10:42:50 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >> >>> On 2015-04-01, Jim Thompson >>> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather" <eather@tpg.com.au> >>>> wrote: >>>> >>>>> On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson >>>>> <To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote: >>>>> >>>>>> On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs >>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>>>> >>>>>>> On 04/01/2015 02:00 PM, Jim Thompson wrote: >>>>>>>> For a simulation situation I need a random number generator with a >>>>>>>> twist... >>>>>>>> >>>>>>>> What I need to simulate is a "random" selection of one-of-16 >>>>>>>> outputs. >>>>>>>> >>>>>>>> Clock "speed" is 12.5kHz ;-) >>>>>>>> >>>>>>>> Built of 74HCxx parts is preferred... I have a full ensemble of >>>>>>>> those >>>>>>>> device in my PSpice library. >>>>>>>> >>>>>>>> Thanks in advance. >>>>>>>> >>>>>>>> ...Jim Thompson >>>>>>>> >>>>>>> >>>>>>> How random? You could use a 16-bit PRBS made from two HC299 and an >>>>>>> HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 >>>>>>> demux. >>>>>>> If you need better randomness, use four PRBSes of different >>>>>>> length. >>>>>>> >>>>>>> Cheers >>>>>>> >>>>>>> Phil Hobbs >>>>>> >>>>>> I just need semi-random enough to test a fast AGC. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>> there is a bias with the 8-bit just use the last 4 bit idea. With 255 >>>>> 'clocks' all states but 0000 will occur 16 times while 0000 will only >>>>> appear 15 - the cycle then repeats. The lack of the extra 0000 may >>>>> cause >>>>> the bias point to continually drift high. >>>> >>>> I was wondering about that myself... I'll see if there's a cure. >>> >>> r=(75*r+74)%65537 visits 0-65535 with no gaps. >>> >>> not that i'd want to build it using 74LS logic. >> >> --- >> But, if you had to, what would it look like, schematic-wise? >> >> John Fields > > <smirk>:-} > > ...Jim Thompson
Better(?) / easier is a Linear congruence generator- the simplest is s = 5*s + 1 (then mod 16) this outputs the sequence: 0 1 6 15 12 13 2 11 8 9 14 7 4 5 10 3 (multiply by 5 is just a shift right by 2 bits and an addition) + another addition of 1 mod 16 is just throw away everything but the 4 LSB's I still think LFSR is better - mod 65537 would be a bitch
On 2015-04-03, rickman <gnuarm@gmail.com> wrote:
> On 4/2/2015 7:52 PM, John Fields wrote: >> On 2 Apr 2015 10:42:50 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >> >>> On 2015-04-01, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather" <eather@tpg.com.au> >>>> wrote: >>>> >>>>> On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson >>>>> <To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote: >>>>> >>>>>> On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs >>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>>>> >>>>>>> On 04/01/2015 02:00 PM, Jim Thompson wrote: >>>>>>>> For a simulation situation I need a random number generator with a >>>>>>>> twist... >>>>>>>> >>>>>>>> What I need to simulate is a "random" selection of one-of-16 outputs. >>>>>>>> >>>>>>>> Clock "speed" is 12.5kHz ;-) >>>>>>>> >>>>>>>> Built of 74HCxx parts is preferred... I have a full ensemble of those >>>>>>>> device in my PSpice library. >>>>>>>> >>>>>>>> Thanks in advance. >>>>>>>> >>>>>>>> ...Jim Thompson >>>>>>>> >>>>>>> >>>>>>> How random? You could use a 16-bit PRBS made from two HC299 and an >>>>>>> HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux. >>>>>>> If you need better randomness, use four PRBSes of different length. >>>>>>> >>>>>>> Cheers >>>>>>> >>>>>>> Phil Hobbs >>>>>> >>>>>> I just need semi-random enough to test a fast AGC. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>> there is a bias with the 8-bit just use the last 4 bit idea. With 255 >>>>> 'clocks' all states but 0000 will occur 16 times while 0000 will only >>>>> appear 15 - the cycle then repeats. The lack of the extra 0000 may cause >>>>> the bias point to continually drift high. >>>> >>>> I was wondering about that myself... I'll see if there's a cure. >>> >>> r=(75*r+74)%65537 visits 0-65535 with no gaps. >>> >>> not that i'd want to build it using 74LS logic. >> >> --- >> But, if you had to, what would it look like, schematic-wise?
it'd look A bit like a LFSR except with serial adders instead of XORS and a bit tacked on to do the %65537 Given that task I'd take it as a hint to learn "FPGA"
> Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that > would be four adders. I assume the modulo value is a typo and should be > 65536 which comes free. I don't recall any 8 bit adder chips, so using > 4 bit ones that would need chips 7 since when adding 64 * r, the lower 4 > bits are always zero.
no, 65537 is correct. mod 65537 isn't too hard, it'd need a second shift register to subtract the overflow from the low 16 bits and subsequently add one if that substraction overflows. this doesn't visit all 65537 states either: 65536 loops back on itself. but it's not a desirable state. I did this in Z80 assembler back in the 80s it took, 15 or so op codes and used all of one register bank (7x 8bit), and I think about 50 clock cycles, so that'd manage 12.5Khz. -- umop apisdn
On 2 Apr 2015 20:59:32 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

>On 2015-04-02, John Fields <jfields@austininstruments.com> wrote: >> On 2 Apr 2015 10:48:15 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >> >>>On 2015-04-01, rickman <gnuarm@gmail.com> wrote: >>>> On 4/1/2015 6:31 PM, Jim Thompson wrote: >>>> >>>> Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke >>>> published one which adds a few gates to specifically inject the zero >>>> state.... >>> >>>yeah, but no LFSR visits all states. >> >> --- >> That's not true, but I've heard that position defended on semantic >> grounds because a "Linear Feedback Shift Register" can only include >> EXOR feedback. > >There is that: there are only three linear boolean operators, NOT, >XOR,XNOR, (and they can all be derived from XOR ) > >> My position is that that's bogus, since by changing the name to >> "Pseudo Random Sequence Generator" and employing the same additional >> logic in the LFSR's feedback path, both circuits will be >> topologically identical and each will visit all states. > >That would make it a non-linear FSR
--- That's precisely why I choose to call them both PRSGs and allay the semantic silliness in favor of what matters. John Fields
On Thu, 02 Apr 2015 20:25:08 -0400, rickman <gnuarm@gmail.com>
wrote:

>On 4/2/2015 7:52 PM, John Fields wrote: >> On 2 Apr 2015 10:42:50 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >> >>> On 2015-04-01, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather" <eather@tpg.com.au> >>>> wrote: >>>> >>>>> On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson >>>>> <To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote: >>>>> >>>>>> On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs >>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>>>> >>>>>>> On 04/01/2015 02:00 PM, Jim Thompson wrote: >>>>>>>> For a simulation situation I need a random number generator with a >>>>>>>> twist... >>>>>>>> >>>>>>>> What I need to simulate is a "random" selection of one-of-16 outputs. >>>>>>>> >>>>>>>> Clock "speed" is 12.5kHz ;-) >>>>>>>> >>>>>>>> Built of 74HCxx parts is preferred... I have a full ensemble of those >>>>>>>> device in my PSpice library. >>>>>>>> >>>>>>>> Thanks in advance. >>>>>>>> >>>>>>>> ...Jim Thompson >>>>>>>> >>>>>>> >>>>>>> How random? You could use a 16-bit PRBS made from two HC299 and an >>>>>>> HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux. >>>>>>> If you need better randomness, use four PRBSes of different length. >>>>>>> >>>>>>> Cheers >>>>>>> >>>>>>> Phil Hobbs >>>>>> >>>>>> I just need semi-random enough to test a fast AGC. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>> there is a bias with the 8-bit just use the last 4 bit idea. With 255 >>>>> 'clocks' all states but 0000 will occur 16 times while 0000 will only >>>>> appear 15 - the cycle then repeats. The lack of the extra 0000 may cause >>>>> the bias point to continually drift high. >>>> >>>> I was wondering about that myself... I'll see if there's a cure. >>> >>> r=(75*r+74)%65537 visits 0-65535 with no gaps. >>> >>> not that i'd want to build it using 74LS logic. >> >> --- >> But, if you had to, what would it look like, schematic-wise? > >Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that >would be four adders. I assume the modulo value is a typo and should be >65536 which comes free. I don't recall any 8 bit adder chips, so using >4 bit ones that would need chips 7 since when adding 64 * r, the lower 4 >bits are always zero.
--- That's not a schematic, and there's many a slip 'twixt the cup and the lip, especially when assumptions are made. Can you post a real schematic showing what you're talking about, please?
On Thu, 02 Apr 2015 17:42:55 -0400, rickman <gnuarm@gmail.com>
wrote:

>On 4/2/2015 4:51 PM, Jasen Betts wrote: >> On 2015-04-02, rickman <gnuarm@gmail.com> wrote: >>> On 4/2/2015 6:48 AM, Jasen Betts wrote: >>>> On 2015-04-01, rickman <gnuarm@gmail.com> wrote: >>>>> On 4/1/2015 6:31 PM, Jim Thompson wrote: >>>>> >>>>> Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke >>>>> published one which adds a few gates to specifically inject the zero >>>>> state.... >>>> >>>> yeah, but no LFSR visits all states. >>> >>> You haven't seen the app note. Why can't it include the zero state with >>> modification? >> >> I think there's something about linear feedback that requires the >> cycle length to be odd. > >The key word there is "something".
--- As noted earlier by Doctor Phil, there's _nothing_ that requires the cycle length, maximal or otherwise, to be odd. ---
>Technically once you make this mod it is not an LFSR anymore.
--- True; it reverts to being a Pseudo Random Sequence Generator, of which an LFSR is a subset. ---
>But that is what the OP wants, something that is *not* an LFSR >because the LFSR only covers 2^N-1 states and he wants 2^N.
--- Where did Jim say he was looking for 2^n? ---
>A rose by any other name....
--- called a turd, by someone trusted, would stink.
On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

> For a simulation situation I need a random number generator with a > twist... > > What I need to simulate is a "random" selection of one-of-16 outputs. > > Clock "speed" is 12.5kHz ;-) > > Built of 74HCxx parts is preferred... I have a full ensemble of those > device in my PSpice library. > > Thanks in advance. > > ...Jim Thompson
Jim do you have a model of a 7483?
On Tue, 14 Apr 2015 07:15:50 +1000, David Eather <eather@tpg.com.au> wrote:

> On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson > <To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote: > >> For a simulation situation I need a random number generator with a >> twist... >> >> What I need to simulate is a "random" selection of one-of-16 outputs. >> >> Clock "speed" is 12.5kHz ;-) >> >> Built of 74HCxx parts is preferred... I have a full ensemble of those >> device in my PSpice library. >> >> Thanks in advance. >> >> ...Jim Thompson > > > Jim do you have a model of a 7483?
or 74 x 283
On Tue, 14 Apr 2015 07:15:50 +1000, "David Eather" <eather@tpg.com.au>
wrote:

>7483
Yep. A PSpice model. Unfortunately I think it will only run on PSpice. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Tue, 14 Apr 2015 07:20:03 +1000, "David Eather" <eather@tpg.com.au>
wrote:

>On Tue, 14 Apr 2015 07:15:50 +1000, David Eather <eather@tpg.com.au> wrote: > >> On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote: >> >>> For a simulation situation I need a random number generator with a >>> twist... >>> >>> What I need to simulate is a "random" selection of one-of-16 outputs. >>> >>> Clock "speed" is 12.5kHz ;-) >>> >>> Built of 74HCxx parts is preferred... I have a full ensemble of those >>> device in my PSpice library. >>> >>> Thanks in advance. >>> >>> ...Jim Thompson >> >> >> Jim do you have a model of a 7483? > >or 74 x 283
Yes, also. I have a 16-long LFSR already running. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Tue, 14 Apr 2015 08:22:07 +1000, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

> On Tue, 14 Apr 2015 07:20:03 +1000, "David Eather" <eather@tpg.com.au> > wrote: > >> On Tue, 14 Apr 2015 07:15:50 +1000, David Eather <eather@tpg.com.au> >> wrote: >> >>> On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson >>> <To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote: >>> >>>> For a simulation situation I need a random number generator with a >>>> twist... >>>> >>>> What I need to simulate is a "random" selection of one-of-16 outputs. >>>> >>>> Clock "speed" is 12.5kHz ;-) >>>> >>>> Built of 74HCxx parts is preferred... I have a full ensemble of those >>>> device in my PSpice library. >>>> >>>> Thanks in advance. >>>> >>>> ...Jim Thompson >>> >>> >>> Jim do you have a model of a 7483? >> >> or 74 x 283 > > Yes, also. I have a 16-long LFSR already running. > > ...Jim Thompson
Just if you ever need one again - this is a 3 chip LCG that I have mentioned before N1 = 5*n0 + 1 It has all 16 states and valid data is clocked in on the falling edge of clock. They are PNG files. Sorry to be so late to the party http://www.datafilehost.com/d/c37024f6 http://www.datafilehost.com/d/a0730ba3