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BJT Amplifier Output Votlage Swing

Started by panfilero October 2, 2012
I'm having a hard time understanding the "negative swing" of a common-emitter amplifier.  There is a website called thesignalpath.com where a BJT amplifier is described.

The set up is a BJT with a collector resistor, an emitter resistor, 2.5V and -2.5V supplies, and we're taking the output off the collector.  The BJT has a Vce,sat = 0.2V  According to the website

maximum Vout = Vdd
positive swing = VRc
minimum Vout = -2.3V + VRc
negative swing = Vce - 0.2V

I understand the first three things, but the last one, negative voltage swing has me confused... why is the negative voltage swing defined as Vce - Vce,sat?

here's a link to the source

http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-and-characterization-of-a-single-transistor-bipolar-amplifier/#comments

much thanks!
On Tue, 2 Oct 2012 08:02:21 -0700 (PDT), panfilero <panfilero@gmail.com>
wrote:

>I'm having a hard time understanding the "negative swing" of a common-emitter amplifier. There is a website called thesignalpath.com where a BJT amplifier is described. > >The set up is a BJT with a collector resistor, an emitter resistor, 2.5V and -2.5V supplies, and we're taking the output off the collector. The BJT has a Vce,sat = 0.2V According to the website > >maximum Vout = Vdd >positive swing = VRc >minimum Vout = -2.3V + VRc >negative swing = Vce - 0.2V > >I understand the first three things, but the last one, negative voltage swing has me confused... why is the negative voltage swing defined as Vce - Vce,sat? > >here's a link to the source > >http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-and-characterization-of-a-single-transistor-bipolar-amplifier/#comments
What they're trying to say is that the negative swing is |VCC- - VCEsat|, or the magnitude of the negative swing is the negative supply minus the saturation voltage.
On Tuesday, October 2, 2012 11:19:15 AM UTC-5, k...@att.bizzzzzzzzzzzz wrote:
> On Tue, 2 Oct 2012 08:02:21 -0700 (PDT) > > wrote: > > > > >I'm having a hard time understanding the "negative swing" of a common-emitter amplifier. There is a website called thesignalpath.com where a BJT amplifier is described. > > > > > >The set up is a BJT with a collector resistor, an emitter resistor, 2.5V and -2.5V supplies, and we're taking the output off the collector. The BJT has a Vce,sat = 0.2V According to the website > > > > > >maximum Vout = Vdd > > >positive swing = VRc > > >minimum Vout = -2.3V + VRc > > >negative swing = Vce - 0.2V > > > > > >I understand the first three things, but the last one, negative voltage swing has me confused... why is the negative voltage swing defined as Vce - Vce,sat? > > > > > >here's a link to the source > > > > > >http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-and-characterization-of-a-single-transistor-bipolar-amplifier/#comments > > > > What they're trying to say is that the negative swing is |VCC- - VCEsat|, or > > the magnitude of the negative swing is the negative supply minus the > > saturation voltage.
so you think it's just a typo? That he really meant Vcc - Vce,sat and not Vce - Vce,sat?
On Tue, 2 Oct 2012 12:54:16 -0700 (PDT), panfilero <panfilero@gmail.com>
wrote:

>On Tuesday, October 2, 2012 11:19:15 AM UTC-5, k...@att.bizzzzzzzzzzzz wrote: >> On Tue, 2 Oct 2012 08:02:21 -0700 (PDT) >> >> wrote: >> >> >> >> >I'm having a hard time understanding the "negative swing" of a common-emitter amplifier. There is a website called thesignalpath.com where a BJT amplifier is described. >> >> > >> >> >The set up is a BJT with a collector resistor, an emitter resistor, 2.5V and -2.5V supplies, and we're taking the output off the collector. The BJT has a Vce,sat = 0.2V According to the website >> >> > >> >> >maximum Vout = Vdd >> >> >positive swing = VRc >> >> >minimum Vout = -2.3V + VRc >> >> >negative swing = Vce - 0.2V >> >> > >> >> >I understand the first three things, but the last one, negative voltage swing has me confused... why is the negative voltage swing defined as Vce - Vce,sat? >> >> > >> >> >here's a link to the source >> >> > >> >> >http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-and-characterization-of-a-single-transistor-bipolar-amplifier/#comments >> >> >> >> What they're trying to say is that the negative swing is |VCC- - VCEsat|, or >> >> the magnitude of the negative swing is the negative supply minus the >> >> saturation voltage. > >so you think it's just a typo? That he really meant Vcc - Vce,sat and not Vce - Vce,sat?
Yes.
On 10/2/2012 8:02 AM, panfilero wrote:
> I'm having a hard time understanding the "negative swing" of a common-emitter amplifier. There is a website called thesignalpath.com where a BJT amplifier is described. > > The set up is a BJT with a collector resistor, an emitter resistor, 2.5V and -2.5V supplies, and we're taking the output off the collector. The BJT has a Vce,sat = 0.2V According to the website > > maximum Vout = Vdd > positive swing = VRc > minimum Vout = -2.3V + VRc > negative swing = Vce - 0.2V > > I understand the first three things, but the last one, negative voltage swing has me confused... why is the negative voltage swing defined as Vce - Vce,sat? > > here's a link to the source > > http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-and-characterization-of-a-single-transistor-bipolar-amplifier/#comments > > much thanks!
Probably a big part of the reason for your confusion is that he does not explain where the equation comes from and it is not true until he adds the emitter capacitor a little later in the presentation. Without that capacitor it is not true. The circuit shown is an inverting amplifier. I.e. when the input (base) voltage goes higher, the output voltage goes lower and vice versa. Thus we get the maximum output voltage with a low input and the lowest output voltage with a high input voltage. The maximum output voltage occurs when the transistor is turned off and there is no current flow through Rc so Vrc goes to zero. This occurs with a low input voltage. The output voltage is Vcc. The output voltage at the bias point was Vcc - VRC. The swing in the output voltage was VRC. (Where Vcc is the positive supply voltage = 2.5 volts, and VRC is the bias voltage across the collector resistor.) The minimum output voltage occurs when we have driven the transistor into saturation. This occurs with a high input voltage which will give us high base, emitter, and collector currents. At saturation the voltage across the transistor is Vcesat. The increase in the collector current increases the voltage across the collector resistor. Without the emitter capacitor, it will also increase the emitter voltage. With the emitter capacitor the voltage at the emitter is held constant (for AC signals). The output voltage will be Ve plus Vce (where Ve is the emitter voltage and Vce is the voltage from the collector to the emitter). As we increase the collector current Vce can swing from its bias value down to Vcesat. If the emitter voltage is held constant then all of this voltage swing be at the output so the output swing will be VCE - Vcestat (where VCE is the bias collector to emitter voltage). This is the result that he gives. If the emitter capacitor is not present then part of the transistor voltage swing will go to the emitter resistor and the swing in the output voltage will be smaller. Dan
On Tue, 2 Oct 2012 08:02:21 -0700 (PDT), panfilero
<panfilero@gmail.com> wrote:

>I'm having a hard time understanding the "negative swing" of a =
common-emitter amplifier. There is a website called thesignalpath.com = where a BJT amplifier is described.
> >The set up is a BJT with a collector resistor, an emitter resistor, 2.5V=
and -2.5V supplies, and we're taking the output off the collector. The = BJT has a Vce,sat =3D 0.2V According to the website
> >maximum Vout =3D Vdd >positive swing =3D VRc >minimum Vout =3D -2.3V + VRc >negative swing =3D Vce - 0.2V > >I understand the first three things, but the last one, negative voltage =
swing has me confused... why is the negative voltage swing defined as Vce= - Vce,sat?
> >here's a link to the source > >http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-=
and-characterization-of-a-single-transistor-bipolar-amplifier/#comments
> >much thanks!
Shahriar must work for Rigol! I think Dan pretty much nails it. But let me say it differently. He's talking about the quiescent value for Vce. He set Iq=3D2mA (quiescent current) in his design. This just means the center operating point which, based on his assumptions (Ie=3DIc), also flows through Re and Rc. He selected 1.6V as the drop for each and therefore the values as 800 ohms each, too. This leaves 1.8V for the quiescent Vce. (Vce will experience BIG changes in operation, but this is the Vce value that happens when the signal is not connected and the circuit is just sitting at its DC operating point. That 1.8V is the Vce he is talking about. The reason he subtracts 0.2V (for the saturation voltage) is that Vce can't really get smaller than that without serious distortion. (Actually, it's better to leave more like 0.8V (so that the base-collector junction stays reverse biased, but his power supply rails were VERY small and he simply couldn't afford to waste it. Besides, it doesn't matter. He only wants 1V swing peak to peak, anyway. So if he has 1.6V on Re and 1.8V on Vce, then 0.5V downward would mean 1.3V on Vce, which is WAY above the 0.8V I'm saying would be better. So he never really drove that thing anywhere NEAR Vce=3D0.2V. He was just using that figure for an absolute worst case (that you would never really use in reality.) Jon
On Tuesday, October 2, 2012 10:02:21 AM UTC-5, panfilero wrote:
> I'm having a hard time understanding the "negative swing" of a common-emitter amplifier. There is a website called thesignalpath.com where a BJT amplifier is described. > > > > The set up is a BJT with a collector resistor, an emitter resistor, 2.5V and -2.5V supplies, and we're taking the output off the collector. The BJT has a Vce,sat = 0.2V According to the website > > > > maximum Vout = Vdd > > positive swing = VRc > > minimum Vout = -2.3V + VRc > > negative swing = Vce - 0.2V > > > > I understand the first three things, but the last one, negative voltage swing has me confused... why is the negative voltage swing defined as Vce - Vce,sat? > > > > here's a link to the source > > > > http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-design-and-characterization-of-a-single-transistor-bipolar-amplifier/#comments > > > > much thanks!
Thanks felas, between yalls two explanations i have a much better idea what he was up to. much apprecaited.
On Oct 3, 4:13=A0am, Jon Kirwan <j...@infinitefactors.org> wrote:
> On Tue, 2 Oct 2012 08:02:21 -0700 (PDT), panfilero > > > > > > <panfil...@gmail.com> wrote: > >I'm having a hard time understanding the "negative swing" of a common-em=
itter amplifier. =A0There is a website called thesignalpath.com where a BJT= amplifier is described.
> > >The set up is a BJT with a collector resistor, an emitter resistor, 2.5V=
and -2.5V supplies, and we're taking the output off the collector. =A0The = BJT has a Vce,sat =3D 0.2V =A0According to the website
> > >maximum Vout =3D Vdd > >positive swing =3D VRc > >minimum Vout =3D -2.3V + VRc > >negative swing =3D Vce - 0.2V > > >I understand the first three things, but the last one, negative voltage =
swing has me confused... why is the negative voltage swing defined as Vce -= Vce,sat?
> > >here's a link to the source > > >http://thesignalpath.com/blogs/2012/09/23/tutorial-on-the-theory-desi... > > >much thanks! > > Shahriar must work for Rigol! > > I think Dan pretty much nails it. But let me say it > differently. He's talking about the quiescent value for Vce. > He set Iq=3D2mA (quiescent current) in his design. This just > means the center operating point which, based on his > assumptions (Ie=3DIc), also flows through Re and Rc. He > selected 1.6V as the drop for each and therefore the values > as 800 ohms each, too. This leaves 1.8V for the quiescent > Vce. (Vce will experience BIG changes in operation, but this > is the Vce value that happens when the signal is not > connected and the circuit is just sitting at its DC operating > point. That 1.8V is the Vce he is talking about. > > The reason he subtracts 0.2V (for the saturation voltage) is > that Vce can't really get smaller than that without serious > distortion. (Actually, it's better to leave more like 0.8V > (so that the base-collector junction stays reverse biased, > but his power supply rails were VERY small and he simply > couldn't afford to waste it. Besides, it doesn't matter. He > only wants 1V swing peak to peak, anyway. So if he has 1.6V > on Re and 1.8V on Vce, then 0.5V downward would mean 1.3V on > Vce, which is WAY above the 0.8V I'm saying would be better. > So he never really drove that thing anywhere NEAR Vce=3D0.2V. > He was just using that figure for an absolute worst case > (that you would never really use in reality.) > > Jon- Hide quoted text - > > - Show quoted text -
Say can I ask what is perhaps a silly question? (I won't wait for permission :^) Now, I don't do much design with transistors, (since opamps are so much easier), but I thought that you should choose the collector voltage to be ~1/2 the supply voltage for maximum swing of the output. This comes from AoE... which IIRC also states that the maximum gain from a common E amp is 1/2 the supply voltage divided by the thermal voltage (25mV). (I know this ignores the CE saturation voltage.) So it seems that Shahriar could have choosen his operating point a bit better and gotten closer to his gain of 100 in one stage. Say if you want, even more gain can you run the collector even lower and give up the maximum voltage swing? George H.
On Wed, 3 Oct 2012 09:09:01 -0700 (PDT), George Herold
<gherold@teachspin.com> wrote:

>On Oct 3, 4:13=A0am, Jon Kirwan <j...@infinitefactors.org> wrote: >> On Tue, 2 Oct 2012 08:02:21 -0700 (PDT), panfilero >><snip> >> Shahriar must work for Rigol! >> >> I think Dan pretty much nails it. But let me say it >> differently. He's talking about the quiescent value for Vce. >> He set Iq=3D2mA (quiescent current) in his design. This just >> means the center operating point which, based on his >> assumptions (Ie=3DIc), also flows through Re and Rc. He >> selected 1.6V as the drop for each and therefore the values >> as 800 ohms each, too. This leaves 1.8V for the quiescent >> Vce. (Vce will experience BIG changes in operation, but this >> is the Vce value that happens when the signal is not >> connected and the circuit is just sitting at its DC operating >> point. That 1.8V is the Vce he is talking about. >> >> The reason he subtracts 0.2V (for the saturation voltage) is >> that Vce can't really get smaller than that without serious >> distortion. (Actually, it's better to leave more like 0.8V >> (so that the base-collector junction stays reverse biased, >> but his power supply rails were VERY small and he simply >> couldn't afford to waste it. Besides, it doesn't matter. He >> only wants 1V swing peak to peak, anyway. So if he has 1.6V >> on Re and 1.8V on Vce, then 0.5V downward would mean 1.3V on >> Vce, which is WAY above the 0.8V I'm saying would be better. >> So he never really drove that thing anywhere NEAR Vce=3D0.2V. >> He was just using that figure for an absolute worst case >> (that you would never really use in reality.) > >Say can I ask what is perhaps a silly question? >(I won't wait for permission :^)
:)
>Now, I don't do much design with transistors, (since opamps are so >much easier),
and noisier unless you pay dearly
>but I thought that you should choose the collector >voltage to be ~1/2 the supply voltage for maximum swing of the >output. This comes from AoE... which IIRC also states that the >maximum gain from a common E amp is 1/2 the supply voltage divided by >the thermal voltage (25mV). (I know this ignores the CE saturation >voltage.)
That's another "rule of thumb," but it is not gospel. I've gradually (that means I'm mentally slow) learned that there are lots of considerations. Anyway, if you "work the equations fully" and take into account all the important things too then you will find that the 1/2 supply rule isn't reality, either. It's decent, that's all. Centering the maximum non-saturated collector swing involves more things than that, though. And it's not always the goal, besides. Since you bring of AofE, take a look at the student manual for it. They actually walk you though a CE design starting on page 115. You will see some competing considerations there and no discussion at all about setting Iq. Which may also be important. No rule of thumb is gospel. They just help a little, is all. And it works a lot better when you have a large magnitude supply rail pair than when you don't. This guy was working with 5V. Some, but not all, considerations: The DC operating point should, for temperature stability, have the emitter resistor with as much voltage drop as you can afford to have. This is because of kT/q in the BJT emitter (it's the cause of little re which depends on Ie and thereby also on Iq). That voltage (around 26mV at room temp) is HIGHLY temperature dependent. So dwarfing it with a drop across Re helps make it irrelevant. AofE's student manual recommends at least 1V there to make the T-dependent 26mV not so important. The author of that video didn't say any of this, but the 1.6V he assigned is not only reasonable it's also a good idea for temperature stability. This, of course, "steals away" some of the range then available between Rc and Vce. Also, you should allow for a continuously reverse biased BC junction, if possible, as well. So that sets up a minimum Vce of 0.8V-1.0V that you should NOT put into your calculations of the "center point" for the collector. Again this steals away some of what you plug into your calculations. If you have a 15V power supply or more you won't care. Just center Vc and be done with it. But if you are stuck designing something for a pair of 1.5V batteries, then you start thinking more about the details and struggling just a little differently when balancing your priorities. There is no bright line rule anywhere. Your brain cannot ever be fully disengaged and there is always more to learn, too, I think. No matter what you think you know, there is something else out there that you haven't yet experienced and your "rules" will then get you in trouble if your brain isn't turned fully on. So assume I have 5V and use AofE's rule of 1V for Re. And then apply my own 1V for Vce-min. This leaves 3V total (5V minus 2V) for collector "swing." So I take the 1V for Re, add 1V for Vce-min, then add 1.5V for half of the 3V swing and wind up with 3.5V for quiescent Vc, right? That's not 2.5V. It's 3.5V. But it maximizes the swing under my rules of not allowing BC to forward bias and allowing AofE's rule for temperature stability. I don't use the 1/2 V-supply rule unless I'm teaching someone who knows nothing about BJTs and wants to just get started.
>So it seems that Shahriar could have choosen his operating point a bit >better and gotten closer to his gain of 100 in one stage. Say if you >want, even more gain can you run the collector even lower and give up >the maximum voltage swing?
Yes, he doesn't say it but he makes that point indirectly when he talks about the max gain of A=3D-64 depending upon 40*Iq*Rc, or 40 times the quiescent voltage drop of Rc. But as I've said above, you have other considerations as well that compete with just throwing more voltage drop at Rc. Jon
On Wed, 03 Oct 2012 15:53:32 -0700, I wrote:

>On Wed, 3 Oct 2012 09:09:01 -0700 (PDT), George Herold ><gherold@teachspin.com> wrote: > >>On Oct 3, 4:13=A0am, Jon Kirwan <j...@infinitefactors.org> wrote: >>> On Tue, 2 Oct 2012 08:02:21 -0700 (PDT), panfilero >>><snip> >>> Shahriar must work for Rigol! >>> >>> I think Dan pretty much nails it. But let me say it >>> differently. He's talking about the quiescent value for Vce. >>> He set Iq=3D2mA (quiescent current) in his design. This just >>> means the center operating point which, based on his >>> assumptions (Ie=3DIc), also flows through Re and Rc. He >>> selected 1.6V as the drop for each and therefore the values >>> as 800 ohms each, too. This leaves 1.8V for the quiescent >>> Vce. (Vce will experience BIG changes in operation, but this >>> is the Vce value that happens when the signal is not >>> connected and the circuit is just sitting at its DC operating >>> point. That 1.8V is the Vce he is talking about. >>> >>> The reason he subtracts 0.2V (for the saturation voltage) is >>> that Vce can't really get smaller than that without serious >>> distortion. (Actually, it's better to leave more like 0.8V >>> (so that the base-collector junction stays reverse biased, >>> but his power supply rails were VERY small and he simply >>> couldn't afford to waste it. Besides, it doesn't matter. He >>> only wants 1V swing peak to peak, anyway. So if he has 1.6V >>> on Re and 1.8V on Vce, then 0.5V downward would mean 1.3V on >>> Vce, which is WAY above the 0.8V I'm saying would be better. >>> So he never really drove that thing anywhere NEAR Vce=3D0.2V. >>> He was just using that figure for an absolute worst case >>> (that you would never really use in reality.) >> >>Say can I ask what is perhaps a silly question? >>(I won't wait for permission :^) > >:) > >>Now, I don't do much design with transistors, (since opamps are so >>much easier), > >and noisier unless you pay dearly > >>but I thought that you should choose the collector >>voltage to be ~1/2 the supply voltage for maximum swing of the >>output. This comes from AoE... which IIRC also states that the >>maximum gain from a common E amp is 1/2 the supply voltage divided by >>the thermal voltage (25mV). (I know this ignores the CE saturation >>voltage.) > >That's another "rule of thumb," but it is not gospel. I've >gradually (that means I'm mentally slow) learned that there >are lots of considerations. Anyway, if you "work the >equations fully" and take into account all the important >things too then you will find that the 1/2 supply rule isn't >reality, either. It's decent, that's all. Centering the >maximum non-saturated collector swing involves more things >than that, though. And it's not always the goal, besides. > >Since you bring of AofE, take a look at the student manual >for it. They actually walk you though a CE design starting on >page 115. You will see some competing considerations there >and no discussion at all about setting Iq. Which may also be >important. No rule of thumb is gospel. They just help a >little, is all. And it works a lot better when you have a >large magnitude supply rail pair than when you don't. This >guy was working with 5V. > >Some, but not all, considerations: The DC operating point >should, for temperature stability, have the emitter resistor >with as much voltage drop as you can afford to have. This is >because of kT/q in the BJT emitter (it's the cause of little >re which depends on Ie and thereby also on Iq). That voltage >(around 26mV at room temp) is HIGHLY temperature dependent. >So dwarfing it with a drop across Re helps make it >irrelevant. AofE's student manual recommends at least 1V >there to make the T-dependent 26mV not so important. The >author of that video didn't say any of this, but the 1.6V he >assigned is not only reasonable it's also a good idea for >temperature stability. This, of course, "steals away" some of >the range then available between Rc and Vce. Also, you should >allow for a continuously reverse biased BC junction, if >possible, as well. So that sets up a minimum Vce of 0.8V-1.0V >that you should NOT put into your calculations of the "center >point" for the collector. Again this steals away some of what >you plug into your calculations. If you have a 15V power >supply or more you won't care. Just center Vc and be done >with it. But if you are stuck designing something for a pair >of 1.5V batteries, then you start thinking more about the >details and struggling just a little differently when >balancing your priorities. There is no bright line rule >anywhere. Your brain cannot ever be fully disengaged and >there is always more to learn, too, I think. No matter what >you think you know, there is something else out there that >you haven't yet experienced and your "rules" will then get >you in trouble if your brain isn't turned fully on. > >So assume I have 5V and use AofE's rule of 1V for Re. And >then apply my own 1V for Vce-min. This leaves 3V total (5V >minus 2V) for collector "swing." So I take the 1V for Re, add >1V for Vce-min, then add 1.5V for half of the 3V swing and >wind up with 3.5V for quiescent Vc, right? That's not 2.5V. >It's 3.5V. But it maximizes the swing under my rules of not >allowing BC to forward bias and allowing AofE's rule for >temperature stability. > >I don't use the 1/2 V-supply rule unless I'm teaching someone >who knows nothing about BJTs and wants to just get started. > >>So it seems that Shahriar could have choosen his operating point a bit >>better and gotten closer to his gain of 100 in one stage. Say if you >>want, even more gain can you run the collector even lower and give up >>the maximum voltage swing? > >Yes, he doesn't say it but he makes that point indirectly >when he talks about the max gain of A=3D-64 depending upon >40*Iq*Rc, or 40 times the quiescent voltage drop of Rc. > >But as I've said above, you have other considerations as well >that compete with just throwing more voltage drop at Rc. > >Jon
Damn, forgot to mention: I'm just an ignorant hobbyist and not a professional. I've had ZERO formal electronics training -- and I mean ZERO when I say it. I'm "book-learned" with very very modest experience behind it. Nothing I've said should be taken over what a trained professional says about any of this. Jon