On Wed, 18 Oct 2023 10:27:30 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:
>On Wednesday, October 18, 2023 at 12:25:40?PM UTC-4, John Larkin wrote:
>> On Wed, 18 Oct 2023 08:38:51 -0700 (PDT), Fred Bloggs
>> <bloggs.fred...@gmail.com> wrote:
>> >On Tuesday, October 17, 2023 at 10:35:55?PM UTC-4, John Larkin wrote:
>> >> https://www.dropbox.com/scl/fi/vcp5qiwxt59cjht493ps2/P945A_top.jpg?rlkey=0qov5oq9dk7pwcqfs6ttspvxm&raw=1
>> >>
>> >> https://www.dropbox.com/scl/fi/gpxexekknt7pl0gyfzl03/P954A_bot.jpg?rlkey=tsgj15uwykg6l1fl2x0llht3z&raw=1
>> >>
>> >> Each of the eight dpak fets has 400 filled vias from top to bottom
>> >> copper.
>> >>
>> >> If I hold the board at just the right grazing incidence, looking at a
>> >> distant light, I can barely see the tiny via dimples.
>> >
>> >That must have been expensive.
>> We just yesterday received 10 boards, 5-day turn, delivered by
>> courier, $300 each. We expect them to be more reasonable in
>> production. The one in the pic is the 11th "solder sample" board, not
>> guaranteed to be functional. We expect to have a few assembled this
>> morning.
>>
>> It's 6 layers, 1 oz copper on top and bottom, 2 oz on the inner
>> layers. It's heavy!
>>
>> The vias are plated 2oz min for thermal conductivity, and epoxy filled
>> so they don't steal solder from the dpak fets. I'm impressed that the
>> giant gold pads look perfectly flat; it takes work to see that there
>> are actually 400 vias per fet.
>
>That's not bad at all for a 5-day turnaround on boards of that complexity. It wasn't too long ago it would have been 1500.00
We do something similar but instead of that many VIAs, we have the PCB
over-plated. Looks the same from the bottom side but you see the
holes on the top side.
There certainly has to be an optimum amount of vias that will work
best for heat transfer. I seem to remember wanting to do a test of
different amounts of vias, maybe on one PCB to test that.
Or, should be simple to just calculate all of the surface area in the
vias with different amounts of vias. Some make this work even with
solder mask on the bottom side plus a sil pad or whatever.
I'm sure both your method and our methods work just fine though.
Neither is cheap but I wonder what the optimum is between price and
number of vias and effectivity of more or less vias ?
boB
Reply by Fred Bloggs●October 18, 20232023-10-18
On Wednesday, October 18, 2023 at 12:25:40 PM UTC-4, John Larkin wrote:
> On Wed, 18 Oct 2023 08:38:51 -0700 (PDT), Fred Bloggs
> <bloggs.fred...@gmail.com> wrote:
> >On Tuesday, October 17, 2023 at 10:35:55?PM UTC-4, John Larkin wrote:
> >> https://www.dropbox.com/scl/fi/vcp5qiwxt59cjht493ps2/P945A_top.jpg?rlkey=0qov5oq9dk7pwcqfs6ttspvxm&raw=1
> >>
> >> https://www.dropbox.com/scl/fi/gpxexekknt7pl0gyfzl03/P954A_bot.jpg?rlkey=tsgj15uwykg6l1fl2x0llht3z&raw=1
> >>
> >> Each of the eight dpak fets has 400 filled vias from top to bottom
> >> copper.
> >>
> >> If I hold the board at just the right grazing incidence, looking at a
> >> distant light, I can barely see the tiny via dimples.
> >
> >That must have been expensive.
> We just yesterday received 10 boards, 5-day turn, delivered by
> courier, $300 each. We expect them to be more reasonable in
> production. The one in the pic is the 11th "solder sample" board, not
> guaranteed to be functional. We expect to have a few assembled this
> morning.
>
> It's 6 layers, 1 oz copper on top and bottom, 2 oz on the inner
> layers. It's heavy!
>
> The vias are plated 2oz min for thermal conductivity, and epoxy filled
> so they don't steal solder from the dpak fets. I'm impressed that the
> giant gold pads look perfectly flat; it takes work to see that there
> are actually 400 vias per fet.
That's not bad at all for a 5-day turnaround on boards of that complexity. It wasn't too long ago it would have been 1500.00
Reply by John Larkin●October 18, 20232023-10-18
On Wed, 18 Oct 2023 08:38:51 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:
We just yesterday received 10 boards, 5-day turn, delivered by
courier, $300 each. We expect them to be more reasonable in
production. The one in the pic is the 11th "solder sample" board, not
guaranteed to be functional. We expect to have a few assembled this
morning.
It's 6 layers, 1 oz copper on top and bottom, 2 oz on the inner
layers. It's heavy!
The vias are plated 2oz min for thermal conductivity, and epoxy filled
so they don't steal solder from the dpak fets. I'm impressed that the
giant gold pads look perfectly flat; it takes work to see that there
are actually 400 vias per fet.
Reply by Fred Bloggs●October 18, 20232023-10-18
On Tuesday, October 17, 2023 at 10:35:55 PM UTC-4, John Larkin wrote: