On Fri, 24 Jun 2022 23:28:54 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
>Am 24.06.22 um 19:48 schrieb Dimiter_Popoff:
>> On 6/24/2022 20:31, Lasse Langwadt Christensen wrote:
>
>>>> Perhaps so, but Power is also free now. I have only looked at
>>>> risc-v docs - to begin with it is little-endian
>>>
>>> so is all the other major platforms
>>>
>>>> (a more serious > drawback than people have been made to think for
>>>> decades though not a show-stopper).
>>>
>>> what serious drawbacks?
>>
>> Do you have enough experience at low level programming to be able
>> to judge that.
>
>Oh, since 8080.
>
>The real fun starts when the CPU offers both, trying to
>get all the customers. And then some details like bit field
>insert are inconsistent with both modes.
>
>And little/big endian comes from the Gulliver book by Jonathan
>Swift where two tribes go to war over the question if eggs
>should be opened on the big or little end. In computers, it is
>just so important.
There is a long history. This is from the early days, when the Endian
Wars broke out:
.<https://www.rfc-editor.org/ien/ien137.txt>
The above was first posted in "Re: the secret sauce" on 8 Jan 2021.
Joe Gwinn
Reply by Dimiter_Popoff●June 24, 20222022-06-24
On 6/25/2022 0:28, Gerhard Hoffmann wrote:
> Am 24.06.22 um 19:48 schrieb Dimiter_Popoff:
>> On 6/24/2022 20:31, Lasse Langwadt Christensen wrote:
>
>>>> Perhaps so, but Power is also free now. I have only looked at
>>>> risc-v docs - to begin with it is little-endian
>>>
>>> so is all the other major platforms
>>>
>>>> (a more serious > drawback than people have been made to think for
>>>> decades though not a show-stopper).
>>>
>>> what serious drawbacks?
>>
>> Do you have enough experience at low level programming to be able
>> to judge that.
>
> Oh, since 8080.
Me since the 6800 (used more the 6809 though).
>
> The real fun starts when the CPU offers both, trying to
> get all the customers. And then some details like bit field
> insert are inconsistent with both modes.
Some power architecture cores do both quite well. Within
our vpa toolchain you either use "move.size" (big endian)
or "mover.size" (byte reversed, little endian). Neither
needs extra opcodes on the cores we have used so far.
>
> And little/big endian commes from the Gulliver book by Jonathan
> Swift where two tribes go to war over the question if eggs
> should be opened on the big or little end. In computers, it is
> just so important.
Like I said it is no game stopper but there is what is called
"network byte order", we read and write left to right, bit
fields are consistently addressed only on true big endian
(where bit 0 is the most significant bit) etc.
All of the problems caused by little endian can be worked
around and have been, of course. But one can live without these.
Reply by Gerhard Hoffmann●June 24, 20222022-06-24
Am 24.06.22 um 19:48 schrieb Dimiter_Popoff:
> On 6/24/2022 20:31, Lasse Langwadt Christensen wrote:
>>> Perhaps so, but Power is also free now. I have only looked at
>>> risc-v docs - to begin with it is little-endian
>>
>> so is all the other major platforms
>>
>>> (a more serious > drawback than people have been made to think for
>>> decades though not a show-stopper).
>>
>> what serious drawbacks?
>
> Do you have enough experience at low level programming to be able
> to judge that.
Oh, since 8080.
The real fun starts when the CPU offers both, trying to
get all the customers. And then some details like bit field
insert are inconsistent with both modes.
And little/big endian commes from the Gulliver book by Jonathan
Swift where two tribes go to war over the question if eggs
should be opened on the big or little end. In computers, it is
just so important.
cheers, Gerhard.
Arghh, the <> brackets ask the posting software not to insert
CRLF, tabs or whatever that breaks things like URLs.
This here would break if it was just a few chars longer.
> Could not make out the PPC part no., was it that 404 (420?) or
> something like that from IBM? I considered it at some point some
> 15 or 20 years ago and got frightened by its errata sheet, was
> clearly half baked at best.
The chip in the photo reads PPC405 in the small print.
> Which coolrunner did you use, the old Philips one or the Xilinx
> version (I have used both, even wrote my own logic compiler for
> the Philips one some 20-odd years ago).
The Coolrunner below/left of the PPC is XILINX.
I still use Coolrunners 2c64 or 128 as garbage collectors.
> I remember that, but I am pretty sure the PPC was exactly that
> half-baked IBM core I remember, not Motorola. Motorola did
> some really good 603e spinoffs, their failure was a 7500 or something
> core (could be hung by user level code so that only hard reset
> would have an effect....).
Reminds me at the never ending instructions in the 68040/50?
that could produce exceptions in a circular way, shortly
b4 Moto gave up. Oh so wonderful stuff like double-memory-
indirect deferred addressing. Who says x86 is complicated?
Gerhard.
Reply by Lasse Langwadt Christensen●June 24, 20222022-06-24
fredag den 24. juni 2022 kl. 19.48.18 UTC+2 skrev Dimiter Popoff:
> On 6/24/2022 20:31, Lasse Langwadt Christensen wrote:
> > fredag den 24. juni 2022 kl. 18.50.35 UTC+2 skrev Dimiter Popoff:
> >> On 6/23/2022 22:35, John Larkin wrote:
> >>> On Thu, 23 Jun 2022 22:05:24 +0300, Dimiter_Popoff <d...@tgi-sci.com>
> >>> wrote:
> >>>
> >>>> On 6/23/2022 19:25, jla...@highlandsniptechnology.com wrote:
> >>>>> On Thu, 23 Jun 2022 12:07:31 -0400, bitrex <us...@example.net> wrote:
> >>>>>
> >>>>>> On 6/22/2022 9:09 PM, John Larkin wrote:
> >>>>>>> On Wed, 22 Jun 2022 20:27:08 -0400, bitrex <us...@example.net> wrote:
> >>>>>>>
> >>>>>>>> On 6/22/2022 8:20 PM, John Larkin wrote:
> >>>>>>>>>
> >>>>>>>>> Got my boards today. We always ask for a "solder sample" to admire;
> >>>>>>>>> it's not guaranteed to be functional. This one has some ugly traces on
> >>>>>>>>> the bottom. Maybe they did that on purpose.
> >>>>>>>>>
> >>>>>>>>> https://www.dropbox.com/sh/ias1388kbfrednn/AACsZ0p4dN4ez90yLFVCasl6a?dl=0
> >>>>>>>>>
> >>>>>>>>> The plugin MicroZed board does the hard work.
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> Looks like a cool board, the availability doesn't look so cool tho:
> >>>>>>>>
> >>>>>>>> <https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/microzed/>
> >>>>>>>
> >>>>>>> We have a bunch in stock. Presumably this crunch will be over some
> >>>>>>> day.
> >>>>>>>
> >>>>>>
> >>>>>> I've tended to rely on the microchip 8-bitters a lot in my work, and
> >>>>>> they've been really thin on the ground lately, particularly the parts
> >>>>>> with a luxurious 8k of Flash or more.
> >>>>>>
> >>>>>> Parts with 1k are readily available though which encourages creativity,
> >>>>>> sometimes by offloading a few functions to a SPLC or using two instead
> >>>>>> of one I've got my relatively low-volume jobs done to my client's
> >>>>>> satisfaction.
> >>>>>>
> >>>>>
> >>>>> We are considering a soft-core RiscV inside an efinix FPGA, sort of a
> >>>>> poor-persons Zynq. Lots of applications need a cpu, but not much.
> >>>>>
> >>>>>
> >>>>
> >>>> Isn't there a soft power architecture core meanwhile? Some time ago
> >>>> (a year or two) IBM made it "open". If available it might be a better
> >>>> option than risk-v or arm.
> >>>
> >>> efinix has a risc-v block available.
> >>>
> >>> https://www.efinixinc.com/products-riscv.html
> >>>
> >>> A modest program could run in on-chip sram.
> >> I see, having the core on chip makes things different.
> >>>
> >>> I suspect that risc-v has a big future. It's free.
> >>>
> >> Perhaps so, but Power is also free now. I have only looked at
> >> risc-v docs - to begin with it is little-endian
> >
> > so is all the other major platforms
> >
> >> (a more serious > drawback than people have been made to think for decades though not a show-stopper).
> >
> > what serious drawbacks?
> Do you have enough experience at low level programming to be able
> to judge that.
since you are not coming up with any examples I'll just assume there isn't any ....
Reply by Dimiter_Popoff●June 24, 20222022-06-24
On 6/24/2022 20:31, Lasse Langwadt Christensen wrote:
> fredag den 24. juni 2022 kl. 18.50.35 UTC+2 skrev Dimiter Popoff:
>> On 6/23/2022 22:35, John Larkin wrote:
>>> On Thu, 23 Jun 2022 22:05:24 +0300, Dimiter_Popoff <d...@tgi-sci.com>
>>> wrote:
>>>
>>>> On 6/23/2022 19:25, jla...@highlandsniptechnology.com wrote:
>>>>> On Thu, 23 Jun 2022 12:07:31 -0400, bitrex <us...@example.net> wrote:
>>>>>
>>>>>> On 6/22/2022 9:09 PM, John Larkin wrote:
>>>>>>> On Wed, 22 Jun 2022 20:27:08 -0400, bitrex <us...@example.net> wrote:
>>>>>>>
>>>>>>>> On 6/22/2022 8:20 PM, John Larkin wrote:
>>>>>>>>>
>>>>>>>>> Got my boards today. We always ask for a "solder sample" to admire;
>>>>>>>>> it's not guaranteed to be functional. This one has some ugly traces on
>>>>>>>>> the bottom. Maybe they did that on purpose.
>>>>>>>>>
>>>>>>>>> https://www.dropbox.com/sh/ias1388kbfrednn/AACsZ0p4dN4ez90yLFVCasl6a?dl=0
>>>>>>>>>
>>>>>>>>> The plugin MicroZed board does the hard work.
>>>>>>>>>
>>>>>>>>
>>>>>>>> Looks like a cool board, the availability doesn't look so cool tho:
>>>>>>>>
>>>>>>>> <https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/microzed/>
>>>>>>>
>>>>>>> We have a bunch in stock. Presumably this crunch will be over some
>>>>>>> day.
>>>>>>>
>>>>>>
>>>>>> I've tended to rely on the microchip 8-bitters a lot in my work, and
>>>>>> they've been really thin on the ground lately, particularly the parts
>>>>>> with a luxurious 8k of Flash or more.
>>>>>>
>>>>>> Parts with 1k are readily available though which encourages creativity,
>>>>>> sometimes by offloading a few functions to a SPLC or using two instead
>>>>>> of one I've got my relatively low-volume jobs done to my client's
>>>>>> satisfaction.
>>>>>>
>>>>>
>>>>> We are considering a soft-core RiscV inside an efinix FPGA, sort of a
>>>>> poor-persons Zynq. Lots of applications need a cpu, but not much.
>>>>>
>>>>>
>>>>
>>>> Isn't there a soft power architecture core meanwhile? Some time ago
>>>> (a year or two) IBM made it "open". If available it might be a better
>>>> option than risk-v or arm.
>>>
>>> efinix has a risc-v block available.
>>>
>>> https://www.efinixinc.com/products-riscv.html
>>>
>>> A modest program could run in on-chip sram.
>> I see, having the core on chip makes things different.
>>>
>>> I suspect that risc-v has a big future. It's free.
>>>
>> Perhaps so, but Power is also free now. I have only looked at
>> risc-v docs - to begin with it is little-endian
>
> so is all the other major platforms
>
>> (a more serious > drawback than people have been made to think for decades though not a show-stopper).
>
> what serious drawbacks?
Do you have enough experience at low level programming to be able
to judge that.
Reply by Lasse Langwadt Christensen●June 24, 20222022-06-24
fredag den 24. juni 2022 kl. 18.50.35 UTC+2 skrev Dimiter Popoff:
> On 6/23/2022 22:35, John Larkin wrote:
> > On Thu, 23 Jun 2022 22:05:24 +0300, Dimiter_Popoff <d...@tgi-sci.com>
> > wrote:
> >
> >> On 6/23/2022 19:25, jla...@highlandsniptechnology.com wrote:
> >>> On Thu, 23 Jun 2022 12:07:31 -0400, bitrex <us...@example.net> wrote:
> >>>
> >>>> On 6/22/2022 9:09 PM, John Larkin wrote:
> >>>>> On Wed, 22 Jun 2022 20:27:08 -0400, bitrex <us...@example.net> wrote:
> >>>>>
> >>>>>> On 6/22/2022 8:20 PM, John Larkin wrote:
> >>>>>>>
> >>>>>>> Got my boards today. We always ask for a "solder sample" to admire;
> >>>>>>> it's not guaranteed to be functional. This one has some ugly traces on
> >>>>>>> the bottom. Maybe they did that on purpose.
> >>>>>>>
> >>>>>>> https://www.dropbox.com/sh/ias1388kbfrednn/AACsZ0p4dN4ez90yLFVCasl6a?dl=0
> >>>>>>>
> >>>>>>> The plugin MicroZed board does the hard work.
> >>>>>>>
> >>>>>>
> >>>>>> Looks like a cool board, the availability doesn't look so cool tho:
> >>>>>>
> >>>>>> <https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/microzed/>
> >>>>>
> >>>>> We have a bunch in stock. Presumably this crunch will be over some
> >>>>> day.
> >>>>>
> >>>>
> >>>> I've tended to rely on the microchip 8-bitters a lot in my work, and
> >>>> they've been really thin on the ground lately, particularly the parts
> >>>> with a luxurious 8k of Flash or more.
> >>>>
> >>>> Parts with 1k are readily available though which encourages creativity,
> >>>> sometimes by offloading a few functions to a SPLC or using two instead
> >>>> of one I've got my relatively low-volume jobs done to my client's
> >>>> satisfaction.
> >>>>
> >>>
> >>> We are considering a soft-core RiscV inside an efinix FPGA, sort of a
> >>> poor-persons Zynq. Lots of applications need a cpu, but not much.
> >>>
> >>>
> >>
> >> Isn't there a soft power architecture core meanwhile? Some time ago
> >> (a year or two) IBM made it "open". If available it might be a better
> >> option than risk-v or arm.
> >
> > efinix has a risc-v block available.
> >
> > https://www.efinixinc.com/products-riscv.html
> >
> > A modest program could run in on-chip sram.
> I see, having the core on chip makes things different.
> >
> > I suspect that risc-v has a big future. It's free.
> >
> Perhaps so, but Power is also free now. I have only looked at
> risc-v docs - to begin with it is little-endian
so is all the other major platforms
> (a more serious > drawback than people have been made to think for decades though not a show-stopper).
what serious drawbacks?
Reply by Dimiter_Popoff●June 24, 20222022-06-24
On 6/23/2022 22:35, John Larkin wrote:
> On Thu, 23 Jun 2022 22:05:24 +0300, Dimiter_Popoff <dp@tgi-sci.com>
> wrote:
>
>> On 6/23/2022 19:25, jlarkin@highlandsniptechnology.com wrote:
>>> On Thu, 23 Jun 2022 12:07:31 -0400, bitrex <user@example.net> wrote:
>>>
>>>> On 6/22/2022 9:09 PM, John Larkin wrote:
>>>>> On Wed, 22 Jun 2022 20:27:08 -0400, bitrex <user@example.net> wrote:
>>>>>
>>>>>> On 6/22/2022 8:20 PM, John Larkin wrote:
>>>>>>>
>>>>>>> Got my boards today. We always ask for a "solder sample" to admire;
>>>>>>> it's not guaranteed to be functional. This one has some ugly traces on
>>>>>>> the bottom. Maybe they did that on purpose.
>>>>>>>
>>>>>>> https://www.dropbox.com/sh/ias1388kbfrednn/AACsZ0p4dN4ez90yLFVCasl6a?dl=0
>>>>>>>
>>>>>>> The plugin MicroZed board does the hard work.
>>>>>>>
>>>>>>
>>>>>> Looks like a cool board, the availability doesn't look so cool tho:
>>>>>>
>>>>>> <https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/microzed/>
>>>>>
>>>>> We have a bunch in stock. Presumably this crunch will be over some
>>>>> day.
>>>>>
>>>>
>>>> I've tended to rely on the microchip 8-bitters a lot in my work, and
>>>> they've been really thin on the ground lately, particularly the parts
>>>> with a luxurious 8k of Flash or more.
>>>>
>>>> Parts with 1k are readily available though which encourages creativity,
>>>> sometimes by offloading a few functions to a SPLC or using two instead
>>>> of one I've got my relatively low-volume jobs done to my client's
>>>> satisfaction.
>>>>
>>>
>>> We are considering a soft-core RiscV inside an efinix FPGA, sort of a
>>> poor-persons Zynq. Lots of applications need a cpu, but not much.
>>>
>>>
>>
>> Isn't there a soft power architecture core meanwhile? Some time ago
>> (a year or two) IBM made it "open". If available it might be a better
>> option than risk-v or arm.
>
> efinix has a risc-v block available.
>
> https://www.efinixinc.com/products-riscv.html
>
> A modest program could run in on-chip sram.
I see, having the core on chip makes things different.
>
> I suspect that risc-v has a big future. It's free.
>
Perhaps so, but Power is also free now. I have only looked at
risc-v docs - to begin with it is little-endian (a more serious
drawback than people have been made to think for decades though
not a show-stopper). I have been living with power for well over
20 years now, have had no buying issues (knock on wood) and have
yet to identify any shortcoming in the architecture. Those who
did it at IBM knew damn well what they were doing.
Reply by Dimiter_Popoff●June 24, 20222022-06-24
On 6/24/2022 1:24, Gerhard Hoffmann wrote:
>
> Am 23.06.22 um 21:05 schrieb Dimiter_Popoff:
> > On 6/23/2022 19:25, jlarkin@highlandsniptechnology.com wrote:
>
> >>
> >> We are considering a soft-core RiscV inside an efinix FPGA, sort of a
> >> poor-persons Zynq. Lots of applications need a cpu, but not much.
> >>
> >>
> >
> > Isn't there a soft power architecture core meanwhile? Some time ago
> > (a year or two) IBM made it "open". If available it might be a better
> > option than risk-v or arm.
> >
>
>
> Methinks Power PC is to fat to do as a soft core.
Perhaps so, though it would be nice to have a 603e. Can't see
why risc-v would be much smaller, some of the small ARMs certainly
would be smaller. But I am not (yet) much of an fpga person so
I can't really judge what is a practical size.
>
> I already had the pleasure with Power PC in a previous life.
> A Pipeline pig with 1024 ultrasonics channels and a PPC for
> each 16 or 32, don't remember. Luckily, I was responsible only
> for the Virtex FPGA nd the Coolrunner; the software guy nearly
> shot himself >
> <
> https://www.flickr.com/photos/137684711@N07/52167372262/in/dateposted-public/
> >
Could not make out the PPC part no., was it that 404 (420?) or
something like that from IBM? I considered it at some point some
15 or 20 years ago and got frightened by its errata sheet, was
clearly half baked at best.
Which coolrunner did you use, the old Philips one or the Xilinx
version (I have used both, even wrote my own logic compiler for
the Philips one some 20-odd years ago).
>
> Xilinx had a fixed core PPC in one of their Virtexes. I heard
> Peter Alfke complain that it was wrong to license it from
> Motorola instead of IBM. It seems, the price was lower, but
> support was nonexistent.
I remember that, but I am pretty sure the PPC was exactly that
half-baked IBM core I remember, not Motorola. Motorola did
some really good 603e spinoffs, their failure was a 7500 or something
core (could be hung by user level code so that only hard reset
would have an effect....).
Now they (well, NXP) have that 5500/6500 cores (64 bit beasts) waiting
in my drawer to get around to them, hopefully they are as good as they
look so far to me.
>
> Cheers, also to Peter if he's still alive!
He was a really fine guy. Went out of his way to find some info
for me at some point, a really knowledgeable guy. Someone else
already mentioned that he died.
On Thu, 23 Jun 2022 16:40:59 -0700 (PDT), "ke...@kjwdesigns.com"
<keith@kjwdesigns.com> wrote:
>On Thursday, 23 June 2022 at 15:24:53 UTC-7, Gerhard Hoffmann wrote:
>...
>> <
>> https://www.flickr.com/photos/137684711@N07/52167372262/in/dateposted-public/
>> >
>>
>> Xilinx had a fixed core PPC in one of their Virtexes. I heard
>> Peter Alfke complain that it was wrong to license it from
>> Motorola instead of IBM. It seems, the price was lower, but
>> support was nonexistent.
>>
>> Cheers, also to Peter if he's still alive!
>>
>> Gerhard
>
>Sorry to say he died over 10 years ago.
>
>https://www.eetimes.com/peter-alfke-remembered-1931-2011/
>
>kw
Peter was cool. One day at the Foothill Flea Market I had my head down
inside a big box of books and another head appeared. It was Peter.
He was a real FPGA missionary, and had fun doing it.
--
If a man will begin with certainties, he shall end with doubts,
but if he will be content to begin with doubts he shall end in certainties.
Francis Bacon