> On Tue, 28 Dec 2021 21:57:18 -0800, Robert Baer
> <robertbaer@localnet.com> wrote:
>
>> John Larkin wrote:
>>> We finally got a batch of boards.
>>>
>>> https://www.dropbox.com/s/rul9yep9ys0snyo/T502A_PCB.jpg?raw=1
>>>
>>> None of the board houses minded making the three v-score breakaways.
>>>
>>> Tiny, in this case some 50 mil high, reference designators don't seem
>>> to be a problem these days. These look ink-jet printed to me.
>>>
>>> My test capacitor is upper-right, layer 1 to the layer 2 ground plane.
>>> If the board was fabbed exactly to the fab notes, Er works out be
>>> 4.63. Saturn assumes 4.6 for FR4. The TDR test trace is close to 50
>>> ohms.
>>>
>>> Gotta build some and see if they work.
>>>
>> Looks like you added a pad under U11 and U17 for heatsinking, then
>> some PTH to enhance that function.
>
> Yes. U11, U12, and U15 all dissipate enough power to get hot, so they
> are heat sunk to the internal power planes through vias. Their gains
> and prop delays change with temperature, so we want to minimize heat
> rise.
>
> U15 is a an HMC659, a $300, 15 GHz distributed amp. Its recommended
> bias is 8 volts and 300 mA, which is a lot of power for a tiny chip.
> It needs that to swing a lot of sinewave RF output. I'm using it to
> make short negative 6-volt pulses, so I bias it at 9 volts and 45 mA,
> about 400 mW.
>
> The Saturn software computes via properties, including inductance and
> resistance. The electrical resistance value can be used to estimate
> thermal resistance.
>
> Regulators U3 and U8 and U9 also have thermal vias, which makes them a
> bit more stable. This is a 6-layer board with four copper planes, so
> heat spreading is pretty good.
>
> My production people hate those vias. They think they steal their
> precious solder paste. I hope they do.
* They will, if the via/drill size is small enough; do not know how big
the hole can be before the solder paste will not fill it (size threshold).
I know hole drill size #32 does not get filled without manual help.
However, it seems to me more holes per square inch would give better
thermal conductivity if enough copper connectivity between them (that
argues/limits holes per square inch).
Gotta be a way to calculate this for optimum drill size and holes per
square inch. Better add in copper thickness.
On Tue, 28 Dec 2021 21:57:18 -0800, Robert Baer
<robertbaer@localnet.com> wrote:
>John Larkin wrote:
>> We finally got a batch of boards.
>>
>> https://www.dropbox.com/s/rul9yep9ys0snyo/T502A_PCB.jpg?raw=1
>>
>> None of the board houses minded making the three v-score breakaways.
>>
>> Tiny, in this case some 50 mil high, reference designators don't seem
>> to be a problem these days. These look ink-jet printed to me.
>>
>> My test capacitor is upper-right, layer 1 to the layer 2 ground plane.
>> If the board was fabbed exactly to the fab notes, Er works out be
>> 4.63. Saturn assumes 4.6 for FR4. The TDR test trace is close to 50
>> ohms.
>>
>> Gotta build some and see if they work.
>>
> Looks like you added a pad under U11 and U17 for heatsinking, then
>some PTH to enhance that function.
Yes. U11, U12, and U15 all dissipate enough power to get hot, so they
are heat sunk to the internal power planes through vias. Their gains
and prop delays change with temperature, so we want to minimize heat
rise.
U15 is a an HMC659, a $300, 15 GHz distributed amp. Its recommended
bias is 8 volts and 300 mA, which is a lot of power for a tiny chip.
It needs that to swing a lot of sinewave RF output. I'm using it to
make short negative 6-volt pulses, so I bias it at 9 volts and 45 mA,
about 400 mW.
The Saturn software computes via properties, including inductance and
resistance. The electrical resistance value can be used to estimate
thermal resistance.
Regulators U3 and U8 and U9 also have thermal vias, which makes them a
bit more stable. This is a 6-layer board with four copper planes, so
heat spreading is pretty good.
My production people hate those vias. They think they steal their
precious solder paste. I hope they do.
--
I yam what I yam - Popeye
Reply by Robert Baer●December 29, 20212021-12-29
John Larkin wrote:
> We finally got a batch of boards.
>
> https://www.dropbox.com/s/rul9yep9ys0snyo/T502A_PCB.jpg?raw=1
>
> None of the board houses minded making the three v-score breakaways.
>
> Tiny, in this case some 50 mil high, reference designators don't seem
> to be a problem these days. These look ink-jet printed to me.
>
> My test capacitor is upper-right, layer 1 to the layer 2 ground plane.
> If the board was fabbed exactly to the fab notes, Er works out be
> 4.63. Saturn assumes 4.6 for FR4. The TDR test trace is close to 50
> ohms.
>
> Gotta build some and see if they work.
>
Looks like you added a pad under U11 and U17 for heatsinking, then
some PTH to enhance that function.
--
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
Reply by John Larkin●December 28, 20212021-12-28
We finally got a batch of boards.
https://www.dropbox.com/s/rul9yep9ys0snyo/T502A_PCB.jpg?raw=1
None of the board houses minded making the three v-score breakaways.
Tiny, in this case some 50 mil high, reference designators don't seem
to be a problem these days. These look ink-jet printed to me.
My test capacitor is upper-right, layer 1 to the layer 2 ground plane.
If the board was fabbed exactly to the fab notes, Er works out be
4.63. Saturn assumes 4.6 for FR4. The TDR test trace is close to 50
ohms.
Gotta build some and see if they work.
--
If a man will begin with certainties, he shall end with doubts,
but if he will be content to begin with doubts he shall end in certainties.
Francis Bacon