On Thu, 2 Apr 2020 06:55:41 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
>Am 02.04.20 um 06:40 schrieb jlarkin@highlandsniptechnology.com:
> cheers, Gerhard
>>
>> What's wrong with a comparator with hysteresis? Why do all that
>> agc/log stuff?
>>
>> Front-end options can include attenuation and lowpass filtering and
>> ac/dc coupling.
>
>The Stanford and the HP5370 use comparators, not agc/log.
>They rely on exact trigger levels. You can even measure rise/fall time.
>
>The HP type number was wrong.
We used to use a bunch of 5370s here. It had 20 ps single-shot
resolution and 30 ps RMS jitter for time measurements. The user
interface was wonderful. Somehow it did all its math with a single
8-bit 6800 (not 68K) CPU, which took 2 us to execute a no-op
instruction and had no multiply.
They eventually died, so we use a Keysight box with about the same
specs, 20 ps LSB and better jitter, 15 maybe. But a brain-damaged user
interface.
The 5370 has a custom IC as the trigger discriminator, and if it gets
zapped it can't be replaced, I think.
Does anybody use the SRS box?
--
John Larkin Highland Technology, Inc
Science teaches us to doubt.
Claude Bernard
Reply by Gerhard Hoffmann●April 2, 20202020-04-02
Am 02.04.20 um 13:24 schrieb Phil Hobbs:
> Clean limiting amps help a lot in messier situations, e.g. radio links
> with fading. AGC is bad news in a counter because it's slow, so that
> fast fading causes artifacts.
>
> Cascaded limiters do give a logarithmic response, but that's not the
> essential point--clean limiting is the key.
>
On 2020-04-02 00:40, jlarkin@highlandsniptechnology.com wrote:
> On Thu, 2 Apr 2020 06:18:47 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
> wrote:
>
>> Am 02.04.20 um 04:08 schrieb Clifford Heath:
>>
>>> The guy who designed these counter modules went through lots of
>>> iterations to come up with his dual-gate MOSFET setup that still doesn't
>>> work very well. I found the Chinese forum where he posted (and got
>>> feedback on) his earlier versions, and read much of it using Google
>>> Translate.
>>>
>>> Someone should clone the design but replace the input with a log-amp...
>>> What's the best chip for that these days?
>>
>> Get the service manual of the Stanford SR620 or HP 5473. (not log)
>>
>> cheers, Gerhard
>
> What's wrong with a comparator with hysteresis? Why do all that
> agc/log stuff?
>
> Front-end options can include attenuation and lowpass filtering and
> ac/dc coupling.
Clean limiting amps help a lot in messier situations, e.g. radio links
with fading. AGC is bad news in a counter because it's slow, so that
fast fading causes artifacts.
Cascaded limiters do give a logarithmic response, but that's not the
essential point--clean limiting is the key.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.nethttp://hobbs-eo.com
Reply by Clifford Heath●April 2, 20202020-04-02
On 2/4/20 3:55 pm, Gerhard Hoffmann wrote:
> Am 02.04.20 um 06:40 schrieb jlarkin@highlandsniptechnology.com:
> cheers, Gerhard
>>
>> What's wrong with a comparator with hysteresis? Why do all that
>> agc/log stuff?
>>
>> Front-end options can include attenuation and lowpass filtering and
>> ac/dc coupling.
>
> The Stanford and the HP5370 use comparators, not agc/log.
> They rely on exact trigger levels. You can even measure rise/fall time.
I found the SR620 schematics. After some FET+BJT buffering, the signal
goes to a AD96685 comparator (ECL differential output), chosen for its
low delay dispersion, which the data sheet defines as "a measure of the
difference in propagation delay under differing overdrive conditions."
Only the tiniest amount of hysteresis though: 1/50th of the ECL swing
(is that 10mV?), with an extra 1pF (about 200R, tau~=10ns). Hysteresis
is applied from the negative output to the negative input, so it doesn't
feed into the signal path.
It's a nice thing. Thanks for mentioning it Gerhard.
Clifford Heath.
Reply by Clifford Heath●April 2, 20202020-04-02
On 2/4/20 3:18 pm, Gerhard Hoffmann wrote:
> Am 02.04.20 um 04:08 schrieb Clifford Heath:
>
>> The guy who designed these counter modules went through lots of
>> iterations to come up with his dual-gate MOSFET setup that still
>> doesn't work very well. I found the Chinese forum where he posted (and
>> got feedback on) his earlier versions, and read much of it using
>> Google Translate.
>>
>> Someone should clone the design but replace the input with a
>> log-amp... What's the best chip for that these days?
>
> Get the service manual of the Stanford SR620 or HP 5473. (not log)
It was the HP5386 I was looking at. I'll see if I can find the section
again.
The comparator approach is fine until you have a mix of signals.
What should a freq counter do if you have a strong fundamental but a
spurious signal introduces an extra zero-crossing every 3rd or 4th cycle?
The HP5386 just seemed rock-solid, where the Chinese hobby clone tended
to be just vague. Well duh... but looking at its input schematic I
couldn't really see why it wasn't better.
Clifford Heath
Reply by whit3rd●April 2, 20202020-04-02
On Wednesday, April 1, 2020 at 9:40:38 PM UTC-7, jla...@highlandsniptechnology.com wrote:
> On Thu, 2 Apr 2020 06:18:47 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
> wrote:
>
> >Am 02.04.20 um 04:08 schrieb Clifford Heath:
> >> Someone should clone the design but replace the input with a log-amp...
> >> What's the best chip for that these days?
> >Get the service manual of the Stanford SR620 or HP 5473. (not log)
> What's wrong with a comparator with hysteresis? Why do all that
> agc/log stuff?
So it has good performance with high or low impedance inputs, with
or without attenuation, tolerates a variety of buffers/filters/amplifiers
if you want to process the input.
Comparators have high output but also limited slew rates make 'em
a pain at 250 MHz.
> Front-end options can include attenuation and lowpass filtering and
> ac/dc coupling.
Yep, you can build a front-end for almost anything. For taking Hsync
from a video signal, I made a self-biased one-transistor amp that
forced the duty cycle but let the input DC level float (because that's
useful for composite video). It woudn't be optimal, however, for
general purpose use (the forced duty cycle wasn't 50% and would
have caused unnecessary jitter).
Built-to-order front ends just don't belong inside the box, where switches
and pots are a signal-path nightmare when they get dirty.
Reply by Gerhard Hoffmann●April 2, 20202020-04-02
Am 02.04.20 um 06:40 schrieb jlarkin@highlandsniptechnology.com:
cheers, Gerhard
>
> What's wrong with a comparator with hysteresis? Why do all that
> agc/log stuff?
>
> Front-end options can include attenuation and lowpass filtering and
> ac/dc coupling.
The Stanford and the HP5370 use comparators, not agc/log.
They rely on exact trigger levels. You can even measure rise/fall time.
The HP type number was wrong.
Reply by ●April 2, 20202020-04-02
On Thu, 2 Apr 2020 06:18:47 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
>Am 02.04.20 um 04:08 schrieb Clifford Heath:
>
>> The guy who designed these counter modules went through lots of
>> iterations to come up with his dual-gate MOSFET setup that still doesn't
>> work very well. I found the Chinese forum where he posted (and got
>> feedback on) his earlier versions, and read much of it using Google
>> Translate.
>>
>> Someone should clone the design but replace the input with a log-amp...
>> What's the best chip for that these days?
>
>Get the service manual of the Stanford SR620 or HP 5473. (not log)
>
>cheers, Gerhard
What's wrong with a comparator with hysteresis? Why do all that
agc/log stuff?
Front-end options can include attenuation and lowpass filtering and
ac/dc coupling.
--
John Larkin Highland Technology, Inc
Science teaches us to doubt.
Claude Bernard
Reply by Gerhard Hoffmann●April 2, 20202020-04-02
Am 02.04.20 um 04:08 schrieb Clifford Heath:
> The guy who designed these counter modules went through lots of
> iterations to come up with his dual-gate MOSFET setup that still doesn't
> work very well. I found the Chinese forum where he posted (and got
> feedback on) his earlier versions, and read much of it using Google
> Translate.
>
> Someone should clone the design but replace the input with a log-amp...
> What's the best chip for that these days?
Get the service manual of the Stanford SR620 or HP 5473. (not log)
cheers, Gerhard
Reply by Clifford Heath●April 1, 20202020-04-01
On 2/4/20 3:35 am, Phil Hobbs wrote:
> On 2020-03-31 20:43, Clifford Heath wrote:
>> On 1/4/20 2:51 am, jlarkin@highlandsniptechnology.com wrote:
>>> On Tue, 31 Mar 2020 07:04:50 -0700 (PDT), George Herold
>>> <ggherold@gmail.com> wrote:
>>>>> The B+K stuff is usually pretty good.
>>>> At PPoE we ditched a (cheaper) B&K counter. The problem for us was
>>>> that it didn't actually give the number of pulses, (or rising edges)
>>>> in the time window. But it did some sort of unknown averaging, so that
>>>> though the average number was correct, there was not enough scatter
>>>> in the
>>>> count number. (This was for a random source... counting pmt pulses.)
>>>>
>>>> For what you want it may be fine.
>>>
>>> "Frequency" counters are often AC-coupled with a zero-volts trigger
>>> threshold. They count sine waves fine but are terrible with pulses.
>>> For pulses, you need DC coupling and a settable trigger level.
>>
>> I investigated the input stages of a good HP frequency counter,
>> because the cheap one I have is not very reliable, and was quite
>> surprised what I saw.
>>
>> There is a huge amount of attenuation first (presumably mostly for
>> protection) followed by lots of amplification - three stages of
>> differential ECL or something, I think.
>>
>> I guess the attenuation ensures that the first amplification stage
>> stays linear, and the amp provides progressive compression ala a
>> log-amp, which (it seems to me) should be much better than just
>> zero-crossing detection. I couldn't see any sign of AGC leading up to
>> the (clamped) output.
>>
>> Does that make sense?
>>
>> Clifford Heath.
>
> Makes perfect sense. The log amp approach prevents the threshold from
> changing on the scale of the AGC bandwidth--it responds cycle-by-cycle.
Oooh, way to go, I understood something tricky, the first time, without
bumping my head on it :)
The guy who designed these counter modules went through lots of
iterations to come up with his dual-gate MOSFET setup that still doesn't
work very well. I found the Chinese forum where he posted (and got
feedback on) his earlier versions, and read much of it using Google
Translate.
Someone should clone the design but replace the input with a log-amp...
What's the best chip for that these days?
Clifford Heath.