On Monday, September 23, 2019 at 10:07:10 AM UTC-4, Joerg wrote:
> On 2019-09-22 18:36, Gerhard Hoffmann wrote:
> > Am 22.09.19 um 16:21 schrieb Joerg:
> >> On 2019-09-21 13:53, Gerhard Hoffmann wrote:
> >
> >> Old TTL didn't pull very high. 3.5V to 4V in some cases so noise
> >> immunity was indeed worse, until CMOS came. That made things
> >> cumbersome because you could not use OC structures to operate it from
> >> external.
> >
> > TTL levels have nothing to do with 5V. That is just the supply voltage.
> > The switching threshold is somewhere near 1V8, anything below 0V6 is
> > definitely low and anything above 2V4 is definitely high.
> >
>
> And sometimes the drive signal didn't quite get there. Or not all the
> time. The threshold in TTL is lower though, but occasionally it wasn't
> low enough. Unless you used 244 bus drivers this stuff just didn't have
> any oomph.
>
>
> > CMOS has its threshold at 1/2 VCC, but the historic importance of
> > TTL required the extraneous 74HCT family with the lower TTL input
> > threshold, implemented by playing games with the width/length ratio
> > of the FETs.
> >
>
> That is one reason I was never much of a fan of HCT. In my youth I built
> a lot of circuits with CD4000 logic because it didn't have such
> problems. It had other problems but the main upside was a vastly lower
> power consumption.
>
> >
> >>> And no, modern digital design has nothing to do with deploying 74xxx.
> >>> You formulate your system in VHDL, Verilog or Matlab and that's it.
> >>> Nobody cares about flipflops, let alone their reset pin polarity.
> >>>
> >>
> >> Nobody? Really nobody? Way north in France, in the province of the
> >> Gauloises ...
> >
> > Deploying a few gates is not digital design.
> >
>
> That part fulfills logic funtions. If this and that happens at the same
> time tug on an alert rail, otherwise not. Preferably while consuming
> less than 1uA. What's not digital about that?
>
>
> >> For example, right now I have to design a circuit for a device that
> >> replaces a uC function because the uC can't be trusted to do the job
> >> reliably enough. I think it could be made reliable but a client's wish
> >> is a client's wish. It'll need several 74LVC chips.
> >
> > Consultant's creed:
> > It's our policy to give the customer what he wants.
> > That is very strong medicine, and usually only required once.
> >
>
> :-)
>
> Once is the goal, of course. After that I (and the client) expect this
> to run for the next few decades.
Whoosh!
--
Rick C.
+ Get 2,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
Reply by Joerg●September 23, 20192019-09-23
On 2019-09-22 18:36, Gerhard Hoffmann wrote:
> Am 22.09.19 um 16:21 schrieb Joerg:
>> On 2019-09-21 13:53, Gerhard Hoffmann wrote:
>
>> Old TTL didn't pull very high. 3.5V to 4V in some cases so noise
>> immunity was indeed worse, until CMOS came. That made things
>> cumbersome because you could not use OC structures to operate it from
>> external.
>
> TTL levels have nothing to do with 5V. That is just the supply voltage.
> The switching threshold is somewhere near 1V8, anything below 0V6 is
> definitely low and anything above 2V4 is definitely high.
>
And sometimes the drive signal didn't quite get there. Or not all the
time. The threshold in TTL is lower though, but occasionally it wasn't
low enough. Unless you used 244 bus drivers this stuff just didn't have
any oomph.
> CMOS has its threshold at 1/2 VCC, but the historic importance of
> TTL required the extraneous 74HCT family with the lower TTL input
> threshold, implemented by playing games with the width/length ratio
> of the FETs.
>
That is one reason I was never much of a fan of HCT. In my youth I built
a lot of circuits with CD4000 logic because it didn't have such
problems. It had other problems but the main upside was a vastly lower
power consumption.
>
>>> And no, modern digital design has nothing to do with deploying 74xxx.
>>> You formulate your system in VHDL, Verilog or Matlab and that's it.
>>> Nobody cares about flipflops, let alone their reset pin polarity.
>>>
>>
>> Nobody? Really nobody? Way north in France, in the province of the
>> Gauloises ...
>
> Deploying a few gates is not digital design.
>
That part fulfills logic funtions. If this and that happens at the same
time tug on an alert rail, otherwise not. Preferably while consuming
less than 1uA. What's not digital about that?
>> For example, right now I have to design a circuit for a device that
>> replaces a uC function because the uC can't be trusted to do the job
>> reliably enough. I think it could be made reliable but a client's wish
>> is a client's wish. It'll need several 74LVC chips.
>
> Consultant's creed:
> It's our policy to give the customer what he wants.
> That is very strong medicine, and usually only required once.
>
:-)
Once is the goal, of course. After that I (and the client) expect this
to run for the next few decades.
--
Regards, Joerg
http://www.analogconsultants.com/
Reply by ●September 22, 20192019-09-22
On Mon, 23 Sep 2019 03:36:53 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
>Am 22.09.19 um 16:21 schrieb Joerg:
>> On 2019-09-21 13:53, Gerhard Hoffmann wrote:
>
>> Old TTL didn't pull very high. 3.5V to 4V in some cases so noise
>> immunity was indeed worse, until CMOS came. That made things cumbersome
>> because you could not use OC structures to operate it from external.
>
>TTL levels have nothing to do with 5V. That is just the supply voltage.
>The switching threshold is somewhere near 1V8, anything below 0V6 is
>definitely low and anything above 2V4 is definitely high.
Classic TTL was about 1.2 volts threshold.
>
>CMOS has its threshold at 1/2 VCC, but the historic importance of
>TTL required the extraneous 74HCT family with the lower TTL input
>threshold, implemented by playing games with the width/length ratio
>of the FETs.
74HCT is great for receiving inputs from FPGAs at 3.3 or 2.5 volts. It
will have much less shoot-through current than HC, too.
>
>
>>> And no, modern digital design has nothing to do with deploying 74xxx.
>>> You formulate your system in VHDL, Verilog or Matlab and that's it.
>>> Nobody cares about flipflops, let alone their reset pin polarity.
>>>
>>
>> Nobody? Really nobody? Way north in France, in the province of the
>> Gauloises ...
>
>Deploying a few gates is not digital design.
>
>> For example, right now I have to design a circuit for a device that
>> replaces a uC function because the uC can't be trusted to do the job
>> reliably enough. I think it could be made reliable but a client's wish
>> is a client's wish. It'll need several 74LVC chips.
>
>Consultant's creed:
>It's our policy to give the customer what he wants.
>That is very strong medicine, and usually only required once.
>
>Gerhard
I often use Tiny dflops to resync the outputs of an FPGA to a clock.
That really cleans up the jitter that FPGAs tend to make.
Reply by Gerhard Hoffmann●September 22, 20192019-09-22
Am 22.09.19 um 16:21 schrieb Joerg:
> On 2019-09-21 13:53, Gerhard Hoffmann wrote:
> Old TTL didn't pull very high. 3.5V to 4V in some cases so noise
> immunity was indeed worse, until CMOS came. That made things cumbersome
> because you could not use OC structures to operate it from external.
TTL levels have nothing to do with 5V. That is just the supply voltage.
The switching threshold is somewhere near 1V8, anything below 0V6 is
definitely low and anything above 2V4 is definitely high.
CMOS has its threshold at 1/2 VCC, but the historic importance of
TTL required the extraneous 74HCT family with the lower TTL input
threshold, implemented by playing games with the width/length ratio
of the FETs.
>> And no, modern digital design has nothing to do with deploying 74xxx.
>> You formulate your system in VHDL, Verilog or Matlab and that's it.
>> Nobody cares about flipflops, let alone their reset pin polarity.
>>
>
> Nobody? Really nobody? Way north in France, in the province of the
> Gauloises ...
Deploying a few gates is not digital design.
> For example, right now I have to design a circuit for a device that
> replaces a uC function because the uC can't be trusted to do the job
> reliably enough. I think it could be made reliable but a client's wish
> is a client's wish. It'll need several 74LVC chips.
Consultant's creed:
It's our policy to give the customer what he wants.
That is very strong medicine, and usually only required once.
Gerhard
Reply by Joerg●September 22, 20192019-09-22
On 2019-09-21 17:03, Piotr Wyderski wrote:
> Lasse Langwadt Christensen wrote:
>
>> active low inputs is more of a practical implementation detail
>
> Is there any practical reason behind the negative logic? Or just a
> convention, as good as the opposite?
>
> Am 21.09.19 um 21:43 schrieb Joerg:
>> On 2019-09-21 11:59, Winfield Hill wrote:
>>> jlarkin@highlandsniptechnology.com wrote...
>>>>
>>>> On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com>
>>>> wrote:
>>>>
>>>>> Today I found that a simulation wasn't working right because the
>>>>> set and
>>>>> reset on the flip-flop (dflop) in LTSpice has the set and reset inputs
>>>>> active high. Yet every modern flip-flop is active low.
>>>>
>>>> Not the ECL parts, like 10EP51. Reset and clear are active high.
>>
>>
>> That's essentially RF stuff and can't easily be simulated with the
>> LTSpice behavioral models. Most of it needs to be breadboarded anyhow.
>
> That has nothing to do with RF can be perfectly simulated. It's just
> that the delay numbers are small. In a previous life, when 10kH an 100K
> were the newest thing, I have built a nice 100K library for the Simucad
> Silos simulator. That included setup/hold violations etc. I had only a
> 200 MHz scope, so I had to make sure that at least the logic was OK
> to start with.
>
"Perfectly" depends on how far one has to go with parameters such as
input capacitances. I don't think those are part of an LTSpice
simulation. Would need a full non-behavioral model.
>>> The same is true for the Ancient CD4000 series high-voltage CMOS.
>>
>> True but those are really long in the tooth. I still use them in
>> designs but figured that a modern simulator would use more modern
>> conventions.
>
> You've got that the wrong way. Low active inputs are a very retro 74xx
> thing. TTL designers speculated that it took more signal energy to
> produce a LOW input than a HIGH (correct for TTL) and that would give
> better noise immunity since most of the time these inputs do nothing.
>
Long in the tooth - retro, same thing :-)
Old TTL didn't pull very high. 3.5V to 4V in some cases so noise
immunity was indeed worse, until CMOS came. That made things cumbersome
because you could not use OC structures to operate it from external.
> That has survived for some time only for some things like 74HCT that
> allowed burning less power without requiring heavy re-thinking.
>
> And no, modern digital design has nothing to do with deploying 74xxx.
> You formulate your system in VHDL, Verilog or Matlab and that's it.
> Nobody cares about flipflops, let alone their reset pin polarity.
>
Nobody? Really nobody? Way north in France, in the province of the
Gauloises ...
For example, right now I have to design a circuit for a device that
replaces a uC function because the uC can't be trusted to do the job
reliably enough. I think it could be made reliable but a client's wish
is a client's wish. It'll need several 74LVC chips.
>
> As it happens, I needed more space in may parts store last week and I
> decided to move most things with pins, 74xx, 10K, 100K etc into
> plastic containers in the basement. I did not use them in years.
> Even the rests of glue logic in my designs go into a Coolrunner2.
>
My designs are often cost sensitive, mass production, where programmable
logic is too expensive. A 20c Coolrunner could work, 50c would not.
Storing parts farther away has health benefits. In my office the book
shelf is 5ft from my desk so I have to get up from the chair every time.
Transistors are in the room next door from my lab bench so a short walk
is required. It's healthy. I saw a neighbor yesterday who stopped
retirement for another engineering job. Despite diet cutbacks he has
developed a profound belly, not very healthy. It'll easily take more
than a year to get rid of that.
--
Regards, Joerg
http://www.analogconsultants.com/
Reply by Joerg●September 22, 20192019-09-22
On 2019-09-21 13:06, jlarkin@highlandsniptechnology.com wrote:
> On Sat, 21 Sep 2019 12:43:42 -0700, Joerg <news@analogconsultants.com>
> wrote:
>
>> On 2019-09-21 11:59, Winfield Hill wrote:
>>> jlarkin@highlandsniptechnology.com wrote...
>>>>
>>>> On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com>
>>>> wrote:
>>>>
>>>>> Today I found that a simulation wasn't working right because the set and
>>>>> reset on the flip-flop (dflop) in LTSpice has the set and reset inputs
>>>>> active high. Yet every modern flip-flop is active low.
>>>>
>>>> Not the ECL parts, like 10EP51. Reset and clear are active high.
>>
>>
>> That's essentially RF stuff and can't easily be simulated with the
>> LTSpice behavioral models. Most of it needs to be breadboarded anyhow.
>>
>>>
>>> The same is true for the Ancient CD4000 series high-voltage CMOS.
>>>
>>
>> True but those are really long in the tooth. I still use them in designs
>> but figured that a modern simulator would use more modern conventions.
>
> LT Spice is not very digital. I suspect that the library flops and
> gates are not behavioral models. More than suspect.
>
They work, at least for the most part. The unused input treatment seems
iffy but I just tie them to a logic level.
> I've had shift registers fail because I didn't set a non-zero prop
> delay.
>
> The EL and EP logic behaves very well, just about what the data sheets
> say. If you need to divide down a 600 MHz oscillator, they are the
> choice.
>
Haven't used ECL-style in more than a decade, mostly because they are
too power-hungry and power consumption matters more and mre these days.
Even on airliners they cound every drop of kerosene and thus watts in
the electronics.
> Just trekked to Safeway. It's brutally hot here, must be pushing 80F.
> How is it out there?
>
I did yard work yesterday, maybe it was in the upper 80's. Having lived
here for so long plus some Arizona exposure, I don't notice heat much.
When I ride a bicycle full bore on a 105F day people think that's crazy.
You just need enough water and an empty yoghurt beker to dump water over
the T-shirt.
--
Regards, Joerg
http://www.analogconsultants.com/
Reply by ●September 21, 20192019-09-21
On Sun, 22 Sep 2019 02:03:44 +0200, Piotr Wyderski
<peter.pan@neverland.mil> wrote:
>Lasse Langwadt Christensen wrote:
>
>> active low inputs is more of a practical implementation detail
>
>Is there any practical reason behind the negative logic? Or just a
>convention, as good as the opposite?
>
> Best regards, Piotr
>
The basic gate in early DTL and TTL logic was the NAND. It was faster
and more economical to make a master-slave flipflop with additional
NAND inputs for preset and clear; active low over-rides into the main
bistable. Hence the 7474 type flipflop.
The basic RTL gate was a NOR, so RTL flops usually had active-high
preset and clear.
TTL killed DTL killed RTL, so TTL won. CMOS inherited the TTL
conventions.
Reply by Phil Hobbs●September 21, 20192019-09-21
On 9/21/19 8:03 PM, Piotr Wyderski wrote:
> Lasse Langwadt Christensen wrote:
>
>> active low inputs is more of a practical implementation detail
>
> Is there any practical reason behind the negative logic? Or just a
> convention, as good as the opposite?
>
> Best regards, Piotr
>
>
7400 TTL convention, perhaps to reduce power dissipation due to an
infrequently-used function. 4000-series CMOS usually used active high IIRC.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.nethttp://hobbs-eo.com
Reply by Lasse Langwadt Christensen●September 21, 20192019-09-21
søndag den 22. september 2019 kl. 02.03.48 UTC+2 skrev Piotr Wyderski:
> Lasse Langwadt Christensen wrote:
>
> > active low inputs is more of a practical implementation detail
>
> Is there any practical reason behind the negative logic? Or just a
> convention, as good as the opposite?
>