Reply by John Larkin April 16, 20192019-04-16
On Tue, 16 Apr 2019 20:10:18 +0100, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>>"John Larkin" wrote in message >>news:4o07be9esulg78b2c8sd48mlogmpdf41o9@4ax.com... > > > >>I've been thinking about this > >>https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0 > >>as a roughly 500 MHz clock oscillator for some digital stuff. My FPGA >>guys claim they can accept that as an LVDS clock input. The comparator >>would be LVDS in and out, FAN1101 maybe, if it is really fast enough. > >>So I have a question for some more RF-ey guys than me. Q1 furnishes >>negative resistance so oscillation builds up, pretty much a sine wave. >>At some point R1 and D1 load the negative swing and add real loss, so >>it stabilizes at ballpark 1 volt p-p centered on ground, just enough >>net negative resistance to match the losses of the transmission line. > >>If the gain of Q1 is high (low R2) and R1 is small, it clips pretty >>hard and the sine is flattened. It's flattened identically on both the >>positive and negative peaks, which confused us for a few seconds. > >>So, given all that, how does hard clipping affect the phase noise, as >>opposed to softer limiting or, ultimately, some super linear AGC loop? >>I want a lot of swing into the comparator, 1 volt p-p maybe before its >>ESD diodes conduct, and I want the thing to oscillate reliably, which >>suggest sorta hard clipping, with some visible flattening of the sine >>wave. > >>No matter how much gain we have in Q1, and how hard we clip, the >>txline still sees exactly as much negative resistance as it takes to >>equal its equivalent resistive losses. So as regards phase noise, does >>it matter how hard we clip? > >Generally, the clipping won't make a difference to flatband noise. For the >same supply current, AGC pretty much always results in worse noise. This is >because its simply more bits and pieces generating noise. > >The comparator will always be the dominant flat noise in a well designed >circuit. > >This paper gives a full analysis as to what clipping/limiting generates 1/f >up converted phase noise. > >http://www.kevinaylward.co.uk/ee/phasenoise/PhaseNoiseOscillators.xht > >A key idea is minimising non-linear time constants. Don't connect a varacter >directly to the amp. Use a cap to block LF modulation. A pierce resistor can >get you 10dB less 1/f close in noise because it damps out the non-linear >output resistance of the amp. It reduces the HF gain though. > >-- Kevin Aylward >http://www.anasoft.co.uk - SuperSpice >http://www.kevinaylward.co.uk/ee/index.html
Good stuff, thanks. I'll read the paper later. I'm concerned with low frequency phase noise. The clock is used to time out delays in a laser system, and lf phase noise maps to more jitter for longer time delays. The comparator only affects jitter for short delays; longer delays are dominated by the oscillator itself... if I drive the comparator hard, I guess. The comparator can have its own 1/f noise, I guess. Especially an LVDS buffer which is hardly optimized for analog. We should test the LVDS buffer separately. We were going to do that, for speed, but we should evaluate noise too. They are sure cheap. SN65CML100 is a possibility too. Where would that pierce resistor go? -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by Kevin Aylward April 16, 20192019-04-16
>"John Larkin" wrote in message >news:4o07be9esulg78b2c8sd48mlogmpdf41o9@4ax.com...
>I've been thinking about this
>https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0
>as a roughly 500 MHz clock oscillator for some digital stuff. My FPGA >guys claim they can accept that as an LVDS clock input. The comparator >would be LVDS in and out, FAN1101 maybe, if it is really fast enough.
>So I have a question for some more RF-ey guys than me. Q1 furnishes >negative resistance so oscillation builds up, pretty much a sine wave. >At some point R1 and D1 load the negative swing and add real loss, so >it stabilizes at ballpark 1 volt p-p centered on ground, just enough >net negative resistance to match the losses of the transmission line.
>If the gain of Q1 is high (low R2) and R1 is small, it clips pretty >hard and the sine is flattened. It's flattened identically on both the >positive and negative peaks, which confused us for a few seconds.
>So, given all that, how does hard clipping affect the phase noise, as >opposed to softer limiting or, ultimately, some super linear AGC loop? >I want a lot of swing into the comparator, 1 volt p-p maybe before its >ESD diodes conduct, and I want the thing to oscillate reliably, which >suggest sorta hard clipping, with some visible flattening of the sine >wave.
>No matter how much gain we have in Q1, and how hard we clip, the >txline still sees exactly as much negative resistance as it takes to >equal its equivalent resistive losses. So as regards phase noise, does >it matter how hard we clip?
Generally, the clipping won't make a difference to flatband noise. For the same supply current, AGC pretty much always results in worse noise. This is because its simply more bits and pieces generating noise. The comparator will always be the dominant flat noise in a well designed circuit. This paper gives a full analysis as to what clipping/limiting generates 1/f up converted phase noise. http://www.kevinaylward.co.uk/ee/phasenoise/PhaseNoiseOscillators.xht A key idea is minimising non-linear time constants. Don't connect a varacter directly to the amp. Use a cap to block LF modulation. A pierce resistor can get you 10dB less 1/f close in noise because it damps out the non-linear output resistance of the amp. It reduces the HF gain though. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
Reply by whit3rd April 15, 20192019-04-15
On Sunday, April 14, 2019 at 3:50:12 PM UTC-7, John Larkin wrote:
> On Sun, 14 Apr 2019 15:32:19 -0700 (PDT), whit3rd <whit3rd@gmail.com> > wrote: >
> >The phase noise might be dominated by a high harmonic in the delay > >line,...
> ... The oscillation is > mostly sinusoidal, squashed a bit on peaks by the clipping > diode+resistor. I'm only interested in the zero crossings into the > comparator, and near zero volts it looks like a good sine wave. > > In real life, the txline losses go up fast with frequency...
It goes up both because of skin effect, AND because of the dielectric absorption (which is why CATV uses foam dielectric). There is extra time delay for the harmonic. Unless the slew rate at zero crossing is peak voltage * f/(2*pi), the time of that zero crossing is being affected by the harmonics, for which Q is lowered.
Reply by John Larkin April 14, 20192019-04-14
On Sun, 14 Apr 2019 15:32:19 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Sunday, April 14, 2019 at 12:27:45 PM UTC-7, John Larkin wrote: >> I've been thinking about this >> >> https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0 >> >> as a roughly 500 MHz clock oscillator... > >> So, given all that, how does hard clipping affect the phase noise > >It'll affect the phase according to the dispersion of the delay line at the >frequencies of interest. The 'square wave' input means you have not >just 500 MHz, but 1.5GHz, 2.5, 3.5, etc. It also means that the >delay line impedance is just as temperature-sensitive as D1 and Q1. > >The phase noise might be dominated by a high harmonic in the delay >line, is what I'm saying. If you could keep it in the sinewave >oscillating region, it'd be better controlled (because it's unclear >WHICH of the high harmonics is the important one).
The transmission line looks like an inductor below its 1/4 wave frequency, so resonates with the capacitors. Sorta like a quartz crystal in parallel mode looks like an inductor. The oscillation is mostly sinusoidal, squashed a bit on peaks by the clipping diode+resistor. I'm only interested in the zero crossings into the comparator, and near zero volts it looks like a good sine wave. In real life, the txline losses go up fast with frequency, which further encourages a sine wave oscillation mode. What's weird is that the clipping is bouncing back and forth inside the line, many times, but it stays near the peak and doesn't wander off into the rest of the sine wave. With a different kind of gain element, this could be a square wave oscillator. Ctune would change the frequency by softening the edges. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by whit3rd April 14, 20192019-04-14
On Sunday, April 14, 2019 at 12:27:45 PM UTC-7, John Larkin wrote:
> I've been thinking about this > > https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0 > > as a roughly 500 MHz clock oscillator...
> So, given all that, how does hard clipping affect the phase noise
It'll affect the phase according to the dispersion of the delay line at the frequencies of interest. The 'square wave' input means you have not just 500 MHz, but 1.5GHz, 2.5, 3.5, etc. It also means that the delay line impedance is just as temperature-sensitive as D1 and Q1. The phase noise might be dominated by a high harmonic in the delay line, is what I'm saying. If you could keep it in the sinewave oscillating region, it'd be better controlled (because it's unclear WHICH of the high harmonics is the important one).
Reply by Clifford Heath April 14, 20192019-04-14
On 15/4/19 5:27 am, John Larkin wrote:
> If the gain of Q1 is high (low R2) and R1 is small, it clips pretty > hard and the sine is flattened. It's flattened identically on both the > positive and negative peaks, which confused us for a few seconds.
Right, because the negative peak is the inverted reflection from the line. Kevin Aylward is the man to answer your original question. Clifford Heath
Reply by Clifford Heath April 14, 20192019-04-14
On 15/4/19 7:22 am, John Larkin wrote:
> On Sun, 14 Apr 2019 21:12:41 -0000 (UTC), Cursitor Doom > <curd@notformail.com> wrote: >> Have you ever built a TDR by any chance? I should imagine that would be >> right up your street. > > I did a board layout for what might be a 40 ps TDR, and had it built, > but I haven't had time to play with it. > > Old 11801 scopes and SD24 TDR/sampling heads are so cheap and good > it's not worth making or selling your own yet.
In the USA maybe, not elsewhere. Perhaps if you can't sell your design, you could be persuaded to publish it?
Reply by John Larkin April 14, 20192019-04-14
On Sun, 14 Apr 2019 21:12:41 -0000 (UTC), Cursitor Doom
<curd@notformail.com> wrote:

>On Sun, 14 Apr 2019 13:39:10 -0700, John Larkin wrote: > >> The FIN, like most LVDS input parts, is happy working around ground. Or >> Vcc. They are amazing. >> >> https://www.dropbox.com/s/0wccw9kffqxf5r2/FIN1101_Vcm.JPG?dl=0 >> >> If people called it a "1 ns rri comparator" they would charge 10x the >> price. > >Have you ever built a TDR by any chance? I should imagine that would be >right up your street.
I did a board layout for what might be a 40 ps TDR, and had it built, but I haven't had time to play with it. Old 11801 scopes and SD24 TDR/sampling heads are so cheap and good it's not worth making or selling your own yet. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by John Larkin April 14, 20192019-04-14
On Sun, 14 Apr 2019 12:27:36 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

> > >I've been thinking about this > >https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0 > >as a roughly 500 MHz clock oscillator for some digital stuff. My FPGA >guys claim they can accept that as an LVDS clock input. The comparator >would be LVDS in and out, FAN1101 maybe, if it is really fast enough. > >So I have a question for some more RF-ey guys than me. Q1 furnishes >negative resistance so oscillation builds up, pretty much a sine wave. >At some point R1 and D1 load the negative swing and add real loss, so >it stabilizes at ballpark 1 volt p-p centered on ground, just enough >net negative resistance to match the losses of the transmission line. > >If the gain of Q1 is high (low R2) and R1 is small, it clips pretty >hard and the sine is flattened. It's flattened identically on both the >positive and negative peaks, which confused us for a few seconds. > >So, given all that, how does hard clipping affect the phase noise, as >opposed to softer limiting or, ultimately, some super linear AGC loop? >I want a lot of swing into the comparator, 1 volt p-p maybe before its >ESD diodes conduct, and I want the thing to oscillate reliably, which >suggest sorta hard clipping, with some visible flattening of the sine >wave. > >No matter how much gain we have in Q1, and how hard we clip, the >txline still sees exactly as much negative resistance as it takes to >equal its equivalent resistive losses. So as regards phase noise, does >it matter how hard we clip? > >I did google this some but didn't find a good answer.
Oops, switched the values for C1 and C2. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by Cursitor Doom April 14, 20192019-04-14
On Sun, 14 Apr 2019 13:39:10 -0700, John Larkin wrote:

> The FIN, like most LVDS input parts, is happy working around ground. Or > Vcc. They are amazing. > > https://www.dropbox.com/s/0wccw9kffqxf5r2/FIN1101_Vcm.JPG?dl=0 > > If people called it a "1 ns rri comparator" they would charge 10x the > price.
Have you ever built a TDR by any chance? I should imagine that would be right up your street. -- This message may be freely reproduced without limit or charge only via the Usenet protocol. Reproduction in whole or part through other protocols, whether for profit or not, is conditional upon a charge of GBP10.00 per reproduction. Publication in this manner via non-Usenet protocols constitutes acceptance of this condition.