Reply by March 5, 20192019-03-05
On Tuesday, March 5, 2019 at 12:00:18 PM UTC-5, John Larkin wrote:
> On Tue, 5 Mar 2019 08:41:29 -0800 (PST), > bloggs.fredbloggs.fred@gmail.com wrote: > > >On Tuesday, March 5, 2019 at 10:58:21 AM UTC-5, John Larkin wrote: > >> On 5 Mar 2019 05:56:33 -0800, Winfield Hill <hill@rowland.harvard.edu> > >> wrote: > >> > >> >bloggs.fredbloggs.fred@gmail.com wrote... > >> >> > >> >>> Any loop, no matter its rise or fall times, could oscillate. > >> >> > >> >> Yours won't, you have 70o phase margin judging from fig2. > >> >> of the datasheet. Probe the top of R5 for feedback > >> >> gain/phase to input: > >> > > >> > Not clear if Fig 2 is of much help, it's made w/o > >> > high cap load. What John ought to do, is simply > >> > run an open-loop-gain Bode plot, with his load, > >> > make his own Fig 2, see what the phase margin is. > >> > >> The transient response is more useful than a Bode plot. It gets more > >> interesting when it's nonlinear. I saw an oscillation of the OPA552 > >> circuit when it was slewing hard. > >> > >> Since my load will be pulsed, I'll do some pulse-loading sims too. But > >> with 100uF, or even 20 uF, on the output, and microsecond pulses, I > >> don't expect much to happen. > > > >I hope it works better than this f$%$#@%* simulation which defies you to make anything work. > > > > Of course it will work, and we'll sell lots of them. I've done many > similar circuits, and all of them have worked. > > The OPA547 is a better opamp for this, with its programmable current > limit. We'll use that one. Thanks, Lasse. > > https://www.dropbox.com/s/v2zqxk7yzdqz2us/ADG_OPA547_2.jpg?dl=0
That's even easier to deal with, you end up with near 90o phase margin, more current drive, and direct current limiting: Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 128 -64 32 WIRE 16 128 -64 128 WIRE -64 160 -64 128 WIRE 16 160 16 128 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 16 288 16 224 WIRE 16 288 -64 288 WIRE 144 288 144 256 WIRE 144 288 16 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 45k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 0 SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 5k SYMBOL cap 128 64 R0 SYMATTR InstName C1 SYMATTR Value 47n SYMBOL cap 432 160 R0 SYMATTR InstName C2 SYMATTR Value 100&micro; SYMBOL voltage 144 160 R0 WINDOW 123 24 124 Left 2 WINDOW 39 24 152 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=10 Cpar=10p SYMATTR InstName V1 SYMATTR Value "" SYMBOL cap 0 160 R0 SYMATTR InstName C3 SYMATTR Value 20p TEXT -96 312 Left 2 !.ac dec 100 10 100k
> > > > > > > -- > > John Larkin Highland Technology, Inc > > lunatic fringe electronics
Reply by John Larkin March 5, 20192019-03-05
On Tue, 5 Mar 2019 08:41:29 -0800 (PST),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Tuesday, March 5, 2019 at 10:58:21 AM UTC-5, John Larkin wrote: >> On 5 Mar 2019 05:56:33 -0800, Winfield Hill <hill@rowland.harvard.edu> >> wrote: >> >> >bloggs.fredbloggs.fred@gmail.com wrote... >> >> >> >>> Any loop, no matter its rise or fall times, could oscillate. >> >> >> >> Yours won't, you have 70o phase margin judging from fig2. >> >> of the datasheet. Probe the top of R5 for feedback >> >> gain/phase to input: >> > >> > Not clear if Fig 2 is of much help, it's made w/o >> > high cap load. What John ought to do, is simply >> > run an open-loop-gain Bode plot, with his load, >> > make his own Fig 2, see what the phase margin is. >> >> The transient response is more useful than a Bode plot. It gets more >> interesting when it's nonlinear. I saw an oscillation of the OPA552 >> circuit when it was slewing hard. >> >> Since my load will be pulsed, I'll do some pulse-loading sims too. But >> with 100uF, or even 20 uF, on the output, and microsecond pulses, I >> don't expect much to happen. > >I hope it works better than this f$%$#@%* simulation which defies you to make anything work. >
Of course it will work, and we'll sell lots of them. I've done many similar circuits, and all of them have worked. The OPA547 is a better opamp for this, with its programmable current limit. We'll use that one. Thanks, Lasse. https://www.dropbox.com/s/v2zqxk7yzdqz2us/ADG_OPA547_2.jpg?dl=0 -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by March 5, 20192019-03-05
On Tuesday, March 5, 2019 at 10:58:21 AM UTC-5, John Larkin wrote:
> On 5 Mar 2019 05:56:33 -0800, Winfield Hill <hill@rowland.harvard.edu> > wrote: > > >bloggs.fredbloggs.fred@gmail.com wrote... > >> > >>> Any loop, no matter its rise or fall times, could oscillate. > >> > >> Yours won't, you have 70o phase margin judging from fig2. > >> of the datasheet. Probe the top of R5 for feedback > >> gain/phase to input: > > > > Not clear if Fig 2 is of much help, it's made w/o > > high cap load. What John ought to do, is simply > > run an open-loop-gain Bode plot, with his load, > > make his own Fig 2, see what the phase margin is. > > The transient response is more useful than a Bode plot. It gets more > interesting when it's nonlinear. I saw an oscillation of the OPA552 > circuit when it was slewing hard. > > Since my load will be pulsed, I'll do some pulse-loading sims too. But > with 100uF, or even 20 uF, on the output, and microsecond pulses, I > don't expect much to happen.
If it's programmable then you will need to know the settling time to 1/2 LSB step input change. That's strictly small signal.
> > > > > -- > > John Larkin Highland Technology, Inc > > lunatic fringe electronics
Reply by March 5, 20192019-03-05
On Tuesday, March 5, 2019 at 10:58:21 AM UTC-5, John Larkin wrote:
> On 5 Mar 2019 05:56:33 -0800, Winfield Hill <hill@rowland.harvard.edu> > wrote: > > >bloggs.fredbloggs.fred@gmail.com wrote... > >> > >>> Any loop, no matter its rise or fall times, could oscillate. > >> > >> Yours won't, you have 70o phase margin judging from fig2. > >> of the datasheet. Probe the top of R5 for feedback > >> gain/phase to input: > > > > Not clear if Fig 2 is of much help, it's made w/o > > high cap load. What John ought to do, is simply > > run an open-loop-gain Bode plot, with his load, > > make his own Fig 2, see what the phase margin is. > > The transient response is more useful than a Bode plot. It gets more > interesting when it's nonlinear. I saw an oscillation of the OPA552 > circuit when it was slewing hard. > > Since my load will be pulsed, I'll do some pulse-loading sims too. But > with 100uF, or even 20 uF, on the output, and microsecond pulses, I > don't expect much to happen.
I hope it works better than this f$%$#@%* simulation which defies you to make anything work.
> > > > > -- > > John Larkin Highland Technology, Inc > > lunatic fringe electronics
Reply by March 5, 20192019-03-05
On Tuesday, March 5, 2019 at 8:56:49 AM UTC-5, Winfield Hill wrote:
> bloggs.fredbloggs.fred@gmail.com wrote... > > > >> Any loop, no matter its rise or fall times, could oscillate. > > > > Yours won't, you have 70o phase margin judging from fig2. > > of the datasheet. Probe the top of R5 for feedback > > gain/phase to input: > > Not clear if Fig 2 is of much help, it's made w/o > high cap load. What John ought to do, is simply > run an open-loop-gain Bode plot, with his load, > make his own Fig 2, see what the phase margin is. > > > -- > Thanks, > - Win
Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 128 -64 32 WIRE 16 128 -64 128 WIRE -64 160 -64 128 WIRE 16 160 16 128 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 16 288 16 224 WIRE 16 288 -64 288 WIRE 144 288 144 256 WIRE 144 288 16 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 8k SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 128 64 R0 SYMATTR InstName C1 SYMATTR Value 1&micro; SYMBOL cap 432 160 R0 SYMATTR InstName C2 SYMATTR Value 20&micro; SYMBOL voltage 144 160 R0 WINDOW 123 24 124 Left 2 WINDOW 39 24 152 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=10 Cpar=10p SYMATTR InstName V1 SYMATTR Value "" SYMBOL cap 0 160 R0 SYMATTR InstName C3 SYMATTR Value 20p TEXT -96 312 Left 2 !.ac dec 100 10 100k
Reply by March 5, 20192019-03-05
On Tuesday, March 5, 2019 at 8:56:49 AM UTC-5, Winfield Hill wrote:
> bloggs.fredbloggs.fred@gmail.com wrote... > > > >> Any loop, no matter its rise or fall times, could oscillate. > > > > Yours won't, you have 70o phase margin judging from fig2. > > of the datasheet. Probe the top of R5 for feedback > > gain/phase to input: > > Not clear if Fig 2 is of much help, it's made w/o > high cap load. What John ought to do, is simply > run an open-loop-gain Bode plot, with his load, > make his own Fig 2, see what the phase margin is. > > > -- > Thanks, > - Win
It only gets better when OA input capacitance and output impedance are added. It looks like the very large separation between the significant poles helps a lot. Is there some other effect you have in mind? Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 128 -64 32 WIRE 16 128 -64 128 WIRE -64 160 -64 128 WIRE 16 160 16 128 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 16 288 16 224 WIRE 16 288 -64 288 WIRE 144 288 144 256 WIRE 144 288 16 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 8k SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 128 64 R0 SYMATTR InstName C1 SYMATTR Value 1&micro; SYMBOL cap 432 160 R0 SYMATTR InstName C2 SYMATTR Value 20&micro; SYMBOL voltage 144 160 R0 WINDOW 123 24 124 Left 2 WINDOW 39 24 152 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=10 Cpar=10p SYMATTR InstName V1 SYMATTR Value "" SYMBOL cap 0 160 R0 SYMATTR InstName C3 SYMATTR Value 20p TEXT -96 312 Left 2 !.ac dec 100 10 100k
Reply by John Larkin March 5, 20192019-03-05
On 5 Mar 2019 05:56:33 -0800, Winfield Hill <hill@rowland.harvard.edu>
wrote:

>bloggs.fredbloggs.fred@gmail.com wrote... >> >>> Any loop, no matter its rise or fall times, could oscillate. >> >> Yours won't, you have 70o phase margin judging from fig2. >> of the datasheet. Probe the top of R5 for feedback >> gain/phase to input: > > Not clear if Fig 2 is of much help, it's made w/o > high cap load. What John ought to do, is simply > run an open-loop-gain Bode plot, with his load, > make his own Fig 2, see what the phase margin is.
The transient response is more useful than a Bode plot. It gets more interesting when it's nonlinear. I saw an oscillation of the OPA552 circuit when it was slewing hard. Since my load will be pulsed, I'll do some pulse-loading sims too. But with 100uF, or even 20 uF, on the output, and microsecond pulses, I don't expect much to happen. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by Winfield Hill March 5, 20192019-03-05
bloggs.fredbloggs.fred@gmail.com wrote...
> >> Any loop, no matter its rise or fall times, could oscillate. > > Yours won't, you have 70o phase margin judging from fig2. > of the datasheet. Probe the top of R5 for feedback > gain/phase to input:
Not clear if Fig 2 is of much help, it's made w/o high cap load. What John ought to do, is simply run an open-loop-gain Bode plot, with his load, make his own Fig 2, see what the phase margin is. -- Thanks, - Win
Reply by Winfield Hill March 5, 20192019-03-05
tabbypurr@gmail.com wrote...
> > The most common problem with parts from unknown sources > in China is when they turn out to be salvaged parts > remarked as something else. With your fets you could > determine they were what they claimed, that's not always > so easy. But yes, if you don't need traceability or a > trustworthy supplier you can get a lot for a little.
In my two examples, what I needed was the unobtainium performance. If they had been salvaged parts, but worked, I probably would have been happy. Here, the obscure nature of the parts, the low selling price, and the fast delivery all argue against remarking, etc. I forgot to mention, in both cases my 250 pieces came sealed in their proper machine-assembly tape. -- Thanks, - Win
Reply by March 5, 20192019-03-05
On Monday, March 4, 2019 at 11:20:27 PM UTC-5, John Larkin wrote:
> On Mon, 4 Mar 2019 15:18:24 -0800 (PST), > bloggs.fredbloggs.fred@gmail.com wrote: > > >On Monday, March 4, 2019 at 11:31:14 AM UTC-5, John Larkin wrote: > >> On Mon, 4 Mar 2019 07:45:10 -0800 (PST), > >> bloggs.fredbloggs.fred@gmail.com wrote: > >> > >> >On Sunday, March 3, 2019 at 5:33:23 PM UTC-5, John Larkin wrote: > >> >> On Sun, 3 Mar 2019 14:05:58 -0800 (PST), > >> >> bloggs.fredbloggs.fred@gmail.com wrote: > >> >> > >> >> >On Sunday, March 3, 2019 at 3:43:31 PM UTC-5, John Larkin wrote: > >> >> >> On Sun, 3 Mar 2019 11:46:45 -0800 (PST), > >> >> >> bloggs.fredbloggs.fred@gmail.com wrote: > >> >> >> > >> >> >> >On Sunday, March 3, 2019 at 1:42:31 PM UTC-5, John Larkin wrote: > >> >> >> >> On Sun, 3 Mar 2019 09:20:23 -0800 (PST), > >> >> >> >> bloggs.fredbloggs.fred@gmail.com wrote: > >> >> >> >> > >> >> >> >> >On Saturday, March 2, 2019 at 3:13:18 PM UTC-5, John Larkin wrote: > >> >> >> >> >> On Sat, 2 Mar 2019 11:38:17 -0800 (PST), > >> >> >> >> >> bloggs.fredbloggs.fred@gmail.com wrote: > >> >> >> >> >> > >> >> >> >> >> >On Saturday, March 2, 2019 at 1:25:29 PM UTC-5, John Larkin wrote: > >> >> >> >> >> >> I need some programmable power supply rails, maybe -5 to +40 volts or > >> >> >> >> >> >> so. We have some OPA552s in stock, a nice 60 volt power opamp. It's a > >> >> >> >> >> >> decomp, and it will be driving a big capacitive load, so there is an > >> >> >> >> >> >> oscillation hazard. One of my guys got the model from TI and kluged it > >> >> >> >> >> >> into LT Spice. The symbol is ugly but it seems to work. We don't know > >> >> >> >> >> >> how to make it look like a real opamp. > >> >> >> >> >> >> > >> >> >> >> >> >> https://www.dropbox.com/s/0qkphdgnpv8y0xv/ADG_Vhi_1.jpg?dl=0 > >> >> >> >> >> >> > >> >> >> >> >> >> This looks fine, even without C1. Maybe I'll include C1 on the pcb > >> >> >> >> >> >> layout just to have another knob to turn. > >> >> >> >> >> >> > >> >> >> >> >> >> I'd like to use the OPA552 thermal cutoff as a secondary, slowish > >> >> >> >> >> >> current limit, but I'd have to tune the pcb thermal resistance somehow > >> >> >> >> >> >> to control that. Maybe a bunch of thermal-zero-ohm jumpers? Maybe a > >> >> >> >> >> >> tweakable amount of gap-pad under the board, or above the amp? I > >> >> >> >> >> >> suppose I could selectively drill out vias on the rev A board, but > >> >> >> >> >> >> that's really ugly. > >> >> >> >> >> >> > >> >> >> >> >> >> I want a thermal conductivity trimpot. Or DAC. > >> >> >> >> >> > > >> >> >> >> >> >What's wrong with using FLAG? > >> >> >> >> >> > >> >> >> >> >> For what? We'll probably not connect it in real life. I guess it could > >> >> >> >> >> light up a red LED or something. > >> >> >> >> > > >> >> >> >> >Didn't you say you wanted to know when it went into thermal cutoff so you could reduce the output current? That's for what. > >> >> >> >> > > >> >> >> >> >> > >> >> >> >> >> > > >> >> >> >> >> >Is that 1p for C1 right? You have stray that's 10x that. > >> >> >> >> >> > >> >> >> >> >> That's a placeholder for "maybe we don't need a cap there." I said > >> >> >> >> >> that. > >> >> >> >> >> > >> >> >> >> >> Tweaking a bit more, it looks like C1 is a good idea: 1 uF. > >> >> >> >> > > >> >> >> >> >I'm not sure it will work so well since the cap shunts the feedback into the low impedance output of the opamp, when it cuts in. > >> >> >> >> > > >> >> >> >> > >> >> >> >> The cap closes the feedback loop local to the opamp, at high > >> >> >> >> frequencies, so the extra pole of the big output cap doen't make the > >> >> >> >> closed loop unstable. That's pretty common. Win discusses that config > >> >> >> >> in AoE3 p 264. > >> >> >> > > >> >> >> >He does? The feedback resistor from the output usually joins to the OA IN(-) and not the inner feedback R+C zero. > >> >> >> > >> >> >> As noted, the OPA552 is not unity-gain stable, so it makes sense to > >> >> >> jam in the fast feedback before the gain-set divider. > >> >> >> > >> >> >> >And you're not compensating for the OA since your gain is large enough. You're compensating for that dominant pole on the output. > >> >> >> > >> >> >> That's just a lot of words. I designed it to work, and it does. > >> >> > > >> >> >That 20 + 20 u alone breaks at 2500 Hz, > >> >> > >> >> radians > >> >> > >> >> > that's not a lot of words, and the output resistance of the OA probably makes it 1000Hz. The OA actually has a pretty clean phase/frequency, looks like a perfect integrator out to 1MHz before the higher frequency internals start cutting in. Did you run a gain/phase on the TI model to see if it resembles fig 2 of the datasheet? > >> >> > >> >> My guy made an inverting -1 gain amp in LT Spice, and the frequency > >> >> response peaked right where it should have. The model looks OK. > >> > > >> >Something isn't right because if you don't compensate for that low frequency output pole, the entire sense of the amplifier is inverted. Does LTSpice do a noise gain analysis? You should run it. > >> > >> C1 fixes the loop stability problem. My current version has C1=1uF, > >> but I was surprised that it behaves well at 1 pF, which is really a > >> placeholder for zero. > >> > >> https://www.dropbox.com/s/3ecb7qtn9ilgqfa/ADG_Vhi_2.jpg?dl=0 > >> > >> Step response is clean, so it's stable. > >> > >> TI doesn't give a schematic of the amp internals. Some opamps bury > >> their dominant pole deep inside, so get unstable in circuits like this > >> where an external pole is added to the loop. But some hang one end of > >> the comp cap on the output pin, so capacitive loads change that > >> internal rolloff, and they tolerate c-loads. A few opamps, like > >> LM8261, tolerate any capacitive load. > > > >LOL- 0.1s rise and fall times won't be exciting any instabilities. > > > > I limited the DAC slew rate so as to not current limit big swings into > 100 uF. I don't expect people to want to change the output voltage > very fast. > > Any loop, no matter its rise or fall times, could oscillate.
Yours won't, you have 70o phase margin judging from fig2. of the datasheet. Probe the top of R5 for feedback gain/phase to input: Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 160 -64 32 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 144 288 144 256 WIRE 144 288 -64 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 8k SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 128 64 R0 SYMATTR InstName C1 SYMATTR Value 1&micro; SYMBOL cap 432 160 R0 SYMATTR InstName C2 SYMATTR Value 20&micro; SYMBOL voltage 144 160 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value AC 1 TEXT 224 320 Left 2 !.ac dec 100 10 100k Really flat feedback gain at -20dB and non existent to negligible phase shift.
> > > -- > > John Larkin Highland Technology, Inc > > lunatic fringe electronics