Reply by Tim Williams August 7, 20182018-08-07
<bill.sloman@ieee.org> wrote in message 
news:10eae4ac-4d9e-46c0-8ad1-dc167ebe8bb2@googlegroups.com...
>A 50% duty cycle is incompatible with break-before-make switching.
>It takes a finite time to switch a MOSFET on or off - you've got to move a >finite amount of charge into or out of the gate electrode - so a 50% duty >cycle implkes that one is turning off (but not turned fully off) at the >same time as the other one is turning on (but not fully turned on). >
Yeah, for PP, you have to deal with the transformer. Small deadtimes (including negative) can be okay for half bridge, as long as you're not driving a low-DCR load (like a transformer without a coupling cap). The classic solution being the ATX power supply, where a half bridge drives the transformer primary, returned via 2.2uF film cap to the FWD supply's middle tap. (The cap could return to any end of the supply, but the middle tap is convenient to reduce the startup transient. Alternately, a "half bridge" of caps can be used -- a capacitor divider -- which is the preferred method for FWB supplies.) Note that, within a cycle (i.e., ignoring "flux walking" bias over many cycles), each switching transient involves the inductance between switches. In the PP case, that's the end-to-end leakage. In the half bridge, it's stray wiring inductance, from nearest bypass cap, through the two switches. Zero dead time, or slightly interleaved, switching is possible when that loop inductance is intentionally controlled, setting dI/dt. This is preferable for synchronous switching, and for bidirectional converters (power converters, class D amps) where consistent EMI and higher efficiency is needed. (Not much higher efficiency, mind -- the high frequency reactive current drawn by the overlap has to be dealt with appropriately after all. The main thing to be gained is body diode recovery, which is a monster with higher voltage MOSFETs.) Also, a current-sourced inverter MUST operate interleaved. In that case, "dead time" is dead in the voltage sense, meaning, both devices ON during the dead time. This isn't used much in power applications, but is relevant to some configurations ("Royer oscillator") and RF amps (e.g., class E, PP). Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website: https://www.seventransistorlabs.com/
Reply by August 7, 20182018-08-07
On a sunny day (Mon, 6 Aug 2018 14:17:44 -0700 (PDT)) it happened AntonF
<fortunatov@gmail.com> wrote in
<d6fcdc35-8f46-4e7a-8ab8-eaa9a2165ac3@googlegroups.com>:

>May I add one more question on push-pull transformers? How do I choose inductance >of primary coil? The datasheets for LT1533 and LT1683 say: >"The inductance of the transformer primary should be such >that LO, when reflected into the primary, dominates the >input current. In other words, we want the magnetizing >current of the transformer small with respect to the >current going through the transformer to LO. In general, >then, the inductance of the primary should be at least five >times that of LO. This ensures that most of the power will >be passed through the transformer to the load. It also >increases the power capability of the converter and >reduces the peak currents that the switch will see." > >I don't this recommendation. L0 is inductance of the output filter. First sentence >says L0 should dominate (that is: larger L0 compare to Lpri - the better), >but the third says Lpri should be "at least 5 =E2=80=A2 LO/N^2" (that >is: large Lpri compare to L0 - the better). What is physical meaning behind >that recommendation?
Having wound and using several push pull transformers, you want the UNLOADED inductance of the primary so high that it does not cause excessive currents in the drivers. That sets the minimum number of turns.
Reply by August 6, 20182018-08-06
On Sunday, August 5, 2018 at 5:42:48 PM UTC+10, Tim Williams wrote:
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
A 50% duty cycle is incompatible with break-before-make switching. It takes a finite time to switch a MOSFET on or off - you've got to move a finite amount of charge into or out of the gate electrode - so a 50% duty cycle implkes that one is turning off (but not turned fully off) at the same time as the other one is turning on (but not fully turned on). This tends to produce nasty current spikes in the supply current. At 100k - a 10usec period - a 45% duty cycle implies two 250nsec gap to cover turn-on and turn-off, which ought to be generous. With high current gate drivers 25nsec might be enough. <snip> -- Bill Sloman, Sydney
Reply by Tim Williams August 6, 20182018-08-06
"AntonF" <fortunatov@gmail.com> wrote in message 
news:d6fcdc35-8f46-4e7a-8ab8-eaa9a2165ac3@googlegroups.com...
> I don't this recommendation. L0 is inductance of the output filter. First > sentence says L0 should dominate (that is: larger L0 compare to Lpri - the > better) >
Read it closely: LO _current_ should dominate. Inductance is inverse with current, therefore LO should be >5 times smaller than Lpri, as it goes on to say. Cheers, Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website: https://www.seventransistorlabs.com/
Reply by AntonF August 6, 20182018-08-06
May I add one more question on push-pull transformers? How do I choose inductance of primary coil? The datasheets for LT1533 and LT1683 say:
"The inductance of the transformer primary should be such
that LO, when reflected into the primary, dominates the
input current. In other words, we want the magnetizing
current of the transformer small with respect to the
current going through the transformer to LO. In general,
then, the inductance of the primary should be at least five
times that of LO. This ensures that most of the power will
be passed through the transformer to the load. It also
increases the power capability of the converter and
reduces the peak currents that the switch will see."

I don't this recommendation. L0 is inductance of the output filter. First sentence says L0 should dominate (that is: larger L0 compare to Lpri - the better), but the third says Lpri should be "at least 5 &bull; LO/N^2" (that is: large Lpri compare to L0 - the better). What is physical meaning behind that recommendation?
Reply by Tim Williams August 5, 20182018-08-05
"Piotr Wyderski" <peter.pan@neverland.mil> wrote in message 
news:pk6e33$snv$1@node1.news.atman.pl...
> Tim Williams wrote: > >> Duty cycle is too high, limit it to, say, 45% (per output) or >> thereabouts. > > Zener snubbing works, with two back-to back connected 18V DO35 diodes > attached to the primary endings the waveforms are like this: > > https://s15.postimg.cc/ixq9wyv7f/DS1_Z_Quick_Print12.png > > But the diodes get warm and idle current jumps to 104mA. > There is considerable power going into the snubber, not good.
Right, you also don't want to do that for a 20V maximum input. 30V TVSs would be better, or a clamp snubber, or quasi-resonant snubber if applicable, etc. Or you can reduce switching time, effectively burning that power in the transistors. If you already need to heatsink them, that's not a big deal. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website: https://www.seventransistorlabs.com/
Reply by Tim Williams August 5, 20182018-08-05
"Piotr Wyderski" <peter.pan@neverland.mil> wrote in message 
news:pk6c9t$qvc$1@node1.news.atman.pl...
> Sure, but could you please explain the asymmetry? >
Most likely pulse width imbalance, leading to "flux walking" as it's colloquially called, but it's just DC imbalance, not some arcane bit of magnetic physics. Reducing duty gives a high impedance period where the transformer can resolve its flux.
> It was the first low-power Schottky I found in the box. I'll check > with something better later. I'm also going to check Zener clamping > just to see what happens (on a good way to invent a MINIMELF LED?)
Better to do an RCD clamp snubber (one diode and one cap, each side; tie together the cathodes and use one resistor back to VIN). Downside: wastes idle current, so efficiency is crap at low output. May or may not be a concern. There are other similar approaches. Simply winding the primary well is the best, but that's not always possible or practical, especially with transistors being as fast as they are these days.
> Will work for sure, > but there would be no fun. ;-) > > I'm willing to spend some time on this approach just to learn something.
:-) Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website: https://www.seventransistorlabs.com/
Reply by Piotr Wyderski August 5, 20182018-08-05
Tim Williams wrote:

A third transformer, 2x10 turns on 16mm 3F3. This
is clearly the winner of the ringing contest:

https://s15.postimg.cc/8q7qkg6dn/DS1_Z_Quick_Print13.png

Dr. Zener is able to teach it good manners, but he sweats like hell.

	Best regards, Piotr
Reply by Piotr Wyderski August 5, 20182018-08-05
Tim Williams wrote:

> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
Sure, but could you please explain the asymmetry?
> No idea what the BAT83s are for, they're at best resistors when forward > biased if ever.&#2013266080; At worst, tiny fuse links when pushed slightly harder. :-)
It was the first low-power Schottky I found in the box. I'll check with something better later. I'm also going to check Zener clamping just to see what happens (on a good way to invent a MINIMELF LED?)
> Shittons of outputs aren't too bad for forward converters, but don't > expect good cross-regulation, unless you can make them all very tightly > coupled!
Only the 3.3V rail needs good regulation, 9V needs to be decent (+/-0.5V is fine) and the 18V rail just needs to be there, as it is intended to power a 10W D-class audio amplifier with.
> You may find it's better to use a main supply (e.g., the 18V?)
8..20. That would require a buck-boost to get 18V and functional isolation is highly welcome. For that reason another option is to produce that 18V with something isolated and then go down with a bunch of SOT-23 synchronous bucks from TI. Will work for sure, but there would be no fun. ;-) I'm willing to spend some time on this approach just to learn something. Best regards, Piotr
Reply by August 5, 20182018-08-05
Piotr Wyderski wrote:
>OK, some experimental data. > >UCC28084, f_osc=224kHz, V_IN=10V (desired range: ~8..20V), >no feedback to force 50/50 mode, no secondary windings. >R_SENSE=50m, output switches: SQJA62EP-T1_GE3, input cap: >150uF/35V SMD polymer tantalum with 70m of ESR. 3D construction >to minimize the lengths of the wires, ~1cm transformer leads >soldered directly to the cap/drain tabs. BAT83 30mA diodes >between D and S, just in case. No gate resistors. Core >is B64290L0618X087, 25mm OD toroid made of N87. > >Trafo #1: 1x7 turns, 20x0.335mm wires twisted together >and then unbraided to make the center-tap primaries. >Spread evenly across the core. Considered the best I can do. > >Trafo #2: 2x10 turns of 0.7wire, the first half, the tap >and then the second part, wound tightly. The worst possible >implementation, just for reference. > >Results: > >Idle current=54mA for Trafo #1, 39mA for T#2. Looks like >the effect of the increased capacitance Bill wrote about. > >Gate signals: perfect, sharp, no ringing. > >Drain waveforms: strange in both cases. With T#1 and T#2 >I have massive ringing, but only on one of the drains. >It's not an output stage issue. If I swap the primary >endings, nothing changes. If I swap the gate signals, >the ringing goes to the other coil. So it originates in >the controller itself. > >With T#1 it is always like that: > >https://s15.postimg.cc/harvkb1u3/DS1_Z_Quick_Print11.png > >With T#2 it started more symmetric: > >https://s15.postimg.cc/3tux17el7/DS1_Z_Quick_Print10.png > >But by manually squeezing/stretching the primaries I am able >to restore the T#1 situation, i.e. dampen the blue waveform. >I am not able to significantly alter the yellow ringing, though. >50V of ringing in a 10V-powered push-pull looks scary. Moreover, >it continues for the entire off-period. > > Best regards, Piotr
I would expect no ringing if the SQJA62EPs were switched on 100%. Datasheet says threshold <= 2.5V, you will need 4V for it to be full on. What do the gate signals look like?