Reply by July 4, 20182018-07-04
On 3 Jul 2018 12:50:08 -0700, Winfield Hill <hill@rowland.harvard.edu>
wrote:

>upsidedown@downunder.com wrote... >> >> Winfield Hill wrote: >> >>> Switching converters and sensitive SAR ADCs don't >>> go well together. Consider a 3.7 Li-ion to 14V boost >>> converter, switching 400mA current ramps at 500kHz. >>> Add a 16-bit ADC, which takes 2us to sampling a signal, >>> and completes its conversion in 15us. A large fraction >>> of the ADC samples are degraded by SMPS switching noise. >> >> So there is a proper Sample & Hold in front of the SAR ? >> Without a S&H any SAR could produce quite erratic results... > > Typical SAR ADCs copy the input voltage onto a small > capacitor, which is then disconnected from the input, > and discharged with successively-smaller 1/2^n charge > packets. What subsequently happens to the input > during this conversion process doesn't matter.
So the capacitor charge goes to zero at end of SAR conversion ? So when the next acquisition cycle begins, the charge is zero and it starts slowly to charge to the input voltage by integrating the charge? The charge is then isolated from input at the beginning of the hold period. The interesting question is, is the analog input stage driver impedance so low, that it immediately changes the capacitor voltage, so at start of hold, the voltage is what happens to be at start of hold. Or is the driving impedance so high that the capacitor is actually integrating (averaging) the average voltage of the whole acquisition period ? If it really averages the voltage level of the whole aquisition period, then this could be used to average out any very high noise, provided that the acquisition period is an exact integer multiple of the offending noise. Compare this with some slow integrating ADCs with 10 Hz (100 ms) sampling rate, this handles nicely the mains hum in both 50 Hz or 60 Hz countries by integrating exactly 5 resp. 6 hum cycles during each cycle. In this case the 500 kHz interference is well above Nyquist frequency, so the anti-alias filter should take care of the interface coming through the analog input pins, so the remaining noise comes through Vdd and ground pins. If the acquisition could start at a specific 500 kHz cycle and last exactly an integer number of 500 kHz cycles before going to hold mode, much of the interference would be averaged out. The hold period could then last as long as is needed and then be idle until the next 500 kHz cycle and then start a new acquisition cycle.
Reply by Tim Williams July 4, 20182018-07-04
"Winfield Hill" <hill@rowland.harvard.edu> wrote in message 
news:phgk1g0rmd@drn.newsguy.com...
> Typical SAR ADCs copy the input voltage onto a small > capacitor, which is then disconnected from the input, > and discharged with successively-smaller 1/2^n charge > packets. What subsequently happens to the input > during this conversion process doesn't matter.
Or the older ones, anyway -- I think today they're mostly two matched caps, pumped to VREF or GND alternately to successively divide the signal until done. I'd imagine JT can tell much more about it (well... "can" but not "may", as these things tend to be). Possibly with a precision 2x gain stage at the same time, so the ref value doesn't change (as it does with a SAR + DAC + comparator), just the offset fed to the gain stage. I'm pretty sure the XMEGA does it this way, at least -- when you set the ADC for higher gain settings, you have a selection in powers of 2, and each power adds another clock cycle to the acquisition. Or if you only need 8 bits of acquisition, then you only need as many cycles to do it. They also describe it as a pipelined ADC, which isn't relevant on the cheaper (D series) parts, but is on the fully-featured (A series) ones, which have multiple channels, and I guess, a greater amount of shared hardware, letting you interleave samples and such. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/
Reply by Winfield Hill July 3, 20182018-07-03
upsidedown@downunder.com wrote...
> > Winfield Hill wrote: > >> Switching converters and sensitive SAR ADCs don't >> go well together. Consider a 3.7 Li-ion to 14V boost >> converter, switching 400mA current ramps at 500kHz. >> Add a 16-bit ADC, which takes 2us to sampling a signal, >> and completes its conversion in 15us. A large fraction >> of the ADC samples are degraded by SMPS switching noise. > > So there is a proper Sample & Hold in front of the SAR ? > Without a S&H any SAR could produce quite erratic results...
Typical SAR ADCs copy the input voltage onto a small capacitor, which is then disconnected from the input, and discharged with successively-smaller 1/2^n charge packets. What subsequently happens to the input during this conversion process doesn't matter. -- Thanks, - Win
Reply by July 3, 20182018-07-03
On Tuesday, July 3, 2018 at 2:24:15 PM UTC-4, Phil Hobbs wrote:
> On 07/03/18 09:42, gnuarm.deletethisbit@gmail.com wrote: > > On Tuesday, July 3, 2018 at 2:05:02 AM UTC-4, Tom Del Rosso wrote: > >> gnuarm.deletethisbit@gmail.com wrote: > >>> On Saturday, June 30, 2018 at 2:32:49 PM UTC-4, Tom Del Rosso wrote: > >>>> John Larkin wrote: > >>>>> > >>>>> Delta-sigma just uses a duty-cycle-based DAC to balance the input > >>>>> signal into an integrator. When it's balanced, the duty cycle tells > >>>>> you the input voltage. Some tricks are played to reduce the duty > >>>>> cycle ripple and speed things up. > >>>> > >>>> So you adjust the duty until the integrator equals the input. But it > >>>> seems that a "duty-cycle-based DAC" _is_ an integrator. > >>>> > >>>> In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an > >>>> internal counter and DAC driving one input of a comparator, the > >>>> output of which was a duty-cycle based digital value. No > >>>> integrator. It looked cheap to me then. But it seems that the > >>>> output is equivalent to delta sigma. > >>> > >>> I don't think so. The DAC is a conventional DAC that converts the > >>> counter output to an analog voltage, right? Then that analog signal > >>> is compared to the analog input, right? That is a ultra slow linear > >>> counting version of a SAR. At the point the comparator trips the > >>> counter value is the digital output. Not at all equivalent to a > >>> delta sigma. > >> > >> It was an 8-pin DIP. The counter value wasn't output. All that was > >> readable was the comparator output, so the output was the duty cycle. > > > > Think about this a bit. The output of the comparator will be 50/50 duty cycle when the counter has reached a value where the DAC is approximately equal to the input voltage. How could the bit stream output by the comparator be duty cycle related to the input amplitude? > > Because it wasn't up/down, but rolled over after 256 clocks and started > again from zero.
Ah, so the counter and DAC were generating a saw tooth waveform which was working with the comparator to create a pulse width modulated output. In replay to Tom's "But it seems that the output is equivalent to delta sigma.", this is nothing like delta-sigma. This is simple pulse width modulation.
> > How was this output to be used? > > Well, you could feed it to an RC airplane servo.
Yeah, that's pretty obvious now. Rick C.
Reply by Phil Hobbs July 3, 20182018-07-03
On 07/03/18 09:42, gnuarm.deletethisbit@gmail.com wrote:
> On Tuesday, July 3, 2018 at 2:05:02 AM UTC-4, Tom Del Rosso wrote: >> gnuarm.deletethisbit@gmail.com wrote: >>> On Saturday, June 30, 2018 at 2:32:49 PM UTC-4, Tom Del Rosso wrote: >>>> John Larkin wrote: >>>>> >>>>> Delta-sigma just uses a duty-cycle-based DAC to balance the input >>>>> signal into an integrator. When it's balanced, the duty cycle tells >>>>> you the input voltage. Some tricks are played to reduce the duty >>>>> cycle ripple and speed things up. >>>> >>>> So you adjust the duty until the integrator equals the input. But it >>>> seems that a "duty-cycle-based DAC" _is_ an integrator. >>>> >>>> In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an >>>> internal counter and DAC driving one input of a comparator, the >>>> output of which was a duty-cycle based digital value. No >>>> integrator. It looked cheap to me then. But it seems that the >>>> output is equivalent to delta sigma. >>> >>> I don't think so. The DAC is a conventional DAC that converts the >>> counter output to an analog voltage, right? Then that analog signal >>> is compared to the analog input, right? That is a ultra slow linear >>> counting version of a SAR. At the point the comparator trips the >>> counter value is the digital output. Not at all equivalent to a >>> delta sigma. >> >> It was an 8-pin DIP. The counter value wasn't output. All that was >> readable was the comparator output, so the output was the duty cycle. > > Think about this a bit. The output of the comparator will be 50/50 duty cycle when the counter has reached a value where the DAC is approximately equal to the input voltage. How could the bit stream output by the comparator be duty cycle related to the input amplitude?
Because it wasn't up/down, but rolled over after 256 clocks and started again from zero.
> > How was this output to be used?
Well, you could feed it to an RC airplane servo. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by Castorp July 3, 20182018-07-03
On Tuesday, 3 July 2018 16:39:36 UTC+2, Gerhard Hoffmann  wrote:
> Am 02.07.2018 um 21:24 schrieb Castorp: > > SAR is catching up fast, also in the higher number of bits. I was surprised by the results I got for >=24 bit ADCs. Sigma-Delta still rules though, but I don't think it's due to anything fundamental. > > > > https://www.researchgate.net/publication/325285614_Analog-to-digital_conversion_beyond_20_bits_Applications_architecutres_state_of_the_art_limitations_and_future_prospects > > > > More will be published later, including actual measurements of low-frequency noise. > > > > One obvious thing I "discovered" along the way was that you really have to be super careful with these babies. > > Yes. I'm just playing with this one: > > < > https://www.digikey.de/product-detail/de/linear-technology-analog-devices/LTC2500CDKD-32-PBF/LTC2500CDKD-32-PBF-ND/6670442 > > > > because I'm sick of the low frequency noise of my FFT analyzer. > > It is recommended to leave it alone for 2/3 of the conversion cycle, i.e > no toggling of the conversion clock, no activity to read it out etc. > > It requires a 100 MHz SPI clock or quite clumsy multi-cycle reading > at 1 MHz sample rate. > > regards, Gerhard
I got pretty similar results for the 20 and 24-bit SAR ADCs by Linear. Didn't get as far as the "32-bit", which just has a lofty digital filter to spew out a few more bits above 24, which are semi-meaningful. These ADCs are indeed not so bad! From the still-unpublished pot: AD7177-2 is the champion. Use external 5 V reference, external crystal, and disable the internal input buffers. Then it puts you somewhere around 15 nVRMS/decade of 1/f noise. With a white noise floor of 32 nV/sqrtHz, that sets the corner frequency around 0.05 Hz. Quite impressive! It also has negligible offset drift and sub-ppm per degree gain drift. Cheers, Nikolai
Reply by Gerhard Hoffmann July 3, 20182018-07-03
Am 02.07.2018 um 21:24 schrieb Castorp:
> SAR is catching up fast, also in the higher number of bits. I was surprised by the results I got for >=24 bit ADCs. Sigma-Delta still rules though, but I don't think it's due to anything fundamental. > > https://www.researchgate.net/publication/325285614_Analog-to-digital_conversion_beyond_20_bits_Applications_architecutres_state_of_the_art_limitations_and_future_prospects > > More will be published later, including actual measurements of low-frequency noise. > > One obvious thing I "discovered" along the way was that you really have to be super careful with these babies.
Yes. I'm just playing with this one: < https://www.digikey.de/product-detail/de/linear-technology-analog-devices/LTC2500CDKD-32-PBF/LTC2500CDKD-32-PBF-ND/6670442 > because I'm sick of the low frequency noise of my FFT analyzer. It is recommended to leave it alone for 2/3 of the conversion cycle, i.e no toggling of the conversion clock, no activity to read it out etc. It requires a 100 MHz SPI clock or quite clumsy multi-cycle reading at 1 MHz sample rate. regards, Gerhard
Reply by July 3, 20182018-07-03
upsidedown@downunder.com wrote:
> On 28 Jun 2018 04:35:38 -0700, Winfield Hill > <hill@rowland.harvard.edu> wrote: > >> Switching converters and sensitive SAR ADCs don't >> go well together. Consider a 3.7 Li-ion to 14V boost >> converter, switching 400mA current ramps at 500kHz. >> Add a 16-bit ADC, which takes 2us to sampling a signal, >> and completes its conversion in 15us. A large fraction >> of the ADC samples are degraded by SMPS switching noise. > > So there is a proper Sample & Hold in front of the SAR ? > Without a S&H any SAR could produce quite erratic results, if the > input varies during the SA sequence due to bad anti-aliasing filters > or power supply noise. > > Is the sample pulse synchronized with the converter cycle pulse ? > This would at last give consistent measurements, although not quite > "correct" values. Integrate & Dump in front would be even better. >
A SAR's analog input voltage is indeed held in a Sample & Hold. Although Maxim calls it a "track-and-hold." 73, -- Don Kuenz, KB7RPU
Reply by July 3, 20182018-07-03
On Tuesday, July 3, 2018 at 2:05:02 AM UTC-4, Tom Del Rosso wrote:
> gnuarm.deletethisbit@gmail.com wrote: > > On Saturday, June 30, 2018 at 2:32:49 PM UTC-4, Tom Del Rosso wrote: > >> John Larkin wrote: > >>> > >>> Delta-sigma just uses a duty-cycle-based DAC to balance the input > >>> signal into an integrator. When it's balanced, the duty cycle tells > >>> you the input voltage. Some tricks are played to reduce the duty > >>> cycle ripple and speed things up. > >> > >> So you adjust the duty until the integrator equals the input. But it > >> seems that a "duty-cycle-based DAC" _is_ an integrator. > >> > >> In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an > >> internal counter and DAC driving one input of a comparator, the > >> output of which was a duty-cycle based digital value. No > >> integrator. It looked cheap to me then. But it seems that the > >> output is equivalent to delta sigma. > > > > I don't think so. The DAC is a conventional DAC that converts the > > counter output to an analog voltage, right? Then that analog signal > > is compared to the analog input, right? That is a ultra slow linear > > counting version of a SAR. At the point the comparator trips the > > counter value is the digital output. Not at all equivalent to a > > delta sigma. > > It was an 8-pin DIP. The counter value wasn't output. All that was > readable was the comparator output, so the output was the duty cycle.
Think about this a bit. The output of the comparator will be 50/50 duty cycle when the counter has reached a value where the DAC is approximately equal to the input voltage. How could the bit stream output by the comparator be duty cycle related to the input amplitude? How was this output to be used? Rick C.
Reply by July 3, 20182018-07-03
On 28 Jun 2018 04:35:38 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

> Switching converters and sensitive SAR ADCs don't > go well together. Consider a 3.7 Li-ion to 14V boost > converter, switching 400mA current ramps at 500kHz. > Add a 16-bit ADC, which takes 2us to sampling a signal, > and completes its conversion in 15us. A large fraction > of the ADC samples are degraded by SMPS switching noise.
So there is a proper Sample & Hold in front of the SAR ? Without a S&H any SAR could produce quite erratic results, if the input varies during the SA sequence due to bad anti-aliasing filters or power supply noise. Is the sample pulse synchronized with the converter cycle pulse ? This would at last give consistent measurements, although not quite "correct" values. Integrate & Dump in front would be even better.