Reply by Lasse Langwadt Christensen April 16, 20172017-04-16
Den søndag den 16. april 2017 kl. 10.28.19 UTC+2 skrev TTman:
> On 16/04/2017 00:16, John Larkin wrote: > > > > Has anyone used the DAC2904? We don't entirely understand the timing. > > We asked TI for help, and thay said "Oh, that's an old Burr-Brown > > part, nobody knows much about that." > > > > > I guess WRT could be used as async and CLK = sync, basically double > buffered.... >
I suspect is so that you can feed it a nice clean clock for the sampling directly from and oscillator and feed it samples with the "dirty" clock from a controller
Reply by TTman April 16, 20172017-04-16
On 16/04/2017 00:16, John Larkin wrote:
> > Has anyone used the DAC2904? We don't entirely understand the timing. > We asked TI for help, and thay said "Oh, that's an old Burr-Brown > part, nobody knows much about that." > >
I guess WRT could be used as async and CLK = sync, basically double buffered.... --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Reply by rickman April 15, 20172017-04-15
On 4/15/2017 7:16 PM, John Larkin wrote:
> > Has anyone used the DAC2904? We don't entirely understand the timing. > We asked TI for help, and thay said "Oh, that's an old Burr-Brown > part, nobody knows much about that."
I don't see anything odd about the timing. It's a bit odd that the input registers appear to be "latches" and the timing diagram is a bit vague. I can only imagine the input is registered and not latched or the timing would be nearly impossible to meet at full speed. "The data is first loaded into the input latch by a rising edge of the WRT line. This data is presented to the DAC latch on the following falling edge of the WRT signal." I am guessing they are using a variant on the standard edge triggered register which uses a pair of opposite polarity enable latches to accept an input on a clock edge and present it to the output following the same edge. If you make the two latches the same enable polarity the output doesn't change until the other edge of the clock giving lots of setup and hold time to the following DAC register. If they properly drew the tH timing data in the timing diagram there would be no question in my mind. But I'm pretty sure they simply drew the hold time value to the wrong point. As it is it really doesn't make sense. But it is quite a reach to think the hold time refers to the falling edge of WRT. -- Rick C
Reply by John Larkin April 15, 20172017-04-15
Has anyone used the DAC2904? We don't entirely understand the timing.
We asked TI for help, and thay said "Oh, that's an old Burr-Brown
part, nobody knows much about that."


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com