Reply by Jeroen Belleman March 31, 20172017-03-31
On 2017-03-30 20:43, George Herold wrote:
> On Thursday, March 30, 2017 at 10:16:47 AM UTC-4, Francesco Zappon > wrote: >> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann >> wrote: >>> Am 30.03.2017 um 10:02 schrieb Francesco Zappon: >> >> [cut] >> >>> regards, Gerhard >> >> Hi Gerhard, >> >> thanks for the answer. >> >> I will give a general answer valid also for the others that >> commented on radiation hardness: we are operating with a 7 TeV beam >> of protons (you might guess where I am working, at this point :D) >> and the radiation areas are *very* harsh. This is not a problem >> that can be solved just by shielding or some smart tricks (but we >> are diverging from my question). >> >> People way smarter than me tell me that no FPGA can withstand that >> kind of radiation for a reasonably long amount of time. >> >> The comment on the FPGA was just meant to say that I cannot mount >> in the proximity of the chip I am designing an FPGA to control it. >> Nothing more than that; you are right when you say that a CFC and >> an FPGA have nothing to do with each other :) >> >> thanks >> >> Francesco > > If you are at Cern, I would think there are many people there who > know more about your problem, than we do here... where's Jeroen > Belleman? > > George H. >
I'm right here. Francesco and I are even in the same beam instrumentation group (although I've never met him, I think). I have my own little problems at the moment. We're about to start up the accelerators and I have lots of work that can't wait. Jeroen Belleman
Reply by Joerg March 30, 20172017-03-30
On 2017-03-30 15:16, Francesco Zappon wrote:
> On Thursday, 30 March 2017 21:47:29 UTC+2, Joerg wrote: > > >>> https://www.dropbox.com/s/52nqfror1jhkqm0/venturini2013.pdf?dl=0 >> >> >> Thanks! That helps a great deal. The SNR numbers in there do not >> look very stellar but they claim to have achieved all objectives >> stated (using sub-ranging though). > > Thanks JM for posting it before me! > > I was not directly involved with the project, but from the notes I > found around it seems that the main "problems" they had with the > first version (the one in the article) were: - too much leakage
Maybe you should then look into SOI like Phil suggested. Then guard rings and all the usual low-current tricks.
> (degrading the low current measurements) - the need of an FPGA to > operate the chip (to control it and readout the data) - some > linearity issues >
Linearity will always be tough because of your 120dB. FPGA could be done in space. Work together with Gerhard maybe? He is located close to you and is self-employed as far as I know.
> >> >> Francesco, I am wondering what you'd like to improve above and >> beyond what these guys did? Is it the sub-ranging and subsequent >> SNR trade-off that you don't like? > > I don't know if I can really say I want to "improve" it. The chip > itself was working quite nice, but for several reasons (I can > explain, but it would take a long post and it is not super-relevant > to the discussion here) we need a new version with a new technology. >
If it is more or less a transfer from an obsolete technology to a new one for foundry reasons and such I'd talk to an analog IC design house.
> Now, I can keep the same approach (no problem on my side) but > changing technology node means doing a redesign and re-dimension of > the OTA, for starters. And this is where I struggle, because I am a > bit in the dark about how to "obtain" the specs of the amplifier. >
I can't imagine going to another node being a large obstacle. You can always use larger geometries as you did before, it's just the minimum that is now lower. Plus of course process differences but that is where a good IC design house helps. We always used those for IC designs, never went it alone.
> But I think I might be starting from the wrong point (after reading > the posts here): I probably should start with the OpAmp as a black > box and consider it ideal, and from there calculate the behavior of > the circuit in ideal conditions; and after this, probably the OpAmp > becomes a bit more straightforward. >
Just keep in mind that in the real world nothing is ideal and you will always have offset, offset drift, offset tempco and such effects.
>> >> If you really want to use a I/F concept (which as others have >> hinted may not be the optimum here) there are V/F converters where >> the manufacturer claims 6 decades which corresponds to 120dB: >> >> http://www.ti.com/lit/ds/symlink/vfc320.pdf >> >> This would have to be preceded by a low noise TIA for a current to >> voltage conversion and those architectures are described in the >> field of pre-biased photodiodes. Like here: >> >> http://electrooptical.net/www/frontends/frontends.pdf > > Thanks for all the info. I have some reading to do! >
It sure is a nice engineering challenge. Those are the things that keep us young :-) -- Regards, Joerg http://www.analogconsultants.com/
Reply by Joerg March 30, 20172017-03-30
On 2017-03-30 14:55, Gerhard Hoffmann wrote:
> Am 30.03.2017 um 21:58 schrieb Joerg: >> On 2017-03-30 11:25, Gerhard Hoffmann wrote: > >>> But it surprised me that even robust things like voltage >>> regulators are affected. >>> >> >> Even space-rated ones? > >> ... >> http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548 >> >> ... > > The documentation of the ST RHFL4913 & friends mentions exactly this, > including the workaround with the large output capacitors. >
Can't find the P/N RHFL4913 but yes, of course you need sufficient output caps in such an application. Then with many LDOs there is often inadequate stability and those I would never use in hi-rel. -- Regards, Joerg http://www.analogconsultants.com/
Reply by George Herold March 30, 20172017-03-30
On Thursday, March 30, 2017 at 6:17:04 PM UTC-4, Francesco Zappon wrote:
> On Thursday, 30 March 2017 21:47:29 UTC+2, Joerg wrote: > > > > > https://www.dropbox.com/s/52nqfror1jhkqm0/venturini2013.pdf?dl=0 > > > > > > Thanks! That helps a great deal. The SNR numbers in there do not look > > very stellar but they claim to have achieved all objectives stated > > (using sub-ranging though). > > Thanks JM for posting it before me! > > I was not directly involved with the project, but from the notes I found around it seems that the main "problems" they had with the first version (the one in the article) were: > - too much leakage (degrading the low current measurements) > - the need of an FPGA to operate the chip (to control it and readout the data) > - some linearity issues > > > > > > Francesco, I am wondering what you'd like to improve above and beyond > > what these guys did? Is it the sub-ranging and subsequent SNR trade-off > > that you don't like? > > I don't know if I can really say I want to "improve" it. The chip itself was working quite nice, but for several reasons (I can explain, but it would take a long post and it is not super-relevant to the discussion here) we need a new version with a new technology. > > Now, I can keep the same approach (no problem on my side) but changing technology node means doing a redesign and re-dimension of the OTA, for starters. And this is where I struggle, because I am a bit in the dark about how to "obtain" the specs of the amplifier. > > But I think I might be starting from the wrong point (after reading the posts here): I probably should start with the OpAmp as a black box and consider it ideal, and from there calculate the behavior of the circuit in ideal conditions; and after this, probably the OpAmp becomes a bit more straightforward.
Hmm, I guess a lot depends on where the problems are. Are the caps in the silicon? (could they be external?) Radiation damage seems like it would cause leakage everywhere.. (~proportional to area.) George H.
> > > > > > If you really want to use a I/F concept (which as others have hinted may > > not be the optimum here) there are V/F converters where the manufacturer > > claims 6 decades which corresponds to 120dB: > > > > http://www.ti.com/lit/ds/symlink/vfc320.pdf > > > > This would have to be preceded by a low noise TIA for a current to > > voltage conversion and those architectures are described in the field of > > pre-biased photodiodes. Like here: > > > > http://electrooptical.net/www/frontends/frontends.pdf > > Thanks for all the info. I have some reading to do! > > Francesco
Reply by Francesco Zappon March 30, 20172017-03-30
On Thursday, 30 March 2017 21:47:29 UTC+2, Joerg  wrote:


> > https://www.dropbox.com/s/52nqfror1jhkqm0/venturini2013.pdf?dl=0 > > > Thanks! That helps a great deal. The SNR numbers in there do not look > very stellar but they claim to have achieved all objectives stated > (using sub-ranging though).
Thanks JM for posting it before me! I was not directly involved with the project, but from the notes I found around it seems that the main "problems" they had with the first version (the one in the article) were: - too much leakage (degrading the low current measurements) - the need of an FPGA to operate the chip (to control it and readout the data) - some linearity issues
> > Francesco, I am wondering what you'd like to improve above and beyond > what these guys did? Is it the sub-ranging and subsequent SNR trade-off > that you don't like?
I don't know if I can really say I want to "improve" it. The chip itself was working quite nice, but for several reasons (I can explain, but it would take a long post and it is not super-relevant to the discussion here) we need a new version with a new technology. Now, I can keep the same approach (no problem on my side) but changing technology node means doing a redesign and re-dimension of the OTA, for starters. And this is where I struggle, because I am a bit in the dark about how to "obtain" the specs of the amplifier. But I think I might be starting from the wrong point (after reading the posts here): I probably should start with the OpAmp as a black box and consider it ideal, and from there calculate the behavior of the circuit in ideal conditions; and after this, probably the OpAmp becomes a bit more straightforward.
> > If you really want to use a I/F concept (which as others have hinted may > not be the optimum here) there are V/F converters where the manufacturer > claims 6 decades which corresponds to 120dB: > > http://www.ti.com/lit/ds/symlink/vfc320.pdf > > This would have to be preceded by a low noise TIA for a current to > voltage conversion and those architectures are described in the field of > pre-biased photodiodes. Like here: > > http://electrooptical.net/www/frontends/frontends.pdf
Thanks for all the info. I have some reading to do! Francesco
Reply by Francesco Zappon March 30, 20172017-03-30
On Thursday, 30 March 2017 19:14:47 UTC+2, Tim Wescott  wrote:

Hi Tim,

> > If you have the bandwidth for the data, using a sigma-delta modulator on > the front end may work better -- just output raw or only lightly > processed bits from the 1-bit ADC, and do the actual processing somewhere > at a lower radiation level.
[cut]
> > I'm thinking like a system-level engineer, and part of that job entails > re-thinking previous assumptions. I'm always confused at this stage of a > project, or at least find myself faced with more choices than I'd prefer. > > Basically, at this stage, you do some feasibility studies of each > approach, and ask yourself which ones are better. Since you're doing an > upgrade of an existing system, you want to give a lot of weight to what's > already there.
thanks a lot for the tips!
> > And it sounds like you're a junior member of the team, so someone else > may have already thought of all of this and either determined from first > principles that the current approach is best, or they're married to it > and won't budge even if it's the worst. So at your level you may not get > to make the decision to change at all (but if you think some other > approach might be better you should prepare your mind to not be dismayed > by any answer, and then ask).
The choice of whether changing approach or not is also due to time constraints. But anyway, thanks for any suggestion so far! Francesco
Reply by Francesco Zappon March 30, 20172017-03-30
On Thursday, 30 March 2017 20:43:34 UTC+2, George Herold  wrote:

> > If you are at Cern, I would think there are many people there who know more > about your problem, than we do here... where's Jeroen Belleman?
You are right. Many experts around. Sadly, everyone is busy and I am not in direct contact with them on a daily basis, so it is difficult to get some collaboration going. But we are working on it :) Francesco
Reply by Gerhard Hoffmann March 30, 20172017-03-30
Am 30.03.2017 um 21:58 schrieb Joerg:
> On 2017-03-30 11:25, Gerhard Hoffmann wrote:
>> But it surprised me that even robust things like voltage >> regulators are affected. >> > > Even space-rated ones?
> ... > http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548 > ...
The documentation of the ST RHFL4913 & friends mentions exactly this, including the workaround with the large output capacitors. cheers, Gerhard
Reply by March 30, 20172017-03-30
  
I'm not an IC designer, but I used to pal around with some. First you need to do the chip on a SOI process and not bulk. Second, use processes with wider features by preference. 

I-to-F is actually reasonably nice, since it uses time and frequency and is immune to voltage offsets. Much better than V-F. 

Cheers

Phil Hobbs
Reply by Joerg March 30, 20172017-03-30
On 2017-03-30 11:25, Gerhard Hoffmann wrote:
> Am 30.03.2017 um 16:16 schrieb Francesco Zappon: >> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann wrote: > >> I will give a general answer valid also for the others that commented >> on radiation hardness: we are operating with a 7 TeV beam of protons >> (you might guess where I am working, at this point :D) and the >> radiation areas are *very* harsh. This is not a problem that can be >> solved just by shielding or some smart tricks (but we are diverging >> from my question). >> >> People way smarter than me tell me that no FPGA can withstand that >> kind of radiation for a reasonably long amount of time. >> >> The comment on the FPGA was just meant to say that I cannot mount in >> the proximity of the chip I am designing an FPGA to control it. >> Nothing more than that; you are right when you say that a CFC and an >> FPGA have nothing to do with each other :) > > I assume then that you are abt. 2 or 3 hours by car from me in the > south/western direction. > > Yes, if the FPGA gets warm from the radiation, that won't work. :-) > But good enough for space probes or devices on the ISS. After all, > there live some people. SEUs happen there, and it's bad if you lose > the counter that has yourtime/position in orbit. > > But it surprised me that even robust things like voltage > regulators are affected. >
Even space-rated ones? http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slyt532d http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548 http://www.linear.com/parametric/Space_Qualified_Linear_Regulators http://www.linear.com/parametric/Space_Qualified_Switching_Regulators I found the old uA723 to be of cast-iron behavior in nasty environments but I don't know about its formal radiation tolerance. -- Regards, Joerg http://www.analogconsultants.com/