Reply by Kevin Aylward April 19, 20172017-04-19
wrote in message 
news:71962b8c-adb7-4bed-a9e8-379820bb75d9@googlegroups.com...

On Wednesday, April 19, 2017 at 3:01:09 PM UTC+2, Kevin Aylward wrote:
> >wrote in message > >news:c00eb16f-9944-4f7f-a049-646e1eb0e350@googlegroups.com...
> It uses different algos
>BTW, do you, by chance, know what LTspice tries to tell us >with messages like these?
>|| Changing Tseed to 1e-016 >|| Heightened Def Con from 3e-010 ++++++++++++to 3.3e-009
Looks like Mikes randomly deciding whether or not to nuke Iran. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
Reply by April 19, 20172017-04-19
On Wednesday, April 19, 2017 at 3:01:09 PM UTC+2, Kevin Aylward wrote:
> >wrote in message > >news:c00eb16f-9944-4f7f-a049-646e1eb0e350@googlegroups.com...
[..]
> >| Original .options: > >| .OPTIONS GMIN=1E-9 ITL4=5000 PIVTOL=1E-9 RELTOL=0.0001 RSHUNT=1E7 > >METHOD=GEAR MAXORD=2 > | .TRAN 1E-9 0.0005 0 1E-7 UIC > > >LTspice options (alternate solver): > >.options reltol=1m method=gear nomarch > >.tran 0 500u 10u uic > > Now rerun LTspice with a blank setting for max time step. > Then check if the waveform is ok.
The above .tran line already has TMAX blank. The "10u" is TSTART, the time when to start saving data (I skip the transient at the start). Or did you mean something else?
> You usually need to let LTSpice do what it wants to do > for any comparison to be valid.
I think I did.
> It uses different algos
BTW, do you, by chance, know what LTspice tries to tell us with messages like these? || Changing Tseed to 1e-016 || Heightened Def Con from 3e-010 ++++++++++++to 3.3e-009 -marcel
Reply by Kevin Aylward April 19, 20172017-04-19
>wrote in message >news:c00eb16f-9944-4f7f-a049-646e1eb0e350@googlegroups.com...
On Wednesday, April 19, 2017 at 7:34:35 AM UTC+2, Tim Williams wrote:
> "Kevin Aylward" <kevinRemovAT@kevinaylward.co.uk> wrote in message > news:J8mdnd0OuafMvmjFnZ2dnUU7-K3NnZ2d@giganews.com... > > This one transistor circuit just don't cut it for me. I would need to > > see > > a much more serious design to make any conclusions as to the > > speed/convergence comparison of LTSpice and NGSpice. > > May I offer you guys a more complicated, but still "all cards on the > table" > discrete, circuit to test with, then? > > Schematic screenshot: > https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackSch.png > Netlist: > https://www.seventransistorlabs.com/Images/Discrete%20Flyback.nsx > (YMMV with other TL431 models; this is tuned for the TI one, included. > Other credits: MOSFET model is Motorola, SB160 is Thomatronik GmbH, > 2N3904/6 > are... dunno, Fairchild maybe?) > > Output, overall: > https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackWave1.png > Zoom (last 10us): > https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackWave2.png > > Simulation time: it's Altium, so it's terrible. Nevermind that. > > LTSpice: seems to run fine but change RSHUNT --> 1/GSHUNT. Doesn't seem > to > be using more than one core; perhaps a bigger circuit is necessary? > > Tim > > -- > Seven Transistor Labs, LLC > Electrical Engineering Consultation and Contract Design > Website: http://seventransistorlabs.com
>Perfectly documented! >Unfortunately MUCH too small.
>LTspice: 8.221 seconds. >NGSPICE: 1.450 seconds. >SuperSpice: (don't have it on this machine)
Note that SS automatically prints out the simulation clock time at the end of each run type.
>| Original .options: >| .OPTIONS GMIN=1E-9 ITL4=5000 PIVTOL=1E-9 RELTOL=0.0001 RSHUNT=1E7 >METHOD=GEAR MAXORD=2
| .TRAN 1E-9 0.0005 0 1E-7 UIC
>LTspice options (alternate solver): >.options reltol=1m method=gear nomarch >.tran 0 500u 10u uic
Now rerun LTspice with a blank setting for max time step. Then check if the waveform is ok. You usually need to let LTSpice do what it wants to do for any comparison to be valid. It uses different algos -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
Reply by April 19, 20172017-04-19
On Wednesday, April 19, 2017 at 7:34:35 AM UTC+2, Tim Williams wrote:
> "Kevin Aylward" <kevinRemovAT@kevinaylward.co.uk> wrote in message > news:J8mdnd0OuafMvmjFnZ2dnUU7-K3NnZ2d@giganews.com... > > This one transistor circuit just don't cut it for me. I would need to see > > a much more serious design to make any conclusions as to the > > speed/convergence comparison of LTSpice and NGSpice. > > May I offer you guys a more complicated, but still "all cards on the table" > discrete, circuit to test with, then? > > Schematic screenshot: > https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackSch.png > Netlist: > https://www.seventransistorlabs.com/Images/Discrete%20Flyback.nsx > (YMMV with other TL431 models; this is tuned for the TI one, included. > Other credits: MOSFET model is Motorola, SB160 is Thomatronik GmbH, 2N3904/6 > are... dunno, Fairchild maybe?) > > Output, overall: > https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackWave1.png > Zoom (last 10us): > https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackWave2.png > > Simulation time: it's Altium, so it's terrible. Nevermind that. > > LTSpice: seems to run fine but change RSHUNT --> 1/GSHUNT. Doesn't seem to > be using more than one core; perhaps a bigger circuit is necessary? > > Tim > > -- > Seven Transistor Labs, LLC > Electrical Engineering Consultation and Contract Design > Website: http://seventransistorlabs.com
Perfectly documented! Unfortunately MUCH too small. LTspice: 8.221 seconds. NGSPICE: 1.450 seconds. SuperSpice: (don't have it on this machine) | Original .options: | .OPTIONS GMIN=1E-9 ITL4=5000 PIVTOL=1E-9 RELTOL=0.0001 RSHUNT=1E7 METHOD=GEAR MAXORD=2 | .TRAN 1E-9 0.0005 0 1E-7 UIC LTspice options (alternate solver): .options reltol=1m method=gear nomarch .tran 0 500u 10u uic NGSPICE options: .options reltol=1m method=gear .tran 0 500u 10u 20n uic -marcel
Reply by Kevin Aylward April 19, 20172017-04-19
>wrote in message >news:179a7510-159e-4454-bf05-89d86da7cdb7@googlegroups.com...
> >LTspice bogs down for larger circuits, e.g. the mcnc or ISCAS > >benchmark sets. Do you have a netlist that would convince you? > > I have a SMPS example in SuperSpice that I compared with LTSPice maybe, 15 > years ago. LTSpice was something like 3 times faster.
>Is that CurrentModeController.sss? It indeed runs in 6.964s. However, >when I try it, it gives suspicious results (false gate triggers) in >SuperSpice (as is), LTspice and NGSPICE. In NGSPICE it runs very >slowly, around 2.527 seconds, because I didn't want to tune the >options yet.
Yes. However, I could have another go and do another model from scratch, could probably speed it up a fair chunk. Overtime, I have his habit of breaking stuff that worked, so its possible its now now strange things. Recently, I noticed that I have inadvertently removed the sweep of resistance in dc sweep setup list box. Now fixed. Note, a lot of the SS examples, are where I just wanted to create demos that worked, rather than a viable real "design". They are meant to demonstrate all the features, and the sort of problems you can solve in SS. I think they are way more extensive than any other simulators examples. There is a lot of behavioural, system examples. Most haven't been updated since they were crated. That example actually has an external gate resister to get convergence, but since then I added RG to the mosfet core model itself. My mosfet 1 now supports an "enhanced" LTSpice VDMOS mode. http://www.anasoft.co.uk/MOS1Model.htm
>> In 2000, it was a real big deal to get practical SMPS sims going. Now, my >> laptop does 90 GFlops, with 16GB of ram, and does it in about 7 secs in >> SuperSpice, so speed for board level stuff is not so important now. For >> analog ASIC, its never fast enough.
>I don't think 7seconds is at all satisfactory when having >feedback control with 100ms time constants, or when doing >a PFC with 20 Hz bandwidth.
Its all relative though. Using my aforementioned expensive $100k per seat, per year, Cadence suite, I often run simulations that last 1/2 or 1 hour. Main top levels can take a day, some several days. PSNoise is the main killer. I started with a HP85 in around 1982 for AC analyses, moving up to DOS PSpice in 1985 on an XT, so I am sure you can appreciate, that today, 7 secs for a SMPS, is sheer Luxury. I used to dreeeeeem of such a life when I was knee high. On that HP, I wrote my first complex number Gaussian elimination with partial pivoting routine. I also learned how to move graphic objects on screen by getting the prior background and XORing stuff. However, all this software stuff is pissing about really. After 150k lines of SS C++ code, I am still just a hack. My expertise is really only in analog design.
>> I have a working ngspice-26 so I might give it go. I actually passed on >> my >> xspice code model code for the John Chan et la. Hysteresis core model to >> Paolo Nenzi many moons ago.
>Your name is still listed in the manual, but I didn't know you >worked on the Chan Core model.
I wrote it from scratch after Mike was lording it over everyone with his LT implementation. I actually paid &pound;30 to get the paper! Anyone that wants my full source code to my xspice version is welcome to it. Just email me. It would be worth copying in my ASK routines for BSIm3 and BSim4 to ngspice. I added the code so that all transient terminal currents (d, g, b,s) are available. The original only has drain. Its an indispensible feature.
> >No it does not, unfortunately. However, my VTune sessions show > >that, in NGSPICE at least, most time is spent in the system > >matrix load phase, not in solving this matrix.
> This depends on the size of the circuit. Are you a pro?
>These were small matrices, and then load time dominates. I have >the numbers when you are interested. For 1000's of transistors >(ISCAS and MCNC) solving becomes dominant, but then NGSPICE >uses KLU (which LTspice doesn't have).
I have considered setting up the latest ngspice to work better with SS. Like having it as an alternative, engine. [..]
> >My remark didn't make sense, as I agree that TRTOL should not > >be too large. A value of 1 is fine. > > I consider the setting of TRTOL to be somewhat controversial. > >> Ken Kundert (Spectre author) wrote a paper with the view that TRTOL >> should >> be set higher, nearer to the spice3 default 7 value and tighten up the >> accuracy settings, say to 100u or 10u.
>Which paper is that?
I will see if I can dig it out.
> I manually set the best TRTOL and RETOL in my SuperSpice examples to get > an > optimum speed/accuracy trade-off. Typically I might use values of 2-4, and > accuracy 10u-100u
>I think TRTOL=1 and RELTOL = 1m is fine, but I'll remember this when using >SuperSpice.
TRTOL=1 is a safe option. For things like Sigma-Dalta, much more risky to increase, especially the tolerance. Its the bit about chaos that does it :-) My SS 1st order S-D is ok with retol=1m and trtol=5, but the 2nd order S-D has something like trtol=1 and relto=100u. It can really mess-up with looser values. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
Reply by Tim Williams April 19, 20172017-04-19
"Kevin Aylward" <kevinRemovAT@kevinaylward.co.uk> wrote in message 
news:J8mdnd0OuafMvmjFnZ2dnUU7-K3NnZ2d@giganews.com...
> This one transistor circuit just don't cut it for me. I would need to see > a much more serious design to make any conclusions as to the > speed/convergence comparison of LTSpice and NGSpice.
May I offer you guys a more complicated, but still "all cards on the table" discrete, circuit to test with, then? Schematic screenshot: https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackSch.png Netlist: https://www.seventransistorlabs.com/Images/Discrete%20Flyback.nsx (YMMV with other TL431 models; this is tuned for the TI one, included. Other credits: MOSFET model is Motorola, SB160 is Thomatronik GmbH, 2N3904/6 are... dunno, Fairchild maybe?) Output, overall: https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackWave1.png Zoom (last 10us): https://www.seventransistorlabs.com/Images/AltiumDiscreteFlybackWave2.png Simulation time: it's Altium, so it's terrible. Nevermind that. LTSpice: seems to run fine but change RSHUNT --> 1/GSHUNT. Doesn't seem to be using more than one core; perhaps a bigger circuit is necessary? Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Reply by April 18, 20172017-04-18
On Tuesday, April 18, 2017 at 8:15:10 PM UTC+2, Kevin Aylward wrote:
> wrote in message > news:406c7b9d-ce9d-4458-b5f3-8ca3cd5407f6@googlegroups.com... > > On Monday, April 17, 2017 at 10:19:38 PM UTC+2, Kevin Aylward wrote: > > wrote in message > > news:605d4f15-d117-4df6-b4d9-274b745b2021@googlegroups.com...
[..]
> > www.linear.com/docs/46028 > > > > Snippet: > > > > " Ideally, the addresses of the > >> data required for a calculation would > >> data can be efficiently loaded, allowing the FPU to operate with the
[..]
> >> pipeline full." > > >That makes perfect sense, but the proof of the pudding is in the eating. > > LTSpice, has been proven to be the fasted, "non pro tool", on Windows for > many years.
That statement needs no proof. I meant proof for the snippet's claim that pointer chasing is the main cause of inefficiency in SPICE.
> There are of course, products like FastSpice from Berkeley Design > Automation, now owned by Mentor. It can reliably do millions of transistors. > Its Linux/Unix though.
I don't doubt that. [..]
> >LTspice bogs down for larger circuits, e.g. the mcnc or ISCAS > >benchmark sets. Do you have a netlist that would convince you? > > I have a SMPS example in SuperSpice that I compared with LTSPice maybe, 15 > years ago. LTSpice was something like 3 times faster.
Is that CurrentModeController.sss? It indeed runs in 6.964s. However, when I try it, it gives suspicious results (false gate triggers) in SuperSpice (as is), LTspice and NGSPICE. In NGSPICE it runs very slowly, around 2.527 seconds, because I didn't want to tune the options yet.
> In 2000, it was a real big deal to get practical SMPS sims going. Now, my > laptop does 90 GFlops, with 16GB of ram, and does it in about 7 secs in > SuperSpice, so speed for board level stuff is not so important now. For > analog ASIC, its never fast enough.
I don't think 7seconds is at all satisfactory when having feedback control with 100ms time constants, or when doing a PFC with 20 Hz bandwidth.
> I have a working ngspice-26 so I might give it go. I actually passed on my > xspice code model code for the John Chan et la. Hysteresis core model to > Paolo Nenzi many moons ago.
Your name is still listed in the manual, but I didn't know you worked on the Chan Core model.
> >No it does not, unfortunately. However, my VTune sessions show > >that, in NGSPICE at least, most time is spent in the system > >matrix load phase, not in solving this matrix.
> This depends on the size of the circuit. Are you a pro?
These were small matrices, and then load time dominates. I have the numbers when you are interested. For 1000's of transistors (ISCAS and MCNC) solving becomes dominant, but then NGSPICE uses KLU (which LTspice doesn't have).
> I routinely run analog ASIC simulations in my day job of maybe, 20,000 to > 100,000 nets. Large circuits get really bogged down in solving the matrix.
Definitely. [..]
> >My remark didn't make sense, as I agree that TRTOL should not > >be too large. A value of 1 is fine. > > I consider the setting of TRTOL to be somewhat controversial. > > Ken Kundert (Spectre author) wrote a paper with the view that TRTOL should > be set higher, nearer to the spice3 default 7 value and tighten up the > accuracy settings, say to 100u or 10u.
Which paper is that? As far as the source code goes, TRTOL always multiplies with the normal TOL value (sum of volttol and chargetol). It does trickier stuff when the compile option NEWTRUNC is enabled, but that is not the case in NGSPICE. Actually. my tests said that NEWTRUNC is not doing any good.
> I did do fair bit of experimenting on this for SMPS and Sigma-Delta > Converters where it definitely all goes to pot with a value of 7. I can't > say I really agree with Ken in general though.
I think I again have to agree with you.
> I manually set the best TRTOL and RETOL in my SuperSpice examples to get an > optimum speed/accuracy trade-off. Typically I might use values of 2-4, and > accuracy 10u-100u
I think TRTOL=1 and RELTOL = 1m is fine, but I'll remember this when using SuperSpice. -marcel
Reply by Kevin Aylward April 18, 20172017-04-18
wrote in message 
news:3e3875a4-5d65-419c-a571-0fa326aa5d59@googlegroups.com...

On Monday, April 17, 2017 at 10:21:06 PM UTC+2, Kevin Aylward wrote:
> wrote in message > news:75bb9bd2-f0ef-4dd2-9759-b07dc896c4e0@googlegroups.com...
[..]
> >That is cheating in the context of a benchmark, but LTspice > >runs it in 252 ms here (normal solver, with .save line). > > What is the cheat? > >> LTSpice uses its own algorithms to get the best speed and accuracy. Max >> step >> time should usually be left as default for most simulations. > >> A bench mark means letting each system run as it wants to run.
>I meant that it would be cheating if I set the options for NGSPICE >differently for those of LTspice, especially for those options that >have a large influence on run speed.
I disagree. Its because the options can have a large effect on speed, that its misleading to do make then the same. LTSpice does a lot of stuff automatically, such that if you set it the same as Spice3, you can cripple it. Its not a fair test. LTSpice is very good at getting fast results without any user input. To know whether one spice is faster/accurate than another, you need to set each one to the setting that make each one as fast/accurate as possible.
> >I am sure most people know that. > >> Apparently not. Its probably the most typical issue I get from those that >> use SuperSpice. > >> Where do you get your information from?
>My colleagues.
How many colleagues do you have that respond to spice customer support? :-) Well, sonny... I have been at this some while, although not as long as old man Jim T. I do have a pretty good idea of the spice knowledge of fellow analog IC designers, and the capabilities of spice customers as well. I also have experience of receiving initial support from the Cadence Application Engineers when trying to resolve technical problems of my own, that provides ample evidence to the level of anticipated answers to questions... I would say, that your colleagues are a rather special set. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html www.kevinaylward.co.uk
Reply by Kevin Aylward April 18, 20172017-04-18
wrote in message 
news:406c7b9d-ce9d-4458-b5f3-8ca3cd5407f6@googlegroups.com...

On Monday, April 17, 2017 at 10:19:38 PM UTC+2, Kevin Aylward wrote:
> wrote in message > news:605d4f15-d117-4df6-b4d9-274b745b2021@googlegroups.com... > > > > > -- > > >> Grizzly H. > > > > >That is really good! > > > > >* LTspice Alternate Solver 33.129 seconds > > >* LTspice normal solver 22.392 seconds > > >* LTspice normal solver with .save 13.306 seconds > > >* NGSPICE 9.660 seconds > > >* NGSPICE with .save 9.002 seconds > > > > This don't make any sense to me. LTSpice should be running several times > > faster than NGSpice. > > >Because? > > Because LTSpice does compile on run to resolve memory addresses for every > individual circuit. > > For the lase 15 years or so it has been 3 times fast as anything else on > Windows. > > I don't keep track of it much, other then noting that it added multicore > support. > > >This is a properly compiled and optimized (for AVX > >and open-mp) console-based NGSPICE from the latest > >Git branch. It has XSPICE integrated and has my custom > >mods for power-electronics (but these shouldn't cut > >in here). It has a Berkeley parallel BJT model, > >but that is only slowing it down here as there is only > >a single transistor in this circuit. > > None on this addresses the special nature of the LTSpice assembler > > It's explained here: > > www.linear.com/docs/46028 > > Snippet: > > " Ideally, the addresses of the >> data required for a calculation would >> be known ahead of calculation time so >> that data can be efficiently fetched and >> the FPU doesn&rsquo;t have to wait for it. >> LTspice eliminates the overhead in getting >> the data to the FPU with self-authoring >> assembly language source written at >> run time, after matrix memory has been >> allocated, and the addresses returned >> from malloc() are known. This late authored >> code can resolve concrete >> matrix element addresses in line with >> LTspice eliminates the overhead in getting the data to the FPU with >> self-authoring >> assembly language source written at run time, after matrix memory has >> been >> allocated, and the addresses returned from malloc() are known. This >> late-authored >> code can resolve concrete matrix element addresses in line with the code >> so >> the >> data can be efficiently loaded, allowing the FPU to operate with the >> pipeline full."
>That makes perfect sense, but the proof of the pudding is in the eating.
LTSpice, has been proven to be the fasted, "non pro tool", on Windows for many years. There are of course, products like FastSpice from Berkeley Design Automation, now owned by Mentor. It can reliably do millions of transistors. Its Linux/Unix though.
> >> Are you running default settings in LTSpice, or say, setting a minimum > >> step > >> time? > > >I use the PH settings, but added "nomarch". > >Plotwinsize is NOT used, it has no effect (here). > > >> It is possible to override stuff in LTSpice, such that it aint running > >> anything like as fast as it should. Its also possible to speed it up a > >> bit > >> by changing some settings for some circuits. > > >I think LTspice runs as fast as it can here (see also the > >other timings presented in this thread). NGSPICE is running > >faster that you seem to expect. > >> This one transistor circuit just don't cut it for me. I would need to see >> a >> much more serious design to make any conclusions as to the >> speed/convergence >> comparison of LTSpice and NGSpice.
>LTspice bogs down for larger circuits, e.g. the mcnc or ISCAS >benchmark sets. Do you have a netlist that would convince you?
I have a SMPS example in SuperSpice that I compared with LTSPice maybe, 15 years ago. LTSpice was something like 3 times faster. In 2000, it was a real big deal to get practical SMPS sims going. Now, my laptop does 90 GFlops, with 16GB of ram, and does it in about 7 secs in SuperSpice, so speed for board level stuff is not so important now. For analog ASIC, its never fast enough. I have a working ngspice-26 so I might give it go. I actually passed on my xspice code model code for the John Chan et la. Hysteresis core model to Paolo Nenzi many moons ago.
> Does the latest version of NGspice do the aforementioned just in time > assemble? Has it done anything to its convergence algorithms?
>No it does not, unfortunately. However, my VTune sessions show >that, in NGSPICE at least, most time is spent in the system >matrix load phase, not in solving this matrix.
This depends on the size of the circuit. Are you a pro? I routinely run analog ASIC simulations in my day job of maybe, 20,000 to 100,000 nets. Large circuits get really bogged down in solving the matrix.
> > > The spice default Spice3 value of trtol is 7. I think LTSpice might use > > 1, > > I > > use 1 in SS. The 1 setting can slow it down by a factor of 3, but for > > some > > switching circuits, a value of 7 generates way too large errors. > > >A too high value of TRTOL can also slow down some circuits. > > Maybe in some vague theory, never, ever, seen that happen though.
>My remark didn't make sense, as I agree that TRTOL should not >be too large. A value of 1 is fine.
I consider the setting of TRTOL to be somewhat controversial. Ken Kundert (Spectre author) wrote a paper with the view that TRTOL should be set higher, nearer to the spice3 default 7 value and tighten up the accuracy settings, say to 100u or 10u. I did do fair bit of experimenting on this for SMPS and Sigma-Delta Converters where it definitely all goes to pot with a value of 7. I can't say I really agree with Ken in general though. I manually set the best TRTOL and RETOL in my SuperSpice examples to get an optimum speed/accuracy trade-off. Typically I might use values of 2-4, and accuracy 10u-100u -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
Reply by April 17, 20172017-04-17
On Monday, April 17, 2017 at 10:21:06 PM UTC+2, Kevin Aylward wrote:
> wrote in message > news:75bb9bd2-f0ef-4dd2-9759-b07dc896c4e0@googlegroups.com...
[..]
> >That is cheating in the context of a benchmark, but LTspice > >runs it in 252 ms here (normal solver, with .save line). > > What is the cheat? > > LTSpice uses its own algorithms to get the best speed and accuracy. Max step > time should usually be left as default for most simulations. > > A bench mark means letting each system run as it wants to run.
I meant that it would be cheating if I set the options for NGSPICE differently for those of LTspice, especially for those options that have a large influence on run speed. I interpret your last statement that one should optimize the settings for each simulator such that they run as fast as they can. That makes some sense, and the advantage for the reader is that they may learn something they didn't know yet.
> >I am sure most people know that. > > Apparently not. Its probably the most typical issue I get from those that > use SuperSpice. > > Where do you get your information from?
My colleagues. -marcel