Reply by Phil Hobbs August 10, 20162016-08-10
On 08/09/2016 11:10 PM, Chris Jones wrote:
> On 10/08/2016 08:25, Phil Hobbs wrote: >> On 08/09/2016 02:50 PM, Phil Hobbs wrote: >>> On 08/09/2016 01:26 PM, Jim Thompson wrote: >>>> Phil, What makes a JFET less noisy than a enhancement mode CMOS >>>> device? >>>> >>>> Would a depletion mode CMOS device be quieter? >>>> >>>> ...Jim Thompson >>>> >>> >>> I don't know in any great detail. The physics of the carriers in the >>> channel will be vaguely similar except that there's no chemical >>> potential to drive the formation of a depletion region there is with a >>> JFET or BJT. I suspect that there are a lot more traps and surface >>> states when you have all those layers that the E field has to go >>> through, compared with a nice buried epitaxial junction. >>> >>> That's backed up by the horrible 1/f noise of MOSFETs, but of course >>> "traps and surface states" is the solid state guy's version of "market >>> sentiment and program trading" on the Friday stock market report. ;) >> >> It would be sort of interesting to look at the noise behaviour of >> lateral MOSFETs with their back gates pinned out separately. I bet the >> 1/f noise would be a lot less if you ran the back gate at the edge of >> forward bias. That would force all the channel conduction to happen >> well away from the Si-SiO2 interface. >> >> You can't get those parts any more, of course. > > Joerg recently pointed out a device that is still available (SST211). > >
Interesting, thanks. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by Chris Jones August 10, 20162016-08-10
On 10/08/2016 08:25, Phil Hobbs wrote:
> On 08/09/2016 02:50 PM, Phil Hobbs wrote: >> On 08/09/2016 01:26 PM, Jim Thompson wrote: >>> Phil, What makes a JFET less noisy than a enhancement mode CMOS >>> device? >>> >>> Would a depletion mode CMOS device be quieter? >>> >>> ...Jim Thompson >>> >> >> I don't know in any great detail. The physics of the carriers in the >> channel will be vaguely similar except that there's no chemical >> potential to drive the formation of a depletion region there is with a >> JFET or BJT. I suspect that there are a lot more traps and surface >> states when you have all those layers that the E field has to go >> through, compared with a nice buried epitaxial junction. >> >> That's backed up by the horrible 1/f noise of MOSFETs, but of course >> "traps and surface states" is the solid state guy's version of "market >> sentiment and program trading" on the Friday stock market report. ;) > > It would be sort of interesting to look at the noise behaviour of > lateral MOSFETs with their back gates pinned out separately. I bet the > 1/f noise would be a lot less if you ran the back gate at the edge of > forward bias. That would force all the channel conduction to happen > well away from the Si-SiO2 interface. > > You can't get those parts any more, of course.
Joerg recently pointed out a device that is still available (SST211).
Reply by Phil Hobbs August 9, 20162016-08-09
On 08/09/2016 02:50 PM, Phil Hobbs wrote:
> On 08/09/2016 01:26 PM, Jim Thompson wrote: >> Phil, What makes a JFET less noisy than a enhancement mode CMOS >> device? >> >> Would a depletion mode CMOS device be quieter? >> >> ...Jim Thompson >> > > I don't know in any great detail. The physics of the carriers in the > channel will be vaguely similar except that there's no chemical > potential to drive the formation of a depletion region there is with a > JFET or BJT. I suspect that there are a lot more traps and surface > states when you have all those layers that the E field has to go > through, compared with a nice buried epitaxial junction. > > That's backed up by the horrible 1/f noise of MOSFETs, but of course > "traps and surface states" is the solid state guy's version of "market > sentiment and program trading" on the Friday stock market report. ;)
It would be sort of interesting to look at the noise behaviour of lateral MOSFETs with their back gates pinned out separately. I bet the 1/f noise would be a lot less if you ran the back gate at the edge of forward bias. That would force all the channel conduction to happen well away from the Si-SiO2 interface. You can't get those parts any more, of course. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by Jim Thompson August 9, 20162016-08-09
On 9 Aug 2016 14:18:03 -0700, Winfield Hill <hill@rowland.harvard.edu>
wrote:

>Jim Thompson wrote... >> >>On 9 Aug 2016 12:18:14 -0700, Winfield Hill <hill@rowland.harvard.edu> >>wrote: >> >>>Jim Thompson wrote... >>>> >>>>>> Would a depletion mode CMOS device be quieter? >>>> >>>> I don't need high voltage, my supplies are +3.3V/-2V >>> >>> Jim, you really should get yourself a copy of AoE III >>> and read chapter 8. There we have loads of details >>> about what other IC op-amp designers have been able >>> to accomplish with their fabs. It's 120 pages of >>> good low-noise stuff. You can compare JFET and CMOS, >>> including 1/f noise breakpoint frequencies, and you >>> can quickly compare low- and high-voltage processes. >> >> I have a copy... but I've just skimmed it... too >> busy with real work... finally!! >> >> Super!! I'll read Chapter 8. THANKS! > > You can skip to Table 8.3, page 522 or thereabouts.
Do you address which companies provide foundry services? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website.
Reply by Winfield Hill August 9, 20162016-08-09
Jim Thompson wrote...
> >On 9 Aug 2016 12:18:14 -0700, Winfield Hill <hill@rowland.harvard.edu> >wrote: > >>Jim Thompson wrote... >>> >>>>> Would a depletion mode CMOS device be quieter? >>> >>> I don't need high voltage, my supplies are +3.3V/-2V >> >> Jim, you really should get yourself a copy of AoE III >> and read chapter 8. There we have loads of details >> about what other IC op-amp designers have been able >> to accomplish with their fabs. It's 120 pages of >> good low-noise stuff. You can compare JFET and CMOS, >> including 1/f noise breakpoint frequencies, and you >> can quickly compare low- and high-voltage processes. > > I have a copy... but I've just skimmed it... too > busy with real work... finally!! > > Super!! I'll read Chapter 8. THANKS!
You can skip to Table 8.3, page 522 or thereabouts. -- Thanks, - Win
Reply by Jim Thompson August 9, 20162016-08-09
On 9 Aug 2016 12:18:14 -0700, Winfield Hill <hill@rowland.harvard.edu>
wrote:

>Jim Thompson wrote... >> >>>> Would a depletion mode CMOS device be quieter? >> >> I don't need high voltage, my supplies are +3.3V/-2V > > Jim, you really should get yourself a copy of AoE III > and read chapter 8. There we have loads of details > about what other IC op-amp designers have been able > to accomplish with their fabs. It's 120 pages of > good low-noise stuff. You can compare JFET and CMOS, > including 1/f noise breakpoint frequencies, and you > can quickly compare low- and high-voltage processes.
I have a copy... but I've just skimmed it... too busy with real work... finally!! Super!! I'll read Chapter 8. THANKS! ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website.
Reply by Winfield Hill August 9, 20162016-08-09
Jim Thompson wrote...
> >>> Would a depletion mode CMOS device be quieter? > > I don't need high voltage, my supplies are +3.3V/-2V
Jim, you really should get yourself a copy of AoE III and read chapter 8. There we have loads of details about what other IC op-amp designers have been able to accomplish with their fabs. It's 120 pages of good low-noise stuff. You can compare JFET and CMOS, including 1/f noise breakpoint frequencies, and you can quickly compare low- and high-voltage processes. -- Thanks, - Win
Reply by Phil Hobbs August 9, 20162016-08-09
On 08/09/2016 01:26 PM, Jim Thompson wrote:
> Phil, What makes a JFET less noisy than a enhancement mode CMOS > device? > > Would a depletion mode CMOS device be quieter? > > ...Jim Thompson >
I don't know in any great detail. The physics of the carriers in the channel will be vaguely similar except that there's no chemical potential to drive the formation of a depletion region there is with a JFET or BJT. I suspect that there are a lot more traps and surface states when you have all those layers that the E field has to go through, compared with a nice buried epitaxial junction. That's backed up by the horrible 1/f noise of MOSFETs, but of course "traps and surface states" is the solid state guy's version of "market sentiment and program trading" on the Friday stock market report. ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by whit3rd August 9, 20162016-08-09
On Tuesday, August 9, 2016 at 10:40:36 AM UTC-7, George Herold wrote:
> On Tuesday, August 9, 2016 at 1:26:16 PM UTC-4, Jim Thompson wrote: > > Phil, What makes a JFET less noisy than a enhancement mode CMOS > > device?
> At some point I remember reading (AoE?) that there was more 1/f noise > in MosFet's... more crud in the gate or something like that.
The gate of a MOSFET is at the surface (and so is the channel); for a JFET, your gate and channel are under the silicon surface. Dirt on the surface is a major concern (and, of course, not repeatable nor easily specified).
Reply by Jim Thompson August 9, 20162016-08-09
On Tue, 9 Aug 2016 10:40:31 -0700 (PDT), George Herold
<gherold@teachspin.com> wrote:

>On Tuesday, August 9, 2016 at 1:26:16 PM UTC-4, Jim Thompson wrote: >> Phil, What makes a JFET less noisy than a enhancement mode CMOS >> device? >> >> Would a depletion mode CMOS device be quieter? > >At some point I remember reading (AoE?) that there was more 1/f noise >in MosFet's... more crud in the gate or something like that. It >seems like they are getting better and better at that... >Nice Cmos opamps these days. But still not as high a voltage as Jfet's... >I don't know why that is. > >George H. >> >> ...Jim Thompson
[snip] I don't need high voltage, my supplies are +3.3V/-2V ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website.