On Wed, 19 Aug 2015 06:37:07 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:
>On Tue, 18 Aug 2015 23:38:59 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
><111619124@umt.edu.pk> wrote:
>
>>Well guys, here is the NETLIST of my 3-bit ADC....sure it is not a very good looking one (my first complete ADC with only 2 weeks of LTspice experience) but it works :)
>>Here is the NETLIST. Please run it and tell me how much time does the simulation takes for , say , 10ms transient. Please tell ASAP :)
>
>You should post the .ASC file (it's text). Most people here can't run
>the netlist (actually .cir file) that you have posted.
>
>You have several syntax issues: (1) multiple declarations of the same
>Spice model and (2) calls to library paths that will be different for
>each of us.
>
And no model for BSB012N03LX3
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Reply by Jim Thompson●August 19, 20152015-08-19
On Tue, 18 Aug 2015 23:38:59 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
<111619124@umt.edu.pk> wrote:
>Well guys, here is the NETLIST of my 3-bit ADC....sure it is not a very good looking one (my first complete ADC with only 2 weeks of LTspice experience) but it works :)
>Here is the NETLIST. Please run it and tell me how much time does the simulation takes for , say , 10ms transient. Please tell ASAP :)
You should post the .ASC file (it's text). Most people here can't run
the netlist (actually .cir file) that you have posted.
You have several syntax issues: (1) multiple declarations of the same
Spice model and (2) calls to library paths that will be different for
each of us.
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Reply by MUHAMMAD FAHAD BHUTTA●August 19, 20152015-08-19
On 8/15/2015 11:27 PM, MUHAMMAD FAHAD BHUTTA wrote:
> On Saturday, 15 August 2015 06:59:56 UTC+5, MUHAMMAD FAHAD BHUTTA wrote:
>> Greetings people !
>>
>> So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple.
>>
>> Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using Instrument Amplifier to get better result but that is not a necessity)
>>
>> Now, the output is not as what we want (that is another issue with Quantizer but we can solve that later) but the time LTspice is taking to simulate the whole circuit is round about 10 minutes or something which is kind of an unacceptable ( giving a look at the transient response parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to start saving data, max time step 1ms , skip initial operating point solution; True). This is the best transient settings I did and it is still taking around 10minutes. And without this setting, the simulation time grows relatively high.
>>
>> Also , the CPU usage during simulation is 100% (means other programs are hard to run). Although the machine I am using is a SAMSUNG series 5 ultra book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is not the problem with CPU to handle a low level simulation.(BTW I burrowed it from a friend for some time till I get my new DELL XPS 13"...So don't blame me on buying an AMD)
>>
>> One more thing is that I used the simulation on my friend's core 2 duo desktop and it is taking almost the same time. Also on my friend's notebook which has 2nd generation core i3 processor and still the same time taken to simulate. RAM is not the issue though !
>>
>> So, Can any one please tell me what are the reasons? Is the circuit not properly optimized? Am I giving the wrong transient parameters ? Is this the CPU problem ? Any advice perhaps because I am relatively new to this spice simulation environment (only a month of little bit of experience).
>>
>> Thanks in advance :)
>
> Okay so here is the 8x3 encoder I am working on right now ( which I will be installing after Delta-Sigma Modulator.
>
> http://sub.allaboutcircuits.com/images/04258.png
>
> And here is the netlist
>
> * C:\Program Files (x86)\LTC\LTspiceIV\Draft3.asc
> R1 REF N005 100
> R2 N005 N008 100
> R3 N008 N011 100
> R4 N011 N014 100
> R5 N014 N017 100
> R6 N017 N020 100
> R7 N020 N023 100
> R8 N023 0 100
> XU1 IN N005 N002 N003 N004 LT1007
> XU2 IN N008 N002 N003 N007 LT1007
> XU3 IN N011 N002 N003 N010 LT1007
> XU4 IN N014 N002 N003 N013 LT1007
> XU5 IN N017 N002 N003 N016 LT1007
> XU6 IN N020 N002 N003 N019 LT1007
> XU7 IN N023 N002 N003 N022 LT1007
> XU8 0 N004 N001 XOR
> XU9 N004 N007 N006 XOR
> XU10 N007 N010 N009 XOR
> XU11 N010 N013 N012 XOR
> XU12 N013 N016 N015 XOR
> XU13 N016 N019 N018 XOR
> XU14 N019 N022 N021 XOR
> D1 N001 LSB 1N4148
> D2 N001 2SB 1N4148
> D3 N001 MSB 1N4148
> R9 MSB 0 1000
> R10 2SB 0 1000
> R11 LSB 0 1000
> D4 N006 MSB 1N4148
> D5 N006 2SB 1N4148
> D6 N009 MSB 1N4148
> D7 N009 LSB 1N4148
> D8 N012 MSB 1N4148
> D9 N015 2SB 1N4148
> D10 N015 LSB 1N4148
> D11 N018 2SB 1N4148
> D12 N021 LSB 1N4148
> V1 N002 0 7
> V2 0 N003 1
> .model D D
> .lib C:\Program Files (x86)\LTC\LTspiceIV\lib\cmp\standard.dio
> * MSB
> * LSB
> .lib C:\Users\Ziaullah\Desktop\XOR\XOR.lib
> .lib LTC.lib
> .backanno
> .end
>
> I am using XOR gate symbol I made using NOT , AND, OR gates (AND OR using NAND NOR and NOT)
> https://asicdigitaldesign.files.wordpress.com/2007/05/high-z_solution_02.png
>
> which in turn were symbolized by myself using Psudo-NMOS logic.
>
> Now the circuit is taking like 10 minutes or something to simulate 20us of waveform....where am I missing ? I have made a 2-bit encoder and it takes much less time for simulation of same amount of time.
>
> The worries are that I need to install this circuit after Sigma - Delta modulator , so most probably it will take around 20-30 minutes which is quite unacceptable !
>
> Please guide me as I am new to spice environment. Thanks again !
>
> Also, before simulation starts, a line comes for 3-4 minutes saying "Parsing 475 circuit elements". What does that mean ?
>
> P.S :- If you have any working 2-3bit (or more ) Delta sigma ADC , please do post it. I will use it as a reference :) Thanks
>
Try running a DC Sweep and see what you get.
Reply by John Larkin●August 16, 20152015-08-16
On Sat, 15 Aug 2015 18:39:27 -0700, Jeff Liebermann <jeffl@cruzio.com>
wrote:
>On Sat, 15 Aug 2015 13:40:42 -0700, John Larkin
><jlarkin@highlandtechnology.com> wrote:
>
>>I'm fine-tuning the Dell at work before we clone it to my new home and
>>cabin machines.
>
>A word of caution. There are numerous SSD tuning guides and programs
>found on the internet. They vary from a few obvious and conservative
>tweaks, to massive overkill with some potentially detrimental to
>performance tweaks. For example, several such guides suggest
>disabling system restore, which I consider a lousy idea.
>
>If your SSD includes tuning software, such as Samsung Magician, I
>suggest you use it.
><http://www.samsung.com/global/business/semiconductor/minisite/SSD/global/html/support/downloads.html>\
>Also use the program to check if your SSD is accumulating too many bad
>blocks, and to check for firmware updates.
>
>For Windoze 7, I'm still undecided on which guide to follow. So far
>this is the most reasonable that I've found and followed:
><http://www.disk-partition.com/kb/tips-ssd-optimization-windows7-1.html>
>
>You also need to test if your SSD partitions are aligned on 4K blocks.
>The easiest test uses "AS SSD" benchmark:
><http://www.alex-is.de/PHP/fusion/downloads.php?download_id=9>
>It should look like this:
><http://superuser.com/questions/718505/is-my-ssd-disk-aligned-to-4k-sectors-and-if-not-how-do-i-fix-it>
>As long as your SSD was formatted with Vista, Win 7 or later, you're
>probably ok. (I had one that was running XP which took a while, but
>worked once I decoded the instructions).
>
>>I'm considering installing Classic Shell to zap the
>>few remaining Win7 annoyances.
>
>Just do it. It's painless:
><http://www.classicshell.net/features/>
>You can also temporarily disabled it if it gets in the way, hit
><shift><click> to temporarily revert to the Microsoft start thing, or
>uninstall it if you hate it. The one annoyance that it fixes for me
>is removing the wiggly icons from the Win 10 start screen. Consider
>yourself fortunate not to have a wiggly icons start screen in Win 7.
We have raid hdds in the new Dells, but no ssds.
The built-in "classic" desktop is pretty good in Win7; it kills the
absurd Aero thing, so you can actually see most of the icons. I miss
not seeing file/folder sizes at the botttom of the Explorer panes, and
the up-directory arrow.
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Reply by MUHAMMAD FAHAD BHUTTA●August 16, 20152015-08-16
On Saturday, 15 August 2015 06:59:56 UTC+5, MUHAMMAD FAHAD BHUTTA wrote:
> Greetings people !
>
> So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple.
>
> Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using Instrument Amplifier to get better result but that is not a necessity)
>
> Now, the output is not as what we want (that is another issue with Quantizer but we can solve that later) but the time LTspice is taking to simulate the whole circuit is round about 10 minutes or something which is kind of an unacceptable ( giving a look at the transient response parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to start saving data, max time step 1ms , skip initial operating point solution; True). This is the best transient settings I did and it is still taking around 10minutes. And without this setting, the simulation time grows relatively high.
>
> Also , the CPU usage during simulation is 100% (means other programs are hard to run). Although the machine I am using is a SAMSUNG series 5 ultra book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is not the problem with CPU to handle a low level simulation.(BTW I burrowed it from a friend for some time till I get my new DELL XPS 13"...So don't blame me on buying an AMD)
>
> One more thing is that I used the simulation on my friend's core 2 duo desktop and it is taking almost the same time. Also on my friend's notebook which has 2nd generation core i3 processor and still the same time taken to simulate. RAM is not the issue though !
>
> So, Can any one please tell me what are the reasons? Is the circuit not properly optimized? Am I giving the wrong transient parameters ? Is this the CPU problem ? Any advice perhaps because I am relatively new to this spice simulation environment (only a month of little bit of experience).
>
> Thanks in advance :)
Okay so here is the 8x3 encoder I am working on right now ( which I will be installing after Delta-Sigma Modulator.
http://sub.allaboutcircuits.com/images/04258.png
And here is the netlist
* C:\Program Files (x86)\LTC\LTspiceIV\Draft3.asc
R1 REF N005 100
R2 N005 N008 100
R3 N008 N011 100
R4 N011 N014 100
R5 N014 N017 100
R6 N017 N020 100
R7 N020 N023 100
R8 N023 0 100
XU1 IN N005 N002 N003 N004 LT1007
XU2 IN N008 N002 N003 N007 LT1007
XU3 IN N011 N002 N003 N010 LT1007
XU4 IN N014 N002 N003 N013 LT1007
XU5 IN N017 N002 N003 N016 LT1007
XU6 IN N020 N002 N003 N019 LT1007
XU7 IN N023 N002 N003 N022 LT1007
XU8 0 N004 N001 XOR
XU9 N004 N007 N006 XOR
XU10 N007 N010 N009 XOR
XU11 N010 N013 N012 XOR
XU12 N013 N016 N015 XOR
XU13 N016 N019 N018 XOR
XU14 N019 N022 N021 XOR
D1 N001 LSB 1N4148
D2 N001 2SB 1N4148
D3 N001 MSB 1N4148
R9 MSB 0 1000
R10 2SB 0 1000
R11 LSB 0 1000
D4 N006 MSB 1N4148
D5 N006 2SB 1N4148
D6 N009 MSB 1N4148
D7 N009 LSB 1N4148
D8 N012 MSB 1N4148
D9 N015 2SB 1N4148
D10 N015 LSB 1N4148
D11 N018 2SB 1N4148
D12 N021 LSB 1N4148
V1 N002 0 7
V2 0 N003 1
.model D D
.lib C:\Program Files (x86)\LTC\LTspiceIV\lib\cmp\standard.dio
* MSB
* LSB
.lib C:\Users\Ziaullah\Desktop\XOR\XOR.lib
.lib LTC.lib
.backanno
.end
I am using XOR gate symbol I made using NOT , AND, OR gates (AND OR using NAND NOR and NOT)
https://asicdigitaldesign.files.wordpress.com/2007/05/high-z_solution_02.png
which in turn were symbolized by myself using Psudo-NMOS logic.
Now the circuit is taking like 10 minutes or something to simulate 20us of waveform....where am I missing ? I have made a 2-bit encoder and it takes much less time for simulation of same amount of time.
The worries are that I need to install this circuit after Sigma - Delta modulator , so most probably it will take around 20-30 minutes which is quite unacceptable !
Please guide me as I am new to spice environment. Thanks again !
Also, before simulation starts, a line comes for 3-4 minutes saying "Parsing 475 circuit elements". What does that mean ?
P.S :- If you have any working 2-3bit (or more ) Delta sigma ADC , please do post it. I will use it as a reference :) Thanks
Reply by Jeff Liebermann●August 15, 20152015-08-15
On Sat, 15 Aug 2015 13:40:42 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:
>I'm fine-tuning the Dell at work before we clone it to my new home and
>cabin machines.
>I'm considering installing Classic Shell to zap the
>few remaining Win7 annoyances.
Just do it. It's painless:
<http://www.classicshell.net/features/>
You can also temporarily disabled it if it gets in the way, hit
<shift><click> to temporarily revert to the Microsoft start thing, or
uninstall it if you hate it. The one annoyance that it fixes for me
is removing the wiggly icons from the Win 10 start screen. Consider
yourself fortunate not to have a wiggly icons start screen in Win 7.
--
Jeff Liebermann jeffl@cruzio.com
150 Felker St #D http://www.LearnByDestroying.com
Santa Cruz CA 95060 http://802.11junk.com
Skype: JeffLiebermann AE6KS 831-336-2558
Reply by John Larkin●August 15, 20152015-08-15
On Sat, 15 Aug 2015 12:30:01 -0700, "Harry D" <harryd@tdsystems.org>
wrote:
>
>
>"John Larkin" wrote in message
>news:u99tsahv6gdghs26qssrtmud004iu2f8h6@4ax.com...
>
>On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
><111619124@umt.edu.pk> wrote:
>
>>Greetings people !
>>
>>So lately, I have been working on my Sigma Delta ADC and before going
>>advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital
>>output) . The circuit is quite simple.
>>
>>Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer->
>>Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of
>>Difference Amplifier (I am using Instrument Amplifier to get better result
>>but that is not a necessity)
>>
>>Now, the output is not as what we want (that is another issue with
>>Quantizer but we can solve that later) but the time LTspice is taking to
>>simulate the whole circuit is round about 10 minutes or something which is
>>kind of an unacceptable ( giving a look at the transient response
>>parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to
>>start saving data, max time step 1ms , skip initial operating point
>>solution; True). This is the best transient settings I did and it is still
>>taking around 10minutes. And without this setting, the simulation time
>>grows relatively high.
>>
>>Also , the CPU usage during simulation is 100% (means other programs are
>>hard to run). Although the machine I am using is a SAMSUNG series 5 ultra
>>book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is
>>not the problem with CPU to handle a low level simulation.(BTW I burrowed
>>it from a friend for some time till I get my new DELL XPS 13"...So don't
>>blame me on buying an AMD)
>>
>>One more thing is that I used the simulation on my friend's core 2 duo
>>desktop and it is taking almost the same time. Also on my friend's notebook
>>which has 2nd generation core i3 processor and still the same time taken to
>>simulate. RAM is not the issue though !
>>
>>So, Can any one please tell me what are the reasons? Is the circuit not
>>properly optimized? Am I giving the wrong transient parameters ? Is this
>>the CPU problem ? Any advice perhaps because I am relatively new to this
>>spice simulation environment (only a month of little bit of experience).
>>
>>Thanks in advance :)
>
>
>Well, post your circuit!
>
>The thing below is a 1st order delta-sigma used to make an analog
>signal isolator, to get an analog signal up into an isolated channel.
>It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my
>ancient HP machine.
>
>We're not going to do it this way, but it was interesting. We'll use a
>DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI
>interface.
>
>
>5 sec. sim time with Intel I7 core and SSD
>
>Cheers, Harry
>
My new Dell (they made me upgrade!) runs Spice about 5x faster than my
old HP, so that's in the ballpark. The SSD may help a bit, saving the
.RAW data faster.
I'm fine-tuning the Dell at work before we clone it to my new home and
cabin machines. I'm considering installing Classic Shell to zap the
few remaining Win7 annoyances.
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Reply by Jim Thompson●August 15, 20152015-08-15
On Sat, 15 Aug 2015 12:30:01 -0700, "Harry D" <harryd@tdsystems.org>
wrote:
>
>
>"John Larkin" wrote in message
>news:u99tsahv6gdghs26qssrtmud004iu2f8h6@4ax.com...
>
>On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
><111619124@umt.edu.pk> wrote:
>
>>Greetings people !
>>
>>So lately, I have been working on my Sigma Delta ADC and before going
>>advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital
>>output) . The circuit is quite simple.
>>
>>Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer->
>>Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of
>>Difference Amplifier (I am using Instrument Amplifier to get better result
>>but that is not a necessity)
>>
>>Now, the output is not as what we want (that is another issue with
>>Quantizer but we can solve that later) but the time LTspice is taking to
>>simulate the whole circuit is round about 10 minutes or something which is
>>kind of an unacceptable ( giving a look at the transient response
>>parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to
>>start saving data, max time step 1ms , skip initial operating point
>>solution; True). This is the best transient settings I did and it is still
>>taking around 10minutes. And without this setting, the simulation time
>>grows relatively high.
>>
>>Also , the CPU usage during simulation is 100% (means other programs are
>>hard to run). Although the machine I am using is a SAMSUNG series 5 ultra
>>book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is
>>not the problem with CPU to handle a low level simulation.(BTW I burrowed
>>it from a friend for some time till I get my new DELL XPS 13"...So don't
>>blame me on buying an AMD)
>>
>>One more thing is that I used the simulation on my friend's core 2 duo
>>desktop and it is taking almost the same time. Also on my friend's notebook
>>which has 2nd generation core i3 processor and still the same time taken to
>>simulate. RAM is not the issue though !
>>
>>So, Can any one please tell me what are the reasons? Is the circuit not
>>properly optimized? Am I giving the wrong transient parameters ? Is this
>>the CPU problem ? Any advice perhaps because I am relatively new to this
>>spice simulation environment (only a month of little bit of experience).
>>
>>Thanks in advance :)
>
>
>Well, post your circuit!
>
>The thing below is a 1st order delta-sigma used to make an analog
>signal isolator, to get an analog signal up into an isolated channel.
>It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my
>ancient HP machine.
>
>We're not going to do it this way, but it was interesting. We'll use a
>DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI
>interface.
>
>
>5 sec. sim time with Intel I7 core and SSD
>
>Cheers, Harry
>
"The thing below" ????
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Reply by Harry D●August 15, 20152015-08-15
"John Larkin" wrote in message
news:u99tsahv6gdghs26qssrtmud004iu2f8h6@4ax.com...
On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
<111619124@umt.edu.pk> wrote:
>Greetings people !
>
>So lately, I have been working on my Sigma Delta ADC and before going
>advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital
>output) . The circuit is quite simple.
>
>Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer->
>Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of
>Difference Amplifier (I am using Instrument Amplifier to get better result
>but that is not a necessity)
>
>Now, the output is not as what we want (that is another issue with
>Quantizer but we can solve that later) but the time LTspice is taking to
>simulate the whole circuit is round about 10 minutes or something which is
>kind of an unacceptable ( giving a look at the transient response
>parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to
>start saving data, max time step 1ms , skip initial operating point
>solution; True). This is the best transient settings I did and it is still
>taking around 10minutes. And without this setting, the simulation time
>grows relatively high.
>
>Also , the CPU usage during simulation is 100% (means other programs are
>hard to run). Although the machine I am using is a SAMSUNG series 5 ultra
>book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is
>not the problem with CPU to handle a low level simulation.(BTW I burrowed
>it from a friend for some time till I get my new DELL XPS 13"...So don't
>blame me on buying an AMD)
>
>One more thing is that I used the simulation on my friend's core 2 duo
>desktop and it is taking almost the same time. Also on my friend's notebook
>which has 2nd generation core i3 processor and still the same time taken to
>simulate. RAM is not the issue though !
>
>So, Can any one please tell me what are the reasons? Is the circuit not
>properly optimized? Am I giving the wrong transient parameters ? Is this
>the CPU problem ? Any advice perhaps because I am relatively new to this
>spice simulation environment (only a month of little bit of experience).
>
>Thanks in advance :)
Well, post your circuit!
The thing below is a 1st order delta-sigma used to make an analog
signal isolator, to get an analog signal up into an isolated channel.
It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my
ancient HP machine.
We're not going to do it this way, but it was interesting. We'll use a
DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI
interface.
5 sec. sim time with Intel I7 core and SSD
Cheers, Harry