> On 05/15/2014 12:09 AM, John Silverman wrote:
>> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>> On 05/13/2014 04:15 PM, John Silverman wrote:
>>>> This is getting way too complicated. Analog circuits drift and can
>>>> never guarantee quadrature.
>>> That isn't so. As long as slew limits are observed, an integrator
>>> will give a very accurate 90 degree phase shift.
>> You are correct. I made a simple comparison model in LTspice and tried
>> to break it. Nothing had much effect on the phase angle, except the op
>> amp GBW needs to be above 50 MHz, preferably 200 MHz or higher. I post
>> the LTspice files at the end.
>>> Servoing the frequency to
>>> make the amplitudes equal isn't very hard. That makes the component
>>> tolerances all come out as frequency shifts, and measuring the
>>> frequency accurately gets rid of all of it, for the purposes of
>>> capacitance measurement.
>> No need to go to that complexity. Simply adjusting the capacitance in
>> the op amp feedback will trim the amplitude. See the LTspice file at
the
>> end.
> But how would you do that in real life? There aren't any really big
> varactors left, and anyway, they'd cause sine distortion (and probably
> parametric phase shift as well). It could probably be done, but not so
> easily.
Leif Asbrink uses 24V zener diodes in a 14Mhz VCO:
<http://www.sm5bsz.com/osc/vco.htm>
Of course, you need a CV analyzer to characterize the zeners, which is
why I decided to build one.
The sine distortion can be minimized by using two diodes back to back and
adding the control voltage to the junction.
>> This allows the measurement to be made at a specific frequency, such
as
>> 1 MHz, which helps repeatability.
> With good components, the adjustment would only have to be a percent or
> two, which won't make much difference to the measurement. I'm not
> wedded to the idea of servoing the frequency, I just thought it was
fun.
> A dpot in front of the integrator's input resistor would work too, but
> you'd have to watch the capacitances.
The pot is probably a better idea. It should not need continuous
adjustment, so it could be a simple tweak pot on the pcb. Only needs to
be tweaked as the component age and the circuit drifts.
>>
>>> A simple 74HC74 will. See
>>>>
>>>> http://www.wb5rvz.com/sdr/ensemble_rx_ii_vhf/04_div.htm
>>>
>>> Johnson counters are great in PLLs, where the square wave output is
>>> just what you want, but not much use for making quadrature sine
>>> oscillators (as others have noted).
>>
>> The intended use is a CV analyzer. The quadrature signals are not
>> applied to the junction. They are needed to apply switching signals to
>> the in-phase and quadrature detectors. A CMOS switcher requires square
>> waves at logic level, which is naturally provided by the 74AC74.
> I don't recall your being the OP.
I never said I was. Once you figure out what George is trying to do, it
is obvious sine waves are not needed. In fact, they are an unnecessary
complication.
>I use Johnson counters fairly often.
> My first PLL, back in 1981, used one to generate a quadrature signal
> for the lock detector since the main PD servoed on the null.
> So they're great. But George was asking for sine waves, unless I'm
very
> much mistaken.
He didn't realize he could do the job with square waves. Once he realized
he would have to convert them into square waves, he stated:
Quote:
And yeah I think it will all get turned into square waves to turn
switches or something on and off. So your D-flip flop circuit may do
the trick.
>> Sine waves would need to be converted square waves, which requires a
>> limiter.
> Which is much easier to do well than square->sine.
Maybe not. See the approach at the end.
>> The switching signals need to have low even harmonic distortion. This
>> may be difficult to achieve using sine waves and a limiter, but it is
a
>> natural result of dividing in a 74AC74.
> Not hard at all. Capacitive coupling into a low-offset comparator, or
> even a crappy comparator with a simple positive/negative feedback
> network to force the duty cycle to 50%.
Too complicated, adds jitter, difficult to guarantee quadrature,
difficult to calibrate, drifts, etc.
It is much simpler to start with a 4X clock and use a Johnson counter.
>> The integrator approach is single frequency, so different modules
would
>> be needed to cover specific frequencies. The 74AC74 is inherently
>> broadband so a single ic can be used over a broad frequency range.
>>
>> The 74AC74 will clock at a minimum of 140 MHz. This would allow
>> measurements up to 35 MHz. It may be difficult to get an op amp
>> integrator to work at higher frequencies and still provide an accurate
>> 90 degree phase shift.
> I don't know about that. The ADA4817 is a unity-gain stable op amp
with
> a GBW of 1.4 GHz.
One degree of phase shift at 10 MHz is 100e-9/360 = 270 picoseconds. Good
Luck.
Where do you get a low jitter, low harmonic distortion, phase and
amplitude lockable sine wave oscillator at 10 MHz?
> <snip LTspice stuff>
Sine wave oscillators are notoriously difficult at RF frequencies. They
have lots of jitter and harmonic distortion, and have difficulty
controlling the amplitude and locking to a desired phase. They also tend
to drift as the components age and the temperature changes.
This approach is very low jitter and has essentially the same jitter as
the source clock. According to LTspice, the second harmonic distortion is
about -80dBc, which is instrumentation-class performance. It can easily
be locked to the desired phase, and the amplitude is easily controlled.
It is inexpensive and takes very little space on the pcb.
The CV analyzer may have to deal with signal amplitudes in the microvolt
or nanovolt range. This requires a high gain ampifier in the detection
chain, which will have considerable propagation delay. This means the
quadrature square wave signals will be out of phase with the sine wave.
A second Johnson counter is needed to generate the quadrature detection
signals. It could be driven from the same 4X clock through a delay or
adjustable phase circuit.
Here are the LTspice files:
SHEET 1 1820 692
WIRE 1136 -128 608 -128
WIRE 608 -48 608 -128
WIRE 640 -48 608 -48
WIRE 864 -48 800 -48
WIRE 944 -48 864 -48
WIRE 1472 -48 1104 -48
WIRE 1488 -48 1472 -48
WIRE 640 0 608 0
WIRE 832 0 816 0
WIRE 944 0 912 0
WIRE 1136 0 1136 -128
WIRE 1136 0 1120 0
WIRE 1472 0 1136 0
WIRE 1488 0 1472 0
WIRE 608 96 608 0
WIRE 672 96 608 96
WIRE 912 96 912 0
WIRE 912 96 672 96
WIRE 608 112 608 96
WIRE 864 128 864 -48
WIRE 1200 128 864 128
WIRE 1472 128 1200 128
WIRE 1488 128 1472 128
WIRE 832 160 832 0
WIRE 1472 160 832 160
WIRE 1488 160 1472 160
WIRE 960 192 944 192
WIRE 1008 192 960 192
WIRE 1088 192 1008 192
WIRE 608 208 608 192
WIRE 1008 208 1008 192
WIRE 1088 208 1088 192
WIRE 1488 240 1232 240
WIRE 1008 304 1008 272
WIRE 1040 304 1008 304
WIRE 1088 304 1088 288
WIRE 1088 304 1040 304
WIRE 1232 304 1232 240
WIRE 1232 304 1088 304
WIRE 1264 304 1232 304
WIRE 944 320 944 192
WIRE 1088 320 1088 304
WIRE 832 368 832 160
WIRE 880 368 832 368
WIRE 1200 368 1200 128
WIRE 1200 368 1152 368
WIRE 608 400 608 384
WIRE 736 400 736 384
WIRE 944 432 944 416
WIRE 1024 432 944 432
WIRE 1088 432 1088 416
WIRE 1088 432 1024 432
WIRE 1024 448 1024 432
WIRE 1152 496 1088 496
WIRE 1264 496 1152 496
WIRE 1152 544 1152 496
WIRE 1024 560 1024 544
WIRE 1024 656 1024 640
WIRE 1072 656 1024 656
WIRE 1152 656 1152 624
WIRE 1152 656 1072 656
FLAG 608 208 0
FLAG 672 96 Clk
FLAG 1472 128 A2Q
FLAG 1472 0 A3!Q
FLAG 1472 -48 A3Q
FLAG 1472 160 A2!Q
FLAG 608 400 0
FLAG 736 400 0
FLAG 608 304 Vcc
FLAG 960 192 Vcc
FLAG 736 304 VEE
FLAG 1072 656 VEE
FLAG 1040 304 Sine
SYMBOL digital\\dflop 720 -96 R0
WINDOW 3 8 168 Invisible 2
SYMATTR Value TD=2n TRise=2n VHigh=0.95
SYMATTR InstName A2
SYMBOL digital\\dflop 1024 -96 R0
WINDOW 3 8 168 Invisible 2
SYMATTR Value TD=2n TRise=2n VHigh=0.95
SYMATTR InstName A3
SYMBOL voltage 608 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0.5 0.5 4e6)
SYMBOL cap 992 208 R0
WINDOW 3 23 53 Left 2
SYMATTR Value 304pf
SYMATTR InstName C1
SYMBOL ind 1072 192 R0
SYMATTR InstName L1
SYMATTR Value 82�h
SYMATTR SpiceLine Rser=24
SYMBOL npn 880 320 R0
SYMATTR InstName Q1
SYMATTR Value 2N2369
SYMBOL npn 1152 320 M0
SYMATTR InstName Q2
SYMATTR Value 2N2369
SYMBOL npn 1088 448 M0
SYMATTR InstName Q3
SYMATTR Value 2N2369
SYMBOL voltage 608 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5V
SYMBOL voltage 736 400 M180
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 5V
SYMBOL res 1008 544 R0
SYMATTR InstName R1
SYMATTR Value 15k
SYMBOL voltage 1152 528 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value 3
TEXT 616 -184 Left 2 !.tran 0 50u 45u 200p
TEXT 616 -216 Left 2 ;'I-Q Quadrature Generator With Sine Output
TEXT 984 -184 Left 2 !.options plotwinsize=0
TEXT 984 -160 Left 2 !.options nomarch
TEXT 1144 480 Left 2 ;AGC Voltage
TEXT 1296 344 Left 2 ;PLL and Amplitude
TEXT 1336 376 Left 2 ;Control
TEXT 1272 224 Left 2 ;Sine Wave To Buffer Amp
TEXT 1304 48 Left 2 ;Quadrature Signals to
TEXT 1304 72 Left 2 ;I-Q Detect
TEXT 1184 -184 Left 2 !.options numdgt=15
RECTANGLE Normal 1488 528 1264 272 2
Here is the PLT file:
[Transient Analysis]
{
Npanes: 4
{
traces: 1 {524293,0,"V(sine)"}
X: ('�',1,0,5e-007,5e-006)
Y[0]: (' ',1,3.8,0.2,6.2)
Y[1]: ('m',1,1e+308,0.0004,-1e+308)
Volts: (' ',0,0,1,3.8,0.2,6.2)
Log: 0 0 0
GridStyle: 1
},
{
traces: 1 {268959748,0,"V(a3q)"}
X: ('�',1,0,5e-007,5e-006)
Y[0]: (' ',1,-0.1,0.1,1)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: (' ',0,0,1,-0.1,0.1,1)
Log: 0 0 0
GridStyle: 1
},
{
traces: 1 {268959747,0,"V(a2q)"}
X: ('�',1,0,5e-007,5e-006)
Y[0]: (' ',1,-0.1,0.1,1)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: (' ',0,0,1,-0.1,0.1,1)
Log: 0 0 0
GridStyle: 1
},
{
traces: 1 {524290,0,"V(clk)"}
X: ('�',1,0,5e-007,5e-006)
Y[0]: (' ',1,0,0.1,1)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: (' ',0,0,1,0,0.1,1)
Log: 0 0 0
GridStyle: 1
}
}