Reply by josephkk November 14, 20122012-11-14
On Mon, 12 Nov 2012 17:52:33 -0600, "Tim Williams" =
<tmoranwms@charter.net>
wrote:

>"whit3rd" <whit3rd@gmail.com> wrote in message=20 >news:44e8dda0-8d3c-420d-9f93-82bc24f477dd@googlegroups.com... >> I thought the original reference was to polyimide (Kapton, Parylene)=20 >> film, >> baked onto the surface to exclude reactive ions (like, from moisture). >> It's a VERY thin film. > >Back in the day, components (mostly diodes) were labeled as "glass=20 >passivated". I believe I have also heard kapton being a prevalent =
method=20
>these days. > >Tim
Hmmm. "Glassivation" (tm) is from the early 1960s or before. I don't think Kapton became popular until the 1980s. YMMV ?-)
Reply by josephkk November 14, 20122012-11-14
On Mon, 12 Nov 2012 15:03:45 -0800 (PST), whit3rd <whit3rd@gmail.com>
wrote:

>On Monday, November 12, 2012 8:41:42 AM UTC-8, John Larkin wrote: >> On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs > >[and SOMEONE wrote}... >> >>>> Some manufacturers put goop over the chip prior to the plastic =
going
>>=20 >> >>>> around the leadframe.=20 > >> >IIRC the goop is generally RTV silicone, which greatly reduces die =20 >> >stress > >> Lots of chip packages are so thin there can't be room for a filler >> inside. > >I thought the original reference was to polyimide (Kapton, Parylene) =
film,
>baked onto the surface to exclude reactive ions (like, from moisture). >It's a VERY thin film.=20
Dunno, just goop does not sound like a thin film to me. OTOH i would = like a better reference than some goop on some parts. ?-)
Reply by Phil Hobbs November 12, 20122012-11-12
On 11/12/2012 6:03 PM, whit3rd wrote:
> On Monday, November 12, 2012 8:41:42 AM UTC-8, John Larkin wrote: >> On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs > > [and SOMEONE wrote}... >>>>>> Some manufacturers put goop over the chip prior to the plastic going >> >>>>>> around the leadframe. > >>> IIRC the goop is generally RTV silicone, which greatly reduces die >>> stress > >> Lots of chip packages are so thin there can't be room for a filler >> inside. > > I thought the original reference was to polyimide (Kapton, Parylene) film, > baked onto the surface to exclude reactive ions (like, from moisture). > It's a VERY thin film. >
Parylene is usually evaporated, so it would be hard to keep that off the leads. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 USA +1 845 480 2058 hobbs at electrooptical dot net http://electrooptical.net
Reply by Tim Williams November 12, 20122012-11-12
"whit3rd" <whit3rd@gmail.com> wrote in message 
news:44e8dda0-8d3c-420d-9f93-82bc24f477dd@googlegroups.com...
> I thought the original reference was to polyimide (Kapton, Parylene) > film, > baked onto the surface to exclude reactive ions (like, from moisture). > It's a VERY thin film.
Back in the day, components (mostly diodes) were labeled as "glass passivated". I believe I have also heard kapton being a prevalent method these days. Tim -- Deep Friar: a very philosophical monk. Website: http://seventransistorlabs.com
Reply by Jim Thompson November 12, 20122012-11-12
On Mon, 12 Nov 2012 15:13:32 -0800, miso <miso@sushi.com> wrote:

>On 11/12/2012 8:41 AM, John Larkin wrote: >> On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 11/12/2012 12:22 AM, miso wrote: >>>> On 11/10/2012 9:00 PM, josephkk wrote: >>>>> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: >>>>> >>>>>> >>>>>> Well as you know, only the electrical test limits (in theory) can be >>>>>> trusted. The curves are guidelines. The story I was always told about >>>>>> electrical limits is the customer gets the right to return a part for a >>>>>> replacement if the part fails electricals. Since nobody does incoming >>>>>> inspection these days, that means a lot of crap gets shipped if the >>>>>> vendor has poor quality. [Note the manufacturers flow usually has a QA >>>>>> test for each lot on a sample basis to insure the test hardware wasn't >>>>>> fubar. QA test is probably over temperature. ] >>>>> >>>>> Actual testing for commercial parts is limited to basic function, >>>>> often on >>>>> wafer. Industrial parts get tested at 25 C and maybe at high temp, >>>>> usually after packaging, no real process difference except test failures >>>>> are usually dropped back into commercial bins. Military grades require >>>>> much more bookkeeping. Generally only "selected wafers" get a chance to >>>>> be Military grade. >>>>>> >>>>>> Anyway, I see your point and the datasheet doesn't make sense. I can't >>>>>> think of anything in a ceramic package that would cause it to leak more >>>>>> than plastic. I assume they don't put carbon black in this plastic >>>>>> package, but that could make it worse than ceramic. >>>>>> >>>>>> Some manufacturers put goop over the chip prior to the plastic going >>>>>> around the leadframe. I assume that goop has high resistivity. >>>>>> >>>>> The goop would have to be much less expensive that package plastic or >>>>> preserve exotic properties like ultra low leakage. >>>>> >>>>> ?-) >>>>> >>>> >>>> The goop is something to do with packaging in general, not low leakage. >>>> Not everyone uses it. >>>> >>>> Wafer test is simply to save packaging parts that will fail at final >>>> test anyway. Nobody, or at least no place I ever worked, packages parts >>>> and didn't test them. Plenty can go wrong in backlap, bonding, >>>> packaging, etc. >>>> >>>> Everything with electrical limits is tested at ATE at all grades at room >>>> temp for packaged parts. If you look carefully, you may see GBD >>>> (guaranteed by design). That can mean a lot of things. If it is a >>>> capacitance at a pin, the assumption is if the wafer passed parametric >>>> testing, then the pin capacitance will be totally predictable, hence >>>> GBD. If the part has a reference in it. the drift at elevated >>>> temperature in theory can correlate to the drift at cold temperature. >>>> >>>> All the tests have guardbands. Depending on the company, some test wide >>>> at wafer then accept the rejects at final. You do this is the chips are >>>> expensive. That is, you are willing to spend some money packaging >>>> borderline parts in order to get product to sell. The other scheme is to >>>> test tight at wafer and then have looser limts as the part goes down the >>>> test flow. That is, the test limits are tighter than the datasheet spec >>>> at wafer. At QA, the test limits are exactly what is on the datasheet >>>> less the bench to ATE correlation error. That is, somebody should be >>>> able to bench test the part and have it pass publsihed electricals. >>>> >>>> If you are not familiar with parameter wafer testing, the devices on the >>>> test pattern have to meet test criteria before product wafer testing is >>>> done. If something fails the parametric test, then a decision is made to >>>> see if the parts are OK to sell in terms of reliability. That is, say >>>> the oxide breakdown was out of spec. You would probably reject the wafer >>>> just because you don't trust it. Put if a parameter is off on a device >>>> you don't use (say epifet), then the wafer can go off to production >>>> wafer test. >>>> >>> >>> Interesting, thanks. >>> >>> IIRC the goop is generally RTV silicone, which greatly reduces die >>> stress due to epoxy shrinkage and temperature cycling. That's often >>> recommended for people who want to pot their circuits in epoxy--a layer >>> of RTV underneath prevents stuff getting torn off or cracking when the >>> epoxy cures. OTOH for chips, the RTV will make the package floppier, >>> which might increase die stress from external effects. >>> >>> Cheers >>> >>> Phil Hobbs >> >> Lots of chip packages are so thin there can't be room for a filler >> inside. >> >> Fun: push here and there on an opamp or a DAC with a pencil point and >> watch the DC offset change. >> >> > >There are layout tricks to get around the pressure effect, but they take >up space. One scheme is named after an annoying pop music group: ABBA. I >have seen texts where the layout is done in a manner to match the >orientation of the wafer. I've never seen that done in real life. > >Surface mount parts get a lot of backlap. If you don't know about >backlap, here is my attempt at an explanation. I don't know the "deal" >exactly, but the fab picks a wafer thickness they believe will stand up >to the rigors of processing, probably handling issues. Often that is too >thick for the package, so they grid the wafer down to the right >thickness after it has been wafer tested. This is an outside service, at >least in my experience. [TI could be an exception since they are known >for doing much work in house.] I have seen a lot of product over the >years screwed up by using the wrong backlap spec. Outside vendors are >always a problem. One place I worked was too cheap to own their own ion >implanter and often the outside service would miss an implant or do it >twice. > >The thinner the dice, the more likely the pressure effect will move the >offset. > >Prior to everyone using epi wafers, some fabs would ion implant the back >of the wafer to reduce resistivity. That sounded like a plan, but ion >implant isn't all that deep, so backklap would alter the bulk >resistivity in the final product. >
The "goop", more commonly referred to by us in the industry as "greased pig snot", is mostly for (1) stress relief of wirebonds, (2) to keep wirebonds from "touching down", and (3) to keep the wirebonds from being pushed/stressed during the injection molding. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by miso November 12, 20122012-11-12
On 11/12/2012 8:41 AM, John Larkin wrote:
> On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 11/12/2012 12:22 AM, miso wrote: >>> On 11/10/2012 9:00 PM, josephkk wrote: >>>> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: >>>> >>>>> >>>>> Well as you know, only the electrical test limits (in theory) can be >>>>> trusted. The curves are guidelines. The story I was always told about >>>>> electrical limits is the customer gets the right to return a part for a >>>>> replacement if the part fails electricals. Since nobody does incoming >>>>> inspection these days, that means a lot of crap gets shipped if the >>>>> vendor has poor quality. [Note the manufacturers flow usually has a QA >>>>> test for each lot on a sample basis to insure the test hardware wasn't >>>>> fubar. QA test is probably over temperature. ] >>>> >>>> Actual testing for commercial parts is limited to basic function, >>>> often on >>>> wafer. Industrial parts get tested at 25 C and maybe at high temp, >>>> usually after packaging, no real process difference except test failures >>>> are usually dropped back into commercial bins. Military grades require >>>> much more bookkeeping. Generally only "selected wafers" get a chance to >>>> be Military grade. >>>>> >>>>> Anyway, I see your point and the datasheet doesn't make sense. I can't >>>>> think of anything in a ceramic package that would cause it to leak more >>>>> than plastic. I assume they don't put carbon black in this plastic >>>>> package, but that could make it worse than ceramic. >>>>> >>>>> Some manufacturers put goop over the chip prior to the plastic going >>>>> around the leadframe. I assume that goop has high resistivity. >>>>> >>>> The goop would have to be much less expensive that package plastic or >>>> preserve exotic properties like ultra low leakage. >>>> >>>> ?-) >>>> >>> >>> The goop is something to do with packaging in general, not low leakage. >>> Not everyone uses it. >>> >>> Wafer test is simply to save packaging parts that will fail at final >>> test anyway. Nobody, or at least no place I ever worked, packages parts >>> and didn't test them. Plenty can go wrong in backlap, bonding, >>> packaging, etc. >>> >>> Everything with electrical limits is tested at ATE at all grades at room >>> temp for packaged parts. If you look carefully, you may see GBD >>> (guaranteed by design). That can mean a lot of things. If it is a >>> capacitance at a pin, the assumption is if the wafer passed parametric >>> testing, then the pin capacitance will be totally predictable, hence >>> GBD. If the part has a reference in it. the drift at elevated >>> temperature in theory can correlate to the drift at cold temperature. >>> >>> All the tests have guardbands. Depending on the company, some test wide >>> at wafer then accept the rejects at final. You do this is the chips are >>> expensive. That is, you are willing to spend some money packaging >>> borderline parts in order to get product to sell. The other scheme is to >>> test tight at wafer and then have looser limts as the part goes down the >>> test flow. That is, the test limits are tighter than the datasheet spec >>> at wafer. At QA, the test limits are exactly what is on the datasheet >>> less the bench to ATE correlation error. That is, somebody should be >>> able to bench test the part and have it pass publsihed electricals. >>> >>> If you are not familiar with parameter wafer testing, the devices on the >>> test pattern have to meet test criteria before product wafer testing is >>> done. If something fails the parametric test, then a decision is made to >>> see if the parts are OK to sell in terms of reliability. That is, say >>> the oxide breakdown was out of spec. You would probably reject the wafer >>> just because you don't trust it. Put if a parameter is off on a device >>> you don't use (say epifet), then the wafer can go off to production >>> wafer test. >>> >> >> Interesting, thanks. >> >> IIRC the goop is generally RTV silicone, which greatly reduces die >> stress due to epoxy shrinkage and temperature cycling. That's often >> recommended for people who want to pot their circuits in epoxy--a layer >> of RTV underneath prevents stuff getting torn off or cracking when the >> epoxy cures. OTOH for chips, the RTV will make the package floppier, >> which might increase die stress from external effects. >> >> Cheers >> >> Phil Hobbs > > Lots of chip packages are so thin there can't be room for a filler > inside. > > Fun: push here and there on an opamp or a DAC with a pencil point and > watch the DC offset change. > >
There are layout tricks to get around the pressure effect, but they take up space. One scheme is named after an annoying pop music group: ABBA. I have seen texts where the layout is done in a manner to match the orientation of the wafer. I've never seen that done in real life. Surface mount parts get a lot of backlap. If you don't know about backlap, here is my attempt at an explanation. I don't know the "deal" exactly, but the fab picks a wafer thickness they believe will stand up to the rigors of processing, probably handling issues. Often that is too thick for the package, so they grid the wafer down to the right thickness after it has been wafer tested. This is an outside service, at least in my experience. [TI could be an exception since they are known for doing much work in house.] I have seen a lot of product over the years screwed up by using the wrong backlap spec. Outside vendors are always a problem. One place I worked was too cheap to own their own ion implanter and often the outside service would miss an implant or do it twice. The thinner the dice, the more likely the pressure effect will move the offset. Prior to everyone using epi wafers, some fabs would ion implant the back of the wafer to reduce resistivity. That sounded like a plan, but ion implant isn't all that deep, so backklap would alter the bulk resistivity in the final product.
Reply by whit3rd November 12, 20122012-11-12
On Monday, November 12, 2012 8:41:42 AM UTC-8, John Larkin wrote:
> On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs
[and SOMEONE wrote}...
> >>>> Some manufacturers put goop over the chip prior to the plastic going > > >>>> around the leadframe.
> >IIRC the goop is generally RTV silicone, which greatly reduces die > >stress
> Lots of chip packages are so thin there can't be room for a filler > inside.
I thought the original reference was to polyimide (Kapton, Parylene) film, baked onto the surface to exclude reactive ions (like, from moisture). It's a VERY thin film.
Reply by John Larkin November 12, 20122012-11-12
On Mon, 12 Nov 2012 11:34:20 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 11/12/2012 12:22 AM, miso wrote: >> On 11/10/2012 9:00 PM, josephkk wrote: >>> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: >>> >>>> >>>> Well as you know, only the electrical test limits (in theory) can be >>>> trusted. The curves are guidelines. The story I was always told about >>>> electrical limits is the customer gets the right to return a part for a >>>> replacement if the part fails electricals. Since nobody does incoming >>>> inspection these days, that means a lot of crap gets shipped if the >>>> vendor has poor quality. [Note the manufacturers flow usually has a QA >>>> test for each lot on a sample basis to insure the test hardware wasn't >>>> fubar. QA test is probably over temperature. ] >>> >>> Actual testing for commercial parts is limited to basic function, >>> often on >>> wafer. Industrial parts get tested at 25 C and maybe at high temp, >>> usually after packaging, no real process difference except test failures >>> are usually dropped back into commercial bins. Military grades require >>> much more bookkeeping. Generally only "selected wafers" get a chance to >>> be Military grade. >>>> >>>> Anyway, I see your point and the datasheet doesn't make sense. I can't >>>> think of anything in a ceramic package that would cause it to leak more >>>> than plastic. I assume they don't put carbon black in this plastic >>>> package, but that could make it worse than ceramic. >>>> >>>> Some manufacturers put goop over the chip prior to the plastic going >>>> around the leadframe. I assume that goop has high resistivity. >>>> >>> The goop would have to be much less expensive that package plastic or >>> preserve exotic properties like ultra low leakage. >>> >>> ?-) >>> >> >> The goop is something to do with packaging in general, not low leakage. >> Not everyone uses it. >> >> Wafer test is simply to save packaging parts that will fail at final >> test anyway. Nobody, or at least no place I ever worked, packages parts >> and didn't test them. Plenty can go wrong in backlap, bonding, >> packaging, etc. >> >> Everything with electrical limits is tested at ATE at all grades at room >> temp for packaged parts. If you look carefully, you may see GBD >> (guaranteed by design). That can mean a lot of things. If it is a >> capacitance at a pin, the assumption is if the wafer passed parametric >> testing, then the pin capacitance will be totally predictable, hence >> GBD. If the part has a reference in it. the drift at elevated >> temperature in theory can correlate to the drift at cold temperature. >> >> All the tests have guardbands. Depending on the company, some test wide >> at wafer then accept the rejects at final. You do this is the chips are >> expensive. That is, you are willing to spend some money packaging >> borderline parts in order to get product to sell. The other scheme is to >> test tight at wafer and then have looser limts as the part goes down the >> test flow. That is, the test limits are tighter than the datasheet spec >> at wafer. At QA, the test limits are exactly what is on the datasheet >> less the bench to ATE correlation error. That is, somebody should be >> able to bench test the part and have it pass publsihed electricals. >> >> If you are not familiar with parameter wafer testing, the devices on the >> test pattern have to meet test criteria before product wafer testing is >> done. If something fails the parametric test, then a decision is made to >> see if the parts are OK to sell in terms of reliability. That is, say >> the oxide breakdown was out of spec. You would probably reject the wafer >> just because you don't trust it. Put if a parameter is off on a device >> you don't use (say epifet), then the wafer can go off to production >> wafer test. >> > >Interesting, thanks. > >IIRC the goop is generally RTV silicone, which greatly reduces die >stress due to epoxy shrinkage and temperature cycling. That's often >recommended for people who want to pot their circuits in epoxy--a layer >of RTV underneath prevents stuff getting torn off or cracking when the >epoxy cures. OTOH for chips, the RTV will make the package floppier, >which might increase die stress from external effects. > >Cheers > >Phil Hobbs
Lots of chip packages are so thin there can't be room for a filler inside. Fun: push here and there on an opamp or a DAC with a pencil point and watch the DC offset change. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Reply by Phil Hobbs November 12, 20122012-11-12
On 11/12/2012 12:22 AM, miso wrote:
> On 11/10/2012 9:00 PM, josephkk wrote: >> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: >> >>> >>> Well as you know, only the electrical test limits (in theory) can be >>> trusted. The curves are guidelines. The story I was always told about >>> electrical limits is the customer gets the right to return a part for a >>> replacement if the part fails electricals. Since nobody does incoming >>> inspection these days, that means a lot of crap gets shipped if the >>> vendor has poor quality. [Note the manufacturers flow usually has a QA >>> test for each lot on a sample basis to insure the test hardware wasn't >>> fubar. QA test is probably over temperature. ] >> >> Actual testing for commercial parts is limited to basic function, >> often on >> wafer. Industrial parts get tested at 25 C and maybe at high temp, >> usually after packaging, no real process difference except test failures >> are usually dropped back into commercial bins. Military grades require >> much more bookkeeping. Generally only "selected wafers" get a chance to >> be Military grade. >>> >>> Anyway, I see your point and the datasheet doesn't make sense. I can't >>> think of anything in a ceramic package that would cause it to leak more >>> than plastic. I assume they don't put carbon black in this plastic >>> package, but that could make it worse than ceramic. >>> >>> Some manufacturers put goop over the chip prior to the plastic going >>> around the leadframe. I assume that goop has high resistivity. >>> >> The goop would have to be much less expensive that package plastic or >> preserve exotic properties like ultra low leakage. >> >> ?-) >> > > The goop is something to do with packaging in general, not low leakage. > Not everyone uses it. > > Wafer test is simply to save packaging parts that will fail at final > test anyway. Nobody, or at least no place I ever worked, packages parts > and didn't test them. Plenty can go wrong in backlap, bonding, > packaging, etc. > > Everything with electrical limits is tested at ATE at all grades at room > temp for packaged parts. If you look carefully, you may see GBD > (guaranteed by design). That can mean a lot of things. If it is a > capacitance at a pin, the assumption is if the wafer passed parametric > testing, then the pin capacitance will be totally predictable, hence > GBD. If the part has a reference in it. the drift at elevated > temperature in theory can correlate to the drift at cold temperature. > > All the tests have guardbands. Depending on the company, some test wide > at wafer then accept the rejects at final. You do this is the chips are > expensive. That is, you are willing to spend some money packaging > borderline parts in order to get product to sell. The other scheme is to > test tight at wafer and then have looser limts as the part goes down the > test flow. That is, the test limits are tighter than the datasheet spec > at wafer. At QA, the test limits are exactly what is on the datasheet > less the bench to ATE correlation error. That is, somebody should be > able to bench test the part and have it pass publsihed electricals. > > If you are not familiar with parameter wafer testing, the devices on the > test pattern have to meet test criteria before product wafer testing is > done. If something fails the parametric test, then a decision is made to > see if the parts are OK to sell in terms of reliability. That is, say > the oxide breakdown was out of spec. You would probably reject the wafer > just because you don't trust it. Put if a parameter is off on a device > you don't use (say epifet), then the wafer can go off to production > wafer test. >
Interesting, thanks. IIRC the goop is generally RTV silicone, which greatly reduces die stress due to epoxy shrinkage and temperature cycling. That's often recommended for people who want to pot their circuits in epoxy--a layer of RTV underneath prevents stuff getting torn off or cracking when the epoxy cures. OTOH for chips, the RTV will make the package floppier, which might increase die stress from external effects. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by miso November 12, 20122012-11-12
On 11/10/2012 9:00 PM, josephkk wrote:
> On Thu, 08 Nov 2012 20:53:26 -0800, miso <miso@sushi.com> wrote: > >> >> Well as you know, only the electrical test limits (in theory) can be >> trusted. The curves are guidelines. The story I was always told about >> electrical limits is the customer gets the right to return a part for a >> replacement if the part fails electricals. Since nobody does incoming >> inspection these days, that means a lot of crap gets shipped if the >> vendor has poor quality. [Note the manufacturers flow usually has a QA >> test for each lot on a sample basis to insure the test hardware wasn't >> fubar. QA test is probably over temperature. ] > > Actual testing for commercial parts is limited to basic function, often on > wafer. Industrial parts get tested at 25 C and maybe at high temp, > usually after packaging, no real process difference except test failures > are usually dropped back into commercial bins. Military grades require > much more bookkeeping. Generally only "selected wafers" get a chance to > be Military grade. >> >> Anyway, I see your point and the datasheet doesn't make sense. I can't >> think of anything in a ceramic package that would cause it to leak more >> than plastic. I assume they don't put carbon black in this plastic >> package, but that could make it worse than ceramic. >> >> Some manufacturers put goop over the chip prior to the plastic going >> around the leadframe. I assume that goop has high resistivity. >> > The goop would have to be much less expensive that package plastic or > preserve exotic properties like ultra low leakage. > > ?-) >
The goop is something to do with packaging in general, not low leakage. Not everyone uses it. Wafer test is simply to save packaging parts that will fail at final test anyway. Nobody, or at least no place I ever worked, packages parts and didn't test them. Plenty can go wrong in backlap, bonding, packaging, etc. Everything with electrical limits is tested at ATE at all grades at room temp for packaged parts. If you look carefully, you may see GBD (guaranteed by design). That can mean a lot of things. If it is a capacitance at a pin, the assumption is if the wafer passed parametric testing, then the pin capacitance will be totally predictable, hence GBD. If the part has a reference in it. the drift at elevated temperature in theory can correlate to the drift at cold temperature. All the tests have guardbands. Depending on the company, some test wide at wafer then accept the rejects at final. You do this is the chips are expensive. That is, you are willing to spend some money packaging borderline parts in order to get product to sell. The other scheme is to test tight at wafer and then have looser limts as the part goes down the test flow. That is, the test limits are tighter than the datasheet spec at wafer. At QA, the test limits are exactly what is on the datasheet less the bench to ATE correlation error. That is, somebody should be able to bench test the part and have it pass publsihed electricals. If you are not familiar with parameter wafer testing, the devices on the test pattern have to meet test criteria before product wafer testing is done. If something fails the parametric test, then a decision is made to see if the parts are OK to sell in terms of reliability. That is, say the oxide breakdown was out of spec. You would probably reject the wafer just because you don't trust it. Put if a parameter is off on a device you don't use (say epifet), then the wafer can go off to production wafer test.