Reply by Jim Thompson March 19, 20122012-03-19
On Sun, 18 Mar 2012 20:27:56 -0800, Robert Baer
<robertbaer@localnet.com> wrote:

>Jim Thompson wrote: >> On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer >> <robertbaer@localnet.com> wrote: >> >>> Jim Thompson wrote: >>>> >> [snip] >>>> >>>> In the I/C world a "pure" diode, unencumbered by parasitic junctions >>>> does not exist. So you can rest assured that a "diode" on an I/C >>>> schematic is actually a three (or more) layer device, connected in >>>> diode mode. >>>> >>>> That's why I'm always wary of more than trivial currents in ESD >>>> "diodes"... the positive rail one (in most processes) is actually a >>>> PNP with a very BIG collector (otherwise known as the whole device >>>> substrate)... and the "guard ring" diffusions to limit parasitic >>>> action DO NOT go all the way thru the die thickness. >>>> >>>> ...Jim Thompson >>> Check and double check. >>> Start with something simple to illustrate: two "isolated" NPNs on a >>> substrate. In one case, if properly done in a geometrical fashion, they >>> will be matched extremely well (beta,leakage) with good thermal tracking >>> (better than 10mSec hysteresis). >>> In another case, in a high gain op-amp, the lateral PNP (base is the >>> substrate) >> >> Almost correct. See... >> >> http://www.analog-innovations.com/SED/NPN-VPNP.pdf >> >> This is a typical bipolar process cross-section. CMOS? Still a >> P-type substrate. >> >> A lateral-PNP is like a vertical-PNP except there are two P-base >> emitters side-by-side... plus a feeble attempt to kill the vertical >> device by adding buried layer >> >>> Q1 to Q2 could have a beta of 0.000001 or so and give hell in >>> feedback - all the way across a chip where Q1 is part the op-amp input >>> and Q2 is part of the output. >>> A measly gain over 10^6 can be trouble in river city. >>> Happened in the first cut for the uA741 at (the original) Fairchild. >>> If i remember right, the solution was to wrap a vertical PNP around >>> the output and make it a DCT to kill the beta across the chip. >> >> But you are right, all kinds of sneak paths to "brighten" (*) your >> day. >> >> (*) I had a complex pin driver chip, ~1980, that glowed in the dark >> ;-) >> >> ...Jim Thompson > Too bad that the glow effect was not looked into..then become an >early LED and maybe an analog controllable LED.
That was back in the days when we didn't have multi-layer metal, so an N+ crossover made an unintended device that light-emitted. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by Phil Hobbs March 19, 20122012-03-19
Robert Baer wrote:
> > Jim Thompson wrote: > > On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer > > <robertbaer@localnet.com> wrote: > > > >> Jim Thompson wrote: > >>> > > [snip] > >>> > >>> In the I/C world a "pure" diode, unencumbered by parasitic junctions > >>> does not exist. So you can rest assured that a "diode" on an I/C > >>> schematic is actually a three (or more) layer device, connected in > >>> diode mode. > >>> > >>> That's why I'm always wary of more than trivial currents in ESD > >>> "diodes"... the positive rail one (in most processes) is actually a > >>> PNP with a very BIG collector (otherwise known as the whole device > >>> substrate)... and the "guard ring" diffusions to limit parasitic > >>> action DO NOT go all the way thru the die thickness. > >>> > >>> ...Jim Thompson > >> Check and double check. > >> Start with something simple to illustrate: two "isolated" NPNs on a > >> substrate. In one case, if properly done in a geometrical fashion, they > >> will be matched extremely well (beta,leakage) with good thermal tracking > >> (better than 10mSec hysteresis). > >> In another case, in a high gain op-amp, the lateral PNP (base is the > >> substrate) > > > > Almost correct. See... > > > > http://www.analog-innovations.com/SED/NPN-VPNP.pdf > > > > This is a typical bipolar process cross-section. CMOS? Still a > > P-type substrate. > > > > A lateral-PNP is like a vertical-PNP except there are two P-base > > emitters side-by-side... plus a feeble attempt to kill the vertical > > device by adding buried layer > > > >> Q1 to Q2 could have a beta of 0.000001 or so and give hell in > >> feedback - all the way across a chip where Q1 is part the op-amp input > >> and Q2 is part of the output. > >> A measly gain over 10^6 can be trouble in river city. > >> Happened in the first cut for the uA741 at (the original) Fairchild. > >> If i remember right, the solution was to wrap a vertical PNP around > >> the output and make it a DCT to kill the beta across the chip. > > > > But you are right, all kinds of sneak paths to "brighten" (*) your > > day. > > > > (*) I had a complex pin driver chip, ~1980, that glowed in the dark > > ;-) > > > > ...Jim Thompson > Too bad that the glow effect was not looked into..then become an > early LED and maybe an analog controllable LED.
Photoemission from silicon is a commonly-used diagnostic tool. Ordinary recombination produces ~1.1 um photons, which you can see through a thinned die, and hot carriers produce visible photons. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
Reply by Robert Baer March 19, 20122012-03-19
Jim Thompson wrote:
> On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer > <robertbaer@localnet.com> wrote: > >> Jim Thompson wrote: >>> > [snip] >>> >>> In the I/C world a "pure" diode, unencumbered by parasitic junctions >>> does not exist. So you can rest assured that a "diode" on an I/C >>> schematic is actually a three (or more) layer device, connected in >>> diode mode. >>> >>> That's why I'm always wary of more than trivial currents in ESD >>> "diodes"... the positive rail one (in most processes) is actually a >>> PNP with a very BIG collector (otherwise known as the whole device >>> substrate)... and the "guard ring" diffusions to limit parasitic >>> action DO NOT go all the way thru the die thickness. >>> >>> ...Jim Thompson >> Check and double check. >> Start with something simple to illustrate: two "isolated" NPNs on a >> substrate. In one case, if properly done in a geometrical fashion, they >> will be matched extremely well (beta,leakage) with good thermal tracking >> (better than 10mSec hysteresis). >> In another case, in a high gain op-amp, the lateral PNP (base is the >> substrate) > > Almost correct. See... > > http://www.analog-innovations.com/SED/NPN-VPNP.pdf > > This is a typical bipolar process cross-section. CMOS? Still a > P-type substrate. > > A lateral-PNP is like a vertical-PNP except there are two P-base > emitters side-by-side... plus a feeble attempt to kill the vertical > device by adding buried layer > >> Q1 to Q2 could have a beta of 0.000001 or so and give hell in >> feedback - all the way across a chip where Q1 is part the op-amp input >> and Q2 is part of the output. >> A measly gain over 10^6 can be trouble in river city. >> Happened in the first cut for the uA741 at (the original) Fairchild. >> If i remember right, the solution was to wrap a vertical PNP around >> the output and make it a DCT to kill the beta across the chip. > > But you are right, all kinds of sneak paths to "brighten" (*) your > day. > > (*) I had a complex pin driver chip, ~1980, that glowed in the dark > ;-) > > ...Jim Thompson
OK; Q1 NPN base is emitter of substrate lateral with that beta of 0.000001, Q2 NPN base is the collector.. Still think a vertical PNP (nice drawing!) was used as a beta killer.
Reply by Robert Baer March 19, 20122012-03-19
Jim Thompson wrote:
> On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer > <robertbaer@localnet.com> wrote: > >> Jim Thompson wrote: >>> > [snip] >>> >>> In the I/C world a "pure" diode, unencumbered by parasitic junctions >>> does not exist. So you can rest assured that a "diode" on an I/C >>> schematic is actually a three (or more) layer device, connected in >>> diode mode. >>> >>> That's why I'm always wary of more than trivial currents in ESD >>> "diodes"... the positive rail one (in most processes) is actually a >>> PNP with a very BIG collector (otherwise known as the whole device >>> substrate)... and the "guard ring" diffusions to limit parasitic >>> action DO NOT go all the way thru the die thickness. >>> >>> ...Jim Thompson >> Check and double check. >> Start with something simple to illustrate: two "isolated" NPNs on a >> substrate. In one case, if properly done in a geometrical fashion, they >> will be matched extremely well (beta,leakage) with good thermal tracking >> (better than 10mSec hysteresis). >> In another case, in a high gain op-amp, the lateral PNP (base is the >> substrate) > > Almost correct. See... > > http://www.analog-innovations.com/SED/NPN-VPNP.pdf > > This is a typical bipolar process cross-section. CMOS? Still a > P-type substrate. > > A lateral-PNP is like a vertical-PNP except there are two P-base > emitters side-by-side... plus a feeble attempt to kill the vertical > device by adding buried layer > >> Q1 to Q2 could have a beta of 0.000001 or so and give hell in >> feedback - all the way across a chip where Q1 is part the op-amp input >> and Q2 is part of the output. >> A measly gain over 10^6 can be trouble in river city. >> Happened in the first cut for the uA741 at (the original) Fairchild. >> If i remember right, the solution was to wrap a vertical PNP around >> the output and make it a DCT to kill the beta across the chip. > > But you are right, all kinds of sneak paths to "brighten" (*) your > day. > > (*) I had a complex pin driver chip, ~1980, that glowed in the dark > ;-) > > ...Jim Thompson
Too bad that the glow effect was not looked into..then become an early LED and maybe an analog controllable LED.
Reply by LM March 18, 20122012-03-18
> (*) I had a complex pin driver chip, ~1980, that glowed in the dark > ;-)
Interesting, how did that happen? I'm sure this is on topic, of course.
Reply by Jim Thompson March 18, 20122012-03-18
On Sat, 17 Mar 2012 18:26:01 -0800, Robert Baer
<robertbaer@localnet.com> wrote:

>Jim Thompson wrote: >>
[snip]
>> >> In the I/C world a "pure" diode, unencumbered by parasitic junctions >> does not exist. So you can rest assured that a "diode" on an I/C >> schematic is actually a three (or more) layer device, connected in >> diode mode. >> >> That's why I'm always wary of more than trivial currents in ESD >> "diodes"... the positive rail one (in most processes) is actually a >> PNP with a very BIG collector (otherwise known as the whole device >> substrate)... and the "guard ring" diffusions to limit parasitic >> action DO NOT go all the way thru the die thickness. >> >> ...Jim Thompson > Check and double check. > Start with something simple to illustrate: two "isolated" NPNs on a >substrate. In one case, if properly done in a geometrical fashion, they >will be matched extremely well (beta,leakage) with good thermal tracking >(better than 10mSec hysteresis). > In another case, in a high gain op-amp, the lateral PNP (base is the >substrate)
Almost correct. See... http://www.analog-innovations.com/SED/NPN-VPNP.pdf This is a typical bipolar process cross-section. CMOS? Still a P-type substrate. A lateral-PNP is like a vertical-PNP except there are two P-base emitters side-by-side... plus a feeble attempt to kill the vertical device by adding buried layer
> Q1 to Q2 could have a beta of 0.000001 or so and give hell in >feedback - all the way across a chip where Q1 is part the op-amp input >and Q2 is part of the output. > A measly gain over 10^6 can be trouble in river city. > Happened in the first cut for the uA741 at (the original) Fairchild. > If i remember right, the solution was to wrap a vertical PNP around >the output and make it a DCT to kill the beta across the chip.
But you are right, all kinds of sneak paths to "brighten" (*) your day. (*) I had a complex pin driver chip, ~1980, that glowed in the dark ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by Robert Baer March 17, 20122012-03-17
Jim Thompson wrote:
> On 17 Mar 2012 19:49:07 GMT, Jasen Betts<jasen@xnet.co.nz> wrote: > >> On 2012-03-17, Jim Thompson<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> On 17 Mar 2012 10:32:49 GMT, Jasen Betts<jasen@xnet.co.nz> wrote: >>> >>>> On 2012-03-16, Jim Thompson<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>>> On 15 Mar 2012 12:21:36 GMT, Jasen Betts<jasen@xnet.co.nz> wrote: >>>>> >>>>>> On 2012-03-13, bloggs.fredbloggs.fred@gmail.com<bloggs.fredbloggs.fred@gmail.com> wrote: >>>>>> >>>>>>> See figure 94 on page 43 of http://www.ti.com/lit/an/snoa653/snoa653.pdf >>>>>> >>>>>> but that has fixed gain. OP wants gain proportional to VCC. >>>>>> >>>>>> Figure 3 has the current mirror drawn in a way I've not seen before. >>>>> >>>>> Elaborate on what it is that you find strange. It's a so-called >>>>> "Norton" amplifier. >>>> >>>> Where I would have expected a diode connected transistor just a diode >>>> is drawn. >>> >>> That's "artistic license" taken by the village idiots in the >>> applications department. Unfortunately, quite early on, datasheets >>> and appnotes weren't written by the designer. >> >> That's good to know, I spent an hour or so searching for a schematic >> with a proper current mirror in vain, trying to reason why a diode >> would be used there. > > In the I/C world a "pure" diode, unencumbered by parasitic junctions > does not exist. So you can rest assured that a "diode" on an I/C > schematic is actually a three (or more) layer device, connected in > diode mode. > > That's why I'm always wary of more than trivial currents in ESD > "diodes"... the positive rail one (in most processes) is actually a > PNP with a very BIG collector (otherwise known as the whole device > substrate)... and the "guard ring" diffusions to limit parasitic > action DO NOT go all the way thru the die thickness. > > ...Jim Thompson
Check and double check. Start with something simple to illustrate: two "isolated" NPNs on a substrate. In one case, if properly done in a geometrical fashion, they will be matched extremely well (beta,leakage) with good thermal tracking (better than 10mSec hysteresis). In another case, in a high gain op-amp, the lateral PNP (base is the substrate) Q1 to Q2 could have a beta of 0.000001 or so and give hell in feedback - all the way across a chip where Q1 is part the op-amp input and Q2 is part of the output. A measly gain over 10^6 can be trouble in river city. Happened in the first cut for the uA741 at (the original) Fairchild. If i remember right, the solution was to wrap a vertical PNP around the output and make it a DCT to kill the beta across the chip.
Reply by Jim Thompson March 17, 20122012-03-17
On 17 Mar 2012 19:49:07 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

>On 2012-03-17, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> On 17 Mar 2012 10:32:49 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >> >>>On 2012-03-16, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> On 15 Mar 2012 12:21:36 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >>>> >>>>>On 2012-03-13, bloggs.fredbloggs.fred@gmail.com <bloggs.fredbloggs.fred@gmail.com> wrote: >>>>> >>>>>> See figure 94 on page 43 of http://www.ti.com/lit/an/snoa653/snoa653.pdf >>>>> >>>>>but that has fixed gain. OP wants gain proportional to VCC. >>>>> >>>>>Figure 3 has the current mirror drawn in a way I've not seen before. >>>> >>>> Elaborate on what it is that you find strange. It's a so-called >>>> "Norton" amplifier. >>> >>>Where I would have expected a diode connected transistor just a diode >>>is drawn. >> >> That's "artistic license" taken by the village idiots in the >> applications department. Unfortunately, quite early on, datasheets >> and appnotes weren't written by the designer. > >That's good to know, I spent an hour or so searching for a schematic >with a proper current mirror in vain, trying to reason why a diode >would be used there.
In the I/C world a "pure" diode, unencumbered by parasitic junctions does not exist. So you can rest assured that a "diode" on an I/C schematic is actually a three (or more) layer device, connected in diode mode. That's why I'm always wary of more than trivial currents in ESD "diodes"... the positive rail one (in most processes) is actually a PNP with a very BIG collector (otherwise known as the whole device substrate)... and the "guard ring" diffusions to limit parasitic action DO NOT go all the way thru the die thickness. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by Jasen Betts March 17, 20122012-03-17
On 2012-03-17, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:
> On 17 Mar 2012 10:32:49 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: > >>On 2012-03-16, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> On 15 Mar 2012 12:21:36 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >>> >>>>On 2012-03-13, bloggs.fredbloggs.fred@gmail.com <bloggs.fredbloggs.fred@gmail.com> wrote: >>>> >>>>> See figure 94 on page 43 of http://www.ti.com/lit/an/snoa653/snoa653.pdf >>>> >>>>but that has fixed gain. OP wants gain proportional to VCC. >>>> >>>>Figure 3 has the current mirror drawn in a way I've not seen before. >>> >>> Elaborate on what it is that you find strange. It's a so-called >>> "Norton" amplifier. >> >>Where I would have expected a diode connected transistor just a diode >>is drawn. > > That's "artistic license" taken by the village idiots in the > applications department. Unfortunately, quite early on, datasheets > and appnotes weren't written by the designer.
That's good to know, I spent an hour or so searching for a schematic with a proper current mirror in vain, trying to reason why a diode would be used there. -- &#9858;&#9859; 100% natural --- Posted via news://freenews.netfront.net/ - Complaints to news@netfront.net ---
Reply by Jim Thompson March 17, 20122012-03-17
On 17 Mar 2012 10:32:49 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

>On 2012-03-16, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> On 15 Mar 2012 12:21:36 GMT, Jasen Betts <jasen@xnet.co.nz> wrote: >> >>>On 2012-03-13, bloggs.fredbloggs.fred@gmail.com <bloggs.fredbloggs.fred@gmail.com> wrote: >>> >>>> See figure 94 on page 43 of http://www.ti.com/lit/an/snoa653/snoa653.pdf >>> >>>but that has fixed gain. OP wants gain proportional to VCC. >>> >>>Figure 3 has the current mirror drawn in a way I've not seen before. >> >> Elaborate on what it is that you find strange. It's a so-called >> "Norton" amplifier. > >Where I would have expected a diode connected transistor just a diode >is drawn.
That's "artistic license" taken by the village idiots in the applications department. Unfortunately, quite early on, datasheets and appnotes weren't written by the designer. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.