Charlie E. expounded in
news:3epq47d5rekuofkfafh0qseeodajeuc4od@4ax.com:
> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg
> <invalid@invalid.invalid> wrote:
>>I find this sim behavior odd. It seems only naturaly that,
>>in a "what-if" scenario, an engineer disconnects just one
>>leg of a part. After all, that's how we also do it in real
>>life. SPICE is not supposed to "partially smoosh that" and
>>then not tell anyone.
>
> Hi Joerg,
> Yes, it looks like you have hit another of those
> 'interesting assumptions' that always come up and bite us
> on the posterior.
>
> Spice has to have everything connected Somewhere, and have
> a path to ground from that connection. ... I am afraid it is
> just a part of learning the capabilities of the tools...
> 8-)
>
> Charlie
I have seen LTspice compain about a missing ground. But in
other circuits the problem remained unreported. So this is
likey a software correctness issue.
Warren
Reply by josephkk●August 19, 20112011-08-19
On Fri, 19 Aug 2011 08:03:25 -0700, Joerg <invalid@invalid.invalid> =
wrote:
>josephkk wrote:
>> On Mon, 15 Aug 2011 07:29:01 -0700, Joerg <invalid@invalid.invalid> =
wrote:
>>=20
>>> nuny@bid.nes wrote:
>>>> On Aug 14, 3:33 pm, Joerg <inva...@invalid.invalid> wrote:
>>>>> Folks,
>>>>>
>>>>> This is close to voodoo but repeatable. Unfortunately I can't =
disclose
>>>>> the schematic since it is for a client. Just wondering , anyone had=
this
>>>>> before?
>>>>>
>>>>> At the far end of a TX line I used to have a diode connected across
>>>>> because a previous version of a chip would have such a substrat =
path.
>>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now =
the
>>>>> new iteration of the chip design won't have this diode path so I =
chopped
>>>>> off its cathode connection. Sims fine. So I deleted the diode ->
>>>>> ka-crunch ... sim slows down and the ouput is junk.
>>>>>
>>>>> If I put the diode back in and connect only its anode -> fine. If I
>>>>> leave the anode open and only connect the cathode it still sims but=
the
>>>>> results are different.
>>>>>
>>>>> <scratching head>
>>>> I really hate to ask this, but have you "simulated" your LTSpice
>>>> results in hardware yet?
>>>>
>>> No, can't do that yet. It's an IC and that is not taped out yet.
>>>
>> Is someone of crazy here (very possibly me, i have not done an actual =
IC
>> design)? How can you dare try tapeout before having a believable
>> simulation? Can't you get adequate device models without tapeout? ...
>
>
>The IC is completely simulated out on the big Mentor simulator, not
>LTSpice It's about the system interface, not the IC.
>
>
>> ... Do
>> they even know which fab and process they are going to use?
>
>
>Oh yes, they do and I do :-)
>
>When you do an IC of this complexity you tailor it to a specific process
>right from the beginning.
>
>[...]
Thanks, i am glad that neither of us is all that crazy. I guess i only
scared myself.
?-/
Reply by nuny...@bid.nes●August 19, 20112011-08-19
On Aug 19, 2:20=A0am, josephkk <joseph_barr...@sbcglobal.net> wrote:
> On Mon, 15 Aug 2011 07:29:01 -0700, Joerg <inva...@invalid.invalid> wrote=
:
> >n...@bid.nes wrote:
> >> On Aug 14, 3:33 pm, Joerg <inva...@invalid.invalid> wrote:
> >>> Folks,
>
> >>> This is close to voodoo but repeatable. Unfortunately I can't disclos=
e
> >>> the schematic since it is for a client. Just wondering , anyone had t=
his
> >>> before?
>
> >>> At the far end of a TX line I used to have a diode connected across
> >>> because a previous version of a chip would have such a substrat path.
> >>> Nice waveforms, fast sims. Everything as expected and peachy. Now the
> >>> new iteration of the chip design won't have this diode path so I chop=
ped
> >>> off its cathode connection. Sims fine. So I deleted the diode ->
> >>> ka-crunch ... sim slows down and the ouput is junk.
>
> >>> If I put the diode back in and connect only its anode -> fine. If I
> >>> leave the anode open and only connect the cathode it still sims but t=
he
> >>> results are different.
>
> >>> <scratching head>
>
> >> =A0 I really hate to ask this, but have you "simulated" your LTSpice
> >> results in hardware yet?
>
> >No, can't do that yet. It's an IC and that is not taped out yet.
>
> Is someone of crazy here (very possibly me, i have not done an actual IC
> design)? =A0How can you dare try tapeout before having a believable
> simulation? =A0Can't you get adequate device models without tapeout? =A0D=
o
> they even know which fab and process they are going to use?
My point was that when a mathematical model blows up (gives
unphysical results or just crashes), it indicates the model does not
accurately "model" reality and a "reality check" is in order.
> >> =A0 Also, what's the RF voltage level on the line?
>
> >About 100V, and then from microvolts up to a volt during receive
> >depending on signal strength coming in.
I was wondering here about whether LTSpice can accurately model a
diode acting as an antenna the way they actually do.
Mark L. Fergerson
Reply by Spehro Pefhany●August 19, 20112011-08-19
On Fri, 19 Aug 2011 14:01:07 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
>On 08/19/2011 12:41 PM, Joerg wrote:
>> Phil Hobbs wrote:
>>> On 08/19/2011 10:59 AM, Joerg wrote:
>>>> Charlie E. wrote:
>>>>> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg<invalid@invalid.invalid>
>>>>> wrote:
>>>>>
>>>>>> Interesting, I also grew up with good old ECA224 but that was when the
>>>>>> 286 was the latest and greatest. It was quite a useful simulator.
>>>>>> Someone told me it merged into EWB but when I tried that at a client I
>>>>>> did not like it anymore. For my consulting office I bought MicroSim
>>>>>> PSpice. It came with those nice cloth covered IBM-style binders.
>>>>>>
>>>>>> I find this sim behavior odd. It seems only naturaly that, in a
>>>>>> "what-if" scenario, an engineer disconnects just one leg of a part.
>>>>>> After all, that's how we also do it in real life. SPICE is not supposed
>>>>>> to "partially smoosh that" and then not tell anyone.
>>>>>
>>>>> Hi Joerg,
>>>>> Yes, it looks like you have hit another of those 'interesting
>>>>> assumptions' that always come up and bite us on the posterior.
>>>>>
>>>>> Spice has to have everything connected Somewhere, and have a path to
>>>>> ground from that connection. ...
>>>>
>>>>
>>>> Why? Why can't it just do the only correct thing and pretend a diode
>>>> with one side disconnected is no longer part of the netlist? That's not
>>>> hard to implement.
>>>>
>>>>
>>>>> ... In the real world, you can have things
>>>>> that go nowhere, and there is no problem. Some spice progs will just
>>>>> give you an error message and say "Where is this supposed to connect,
>>>>> dummy?" while others, like you have run into, try to help out and
>>>>> assume you have a floating node, and it should connect to ground
>>>>> through a high value reisistance. I am afraid it is just a part of
>>>>> learning the capabilities of the tools... 8-)
>>>>>
>>>>
>>>> Or the tools should learn to follow breadboarding strategies more
>>>> closely :-)
>>>>
>>>
>>> So all standoffs should be 22 meg?
>>>
>>
>> No, no, this implies the kludgy kind of experimenting. No standoffs.
>> Wire cutters ... snip ... pinggggg ... oh, looks bad, we need this, got
>> to solder it back on ... bend it down ... apply liberal gob of solder.
>>
>
>Dead bug Muntzing!
Or as Antoine de Saint Exup�ry might say, "Il semble que la perfection
soit atteinte non quand il n'y a plus rien � ajouter, mais quand il
n'y a plus rien � retrancher".
(perfection is attained not when there is no longer anything to add,
but when there is no longer anything to take away )
>
>Cheers
>
>Phil Hobbs
Reply by Phil Hobbs●August 19, 20112011-08-19
On 08/19/2011 12:41 PM, Joerg wrote:
> Phil Hobbs wrote:
>> On 08/19/2011 10:59 AM, Joerg wrote:
>>> Charlie E. wrote:
>>>> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg<invalid@invalid.invalid>
>>>> wrote:
>>>>
>>>>> Interesting, I also grew up with good old ECA224 but that was when the
>>>>> 286 was the latest and greatest. It was quite a useful simulator.
>>>>> Someone told me it merged into EWB but when I tried that at a client I
>>>>> did not like it anymore. For my consulting office I bought MicroSim
>>>>> PSpice. It came with those nice cloth covered IBM-style binders.
>>>>>
>>>>> I find this sim behavior odd. It seems only naturaly that, in a
>>>>> "what-if" scenario, an engineer disconnects just one leg of a part.
>>>>> After all, that's how we also do it in real life. SPICE is not supposed
>>>>> to "partially smoosh that" and then not tell anyone.
>>>>
>>>> Hi Joerg,
>>>> Yes, it looks like you have hit another of those 'interesting
>>>> assumptions' that always come up and bite us on the posterior.
>>>>
>>>> Spice has to have everything connected Somewhere, and have a path to
>>>> ground from that connection. ...
>>>
>>>
>>> Why? Why can't it just do the only correct thing and pretend a diode
>>> with one side disconnected is no longer part of the netlist? That's not
>>> hard to implement.
>>>
>>>
>>>> ... In the real world, you can have things
>>>> that go nowhere, and there is no problem. Some spice progs will just
>>>> give you an error message and say "Where is this supposed to connect,
>>>> dummy?" while others, like you have run into, try to help out and
>>>> assume you have a floating node, and it should connect to ground
>>>> through a high value reisistance. I am afraid it is just a part of
>>>> learning the capabilities of the tools... 8-)
>>>>
>>>
>>> Or the tools should learn to follow breadboarding strategies more
>>> closely :-)
>>>
>>
>> So all standoffs should be 22 meg?
>>
>
> No, no, this implies the kludgy kind of experimenting. No standoffs.
> Wire cutters ... snip ... pinggggg ... oh, looks bad, we need this, got
> to solder it back on ... bend it down ... apply liberal gob of solder.
>
Dead bug Muntzing!
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Reply by Joerg●August 19, 20112011-08-19
Phil Hobbs wrote:
> On 08/19/2011 10:59 AM, Joerg wrote:
>> Charlie E. wrote:
>>> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg<invalid@invalid.invalid>
>>> wrote:
>>>
>>>> Interesting, I also grew up with good old ECA224 but that was when the
>>>> 286 was the latest and greatest. It was quite a useful simulator.
>>>> Someone told me it merged into EWB but when I tried that at a client I
>>>> did not like it anymore. For my consulting office I bought MicroSim
>>>> PSpice. It came with those nice cloth covered IBM-style binders.
>>>>
>>>> I find this sim behavior odd. It seems only naturaly that, in a
>>>> "what-if" scenario, an engineer disconnects just one leg of a part.
>>>> After all, that's how we also do it in real life. SPICE is not supposed
>>>> to "partially smoosh that" and then not tell anyone.
>>>
>>> Hi Joerg,
>>> Yes, it looks like you have hit another of those 'interesting
>>> assumptions' that always come up and bite us on the posterior.
>>>
>>> Spice has to have everything connected Somewhere, and have a path to
>>> ground from that connection. ...
>>
>>
>> Why? Why can't it just do the only correct thing and pretend a diode
>> with one side disconnected is no longer part of the netlist? That's not
>> hard to implement.
>>
>>
>>> ... In the real world, you can have things
>>> that go nowhere, and there is no problem. Some spice progs will just
>>> give you an error message and say "Where is this supposed to connect,
>>> dummy?" while others, like you have run into, try to help out and
>>> assume you have a floating node, and it should connect to ground
>>> through a high value reisistance. I am afraid it is just a part of
>>> learning the capabilities of the tools... 8-)
>>>
>>
>> Or the tools should learn to follow breadboarding strategies more
>> closely :-)
>>
>
> So all standoffs should be 22 meg?
>
No, no, this implies the kludgy kind of experimenting. No standoffs.
Wire cutters ... snip ... pinggggg ... oh, looks bad, we need this, got
to solder it back on ... bend it down ... apply liberal gob of solder.
--
Regards, Joerg
http://www.analogconsultants.com/
Reply by Phil Hobbs●August 19, 20112011-08-19
On 08/19/2011 10:59 AM, Joerg wrote:
> Charlie E. wrote:
>> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg<invalid@invalid.invalid>
>> wrote:
>>
>>> Interesting, I also grew up with good old ECA224 but that was when the
>>> 286 was the latest and greatest. It was quite a useful simulator.
>>> Someone told me it merged into EWB but when I tried that at a client I
>>> did not like it anymore. For my consulting office I bought MicroSim
>>> PSpice. It came with those nice cloth covered IBM-style binders.
>>>
>>> I find this sim behavior odd. It seems only naturaly that, in a
>>> "what-if" scenario, an engineer disconnects just one leg of a part.
>>> After all, that's how we also do it in real life. SPICE is not supposed
>>> to "partially smoosh that" and then not tell anyone.
>>
>> Hi Joerg,
>> Yes, it looks like you have hit another of those 'interesting
>> assumptions' that always come up and bite us on the posterior.
>>
>> Spice has to have everything connected Somewhere, and have a path to
>> ground from that connection. ...
>
>
> Why? Why can't it just do the only correct thing and pretend a diode
> with one side disconnected is no longer part of the netlist? That's not
> hard to implement.
>
>
>> ... In the real world, you can have things
>> that go nowhere, and there is no problem. Some spice progs will just
>> give you an error message and say "Where is this supposed to connect,
>> dummy?" while others, like you have run into, try to help out and
>> assume you have a floating node, and it should connect to ground
>> through a high value reisistance. I am afraid it is just a part of
>> learning the capabilities of the tools... 8-)
>>
>
> Or the tools should learn to follow breadboarding strategies more
> closely :-)
>
So all standoffs should be 22 meg?
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Reply by Joerg●August 19, 20112011-08-19
josephkk wrote:
> On Mon, 15 Aug 2011 07:29:01 -0700, Joerg <invalid@invalid.invalid> wrote:
>
>> nuny@bid.nes wrote:
>>> On Aug 14, 3:33 pm, Joerg <inva...@invalid.invalid> wrote:
>>>> Folks,
>>>>
>>>> This is close to voodoo but repeatable. Unfortunately I can't disclose
>>>> the schematic since it is for a client. Just wondering , anyone had this
>>>> before?
>>>>
>>>> At the far end of a TX line I used to have a diode connected across
>>>> because a previous version of a chip would have such a substrat path.
>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now the
>>>> new iteration of the chip design won't have this diode path so I chopped
>>>> off its cathode connection. Sims fine. So I deleted the diode ->
>>>> ka-crunch ... sim slows down and the ouput is junk.
>>>>
>>>> If I put the diode back in and connect only its anode -> fine. If I
>>>> leave the anode open and only connect the cathode it still sims but the
>>>> results are different.
>>>>
>>>> <scratching head>
>>> I really hate to ask this, but have you "simulated" your LTSpice
>>> results in hardware yet?
>>>
>> No, can't do that yet. It's an IC and that is not taped out yet.
>>
> Is someone of crazy here (very possibly me, i have not done an actual IC
> design)? How can you dare try tapeout before having a believable
> simulation? Can't you get adequate device models without tapeout? ...
The IC is completely simulated out on the big Mentor simulator, not
LTSpice It's about the system interface, not the IC.
> ... Do
> they even know which fab and process they are going to use?
Oh yes, they do and I do :-)
When you do an IC of this complexity you tailor it to a specific process
right from the beginning.
[...]
--
Regards, Joerg
http://www.analogconsultants.com/
Reply by Joerg●August 19, 20112011-08-19
josephkk wrote:
> On Mon, 15 Aug 2011 09:44:56 -0700, Joerg <invalid@invalid.invalid> wrote:
>
>> nuny@bid.nes wrote:
>>> On 8/15/2011 7:29 AM, Joerg wrote:
>>>> nuny@bid.nes wrote:
>>>>> On Aug 14, 3:33 pm, Joerg<inva...@invalid.invalid> wrote:
>>>>>> Folks,
>>>>>>
>>>>>> This is close to voodoo but repeatable. Unfortunately I can't disclose
>>>>>> the schematic since it is for a client. Just wondering , anyone had
>>>>>> this
>>>>>> before?
>>>>>>
>>>>>> At the far end of a TX line I used to have a diode connected across
>>>>>> because a previous version of a chip would have such a substrat path.
>>>>>> Nice waveforms, fast sims. Everything as expected and peachy. Now the
>>>>>> new iteration of the chip design won't have this diode path so I
>>>>>> chopped
>>>>>> off its cathode connection. Sims fine. So I deleted the diode ->
>>>>>> ka-crunch ... sim slows down and the ouput is junk.
>>>>>>
>>>>>> If I put the diode back in and connect only its anode -> fine. If I
>>>>>> leave the anode open and only connect the cathode it still sims but the
>>>>>> results are different.
>>>>>>
>>>>>> <scratching head>
>>>>> I really hate to ask this, but have you "simulated" your LTSpice
>>>>> results in hardware yet?
>>>> No, can't do that yet. It's an IC and that is not taped out yet.
>>> Dang. Do you have an example of the old setup handy on which you can
>>> try your diode changes as above?
>>>
>> No, this IC will be totally new turf. Reason for my sims is the we now
>> have to take care of the design of the connecting electronics while
>> it'll be in production. That way it'll all come together at roughly the
>> same time.
>>
>>
>>>>> Also, what's the RF voltage level on the line?
>>>> About 100V, and then from microvolts up to a volt during receive
>>>> depending on signal strength coming in.
>>> I thought it might be high. Think; what happens with a real diode
>>> connected as described above in such a field?
>>>
>> In the end we'll have to live with whatever the IC has, there is
>> practically no space for any other parts to the right of the TX line.
>>
>>
>>> Anyway, if it were me I'd stop fiddling with the diode and just use a
>>> terminating resistor.
>>>
>>> Of course, once the chip was ready I'd try it with the diode, just to
>>> see. ;>)
>>>
>> I might. But we can't place diodes because it's multi-channel and that
>> would be lots of parts in a space that isn't there :-)
>>
>> It's no problem because the signals going up can be shaped accordingly.
>> I was just wondering why LTSpice is producing inconsistent results here.
>> It's ok if it runs into a dead end with some calcs but I'd have thought
>> that would caused the usual error messages. Yet I get none of those.
>
> I can totally understand being uneasy committing to an IC design with a
> sim that i could not trust.
>
> On Wed, 17 Aug 2011 11:02:07 -0700, Joerg <invalid@invalid.invalid>
> wrote:
>
>> Interesting, I also grew up with good old ECA224 but that was when the
>> 286 was the latest and greatest. It was quite a useful simulator.
>> Someone told me it merged into EWB but when I tried that at a client I
>> did not like it anymore. For my consulting office I bought MicroSim
>> PSpice. It came with those nice cloth covered IBM-style binders.
>>
>> I find this sim behavior odd. It seems only naturaly that, in a
>> "what-if" scenario, an engineer disconnects just one leg of a part.
>> After all, that's how we also do it in real life. SPICE is not supposed
>> to "partially smoosh that" and then not tell anyone.
>
> Hi Joerg,
> Yes, it looks like you have hit another of those 'interesting
> assumptions' that always come up and bite us on the posterior.
>
> Spice has to have everything connected Somewhere, and have a path to
> ground from that connection. ...
Why? Why can't it just do the only correct thing and pretend a diode
with one side disconnected is no longer part of the netlist? That's not
hard to implement.
> ... In the real world, you can have things
> that go nowhere, and there is no problem. Some spice progs will just
> give you an error message and say "Where is this supposed to connect,
> dummy?" while others, like you have run into, try to help out and
> assume you have a floating node, and it should connect to ground
> through a high value reisistance. I am afraid it is just a part of
> learning the capabilities of the tools... 8-)
>