On Wed, 13 Oct 2010 14:06:25 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:
>Does anyone have a transistor-level schematic of the CD4046 VCO?
>
>The datasheets are crocks... can't work as shown. But the general
>scheme implies that someone did a copy attempt of my vintage (mid
>'60's) MC4024 core (which was actually current mode).
>
>If someone has a working unit, take a snapshot of the voltage across
>the VCO capacitor.
>
>Thanks!
>
> ...Jim Thompson
Like as shown in...
Newsgroups: alt.binaries.schematics.electronic
Subject: LTspice subckt model for CD4046 (SED) - VCOala4046.pdf
Date: Thu, 14 Oct 2010 11:56:33 -0700
Message-ID: <hekeb6dqpm3dh73a7b5pciqhqo6pot0r9b@4ax.com>
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
Reply by Jim Thompson●October 13, 20102010-10-13
Does anyone have a transistor-level schematic of the CD4046 VCO?
The datasheets are crocks... can't work as shown. But the general
scheme implies that someone did a copy attempt of my vintage (mid
'60's) MC4024 core (which was actually current mode).
If someone has a working unit, take a snapshot of the voltage across
the VCO capacitor.
Thanks!
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
Reply by Joerg●October 11, 20102010-10-11
Helmut Sennewald wrote:
> "Joerg" <invalid@invalid.invalid> schrieb im Newsbeitrag
> news:8hetarF66lU1@mid.individual.net...
>> Helmut Sennewald wrote:
>>> "Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com>
>>> schrieb
>>> im Newsbeitrag news:lus3b69srmui4h3mkea4e7q791vcpl4i7t@4ax.com...
>>>> On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"
>>>> <helmutsennewald@t-online.de> wrote:
>>>>
>>>>> Hello,
>>>>>
>>>>> I have written sometimes ago a CD4046 model for LTspice.
>>>>> You can download it from the LTspice Yahoo group.
>>>>>
>>>>> http://tech.groups.yahoo.com/group/LTspice/
>>>>> Files > Lib > CD4046
>>>>>
>>>>> Best regards,
>>>>> Helmut
>>>>>
>>>> [snip]
>>>>
>>>> Hi Helmut,
>>>>
>>>> Thanks for a clean hierarchical schematic!
>>>>
>>>> Amusing myself with how to make a full behavioral model...
>>>>
>>>> Do you have any ideas on how to characterize a CMOS inverter?
>>>>
>>>> I think you could characterize an inverter as an input capacitance
>>>> versus input voltage and the output as a resistance variable with
>>>> input voltage and also with a capacitance likewise related.
>>>>
>>>> ...Jim Thompson
>>>> --
>>>> | James E.Thompson, CTO | mens |
>>>> | Analog Innovations, Inc. | et |
>>>> | Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
>>>> | Phoenix, Arizona 85048 Skype: Contacts Only | |
>>>> | Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
>>>> | E-mail Icon at http://www.analog-innovations.com | 1962 |
>>>>
>>>> I can see November from my house :-)
>>> Hello Jim,
>>>
>>> I haven't needed the CD4046 for myelf. I guess somebody
>>> asked for it. My goal has been to use the highest possible
>>> level of components to get it quickly done. Thus I tried
>>> to avoid the transistor level as much as possible.
>>>
>> Helmut, do you have any idea why the LTSpice group might "forget"
>> members? It shows up under "My Groups" but then a screen pops up to
>> "Join Now". Weird.
>>
>> Any chance this group might be newsserver accessible some day? Most
>> technical ones already are, via gmane. The Yahoo interface is IMHO a
>> pain, inefficient and very slow.
>>
>> --
>> Regards, Joerg
>
> Hello Joerg,
>
> "Join now" only menas you have to login with your password.
> This happens after a every few weeks for safety reason.
> Somebody from Yahoo had this bad idea to name this "Join now" instead of
> "Login".
>
> Type in your login and password.
> In the next window, directly go to Messages.
>
Thanks, Helmut, but it doesn't work anymore. After entering name and
password a 2nd time it pops over to regular Yahoo. Wants all that a 3rd
time but won't take it. Plus it moans and groans about cookies before
that and then sets ad cookies.
IMHO they have royally screwed up this time. Can't you open the LTSpice
group to gmane like the other tech groups? Then all this script kiddie
nonsense is gone and people can use it like a real newsgroup. Without
the file section, of course, for that one would have to wade through the
morass (or try ...).
--
Regards, Joerg
http://www.analogconsultants.com/
"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
Reply by Helmut Sennewald●October 11, 20102010-10-11
"Joerg" <invalid@invalid.invalid> schrieb im Newsbeitrag
news:8hetarF66lU1@mid.individual.net...
> Helmut Sennewald wrote:
>> "Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com>
>> schrieb
>> im Newsbeitrag news:lus3b69srmui4h3mkea4e7q791vcpl4i7t@4ax.com...
>>> On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"
>>> <helmutsennewald@t-online.de> wrote:
>>>
>>>> Hello,
>>>>
>>>> I have written sometimes ago a CD4046 model for LTspice.
>>>> You can download it from the LTspice Yahoo group.
>>>>
>>>> http://tech.groups.yahoo.com/group/LTspice/
>>>> Files > Lib > CD4046
>>>>
>>>> Best regards,
>>>> Helmut
>>>>
>>> [snip]
>>>
>>> Hi Helmut,
>>>
>>> Thanks for a clean hierarchical schematic!
>>>
>>> Amusing myself with how to make a full behavioral model...
>>>
>>> Do you have any ideas on how to characterize a CMOS inverter?
>>>
>>> I think you could characterize an inverter as an input capacitance
>>> versus input voltage and the output as a resistance variable with
>>> input voltage and also with a capacitance likewise related.
>>>
>>> ...Jim Thompson
>>> --
>>> | James E.Thompson, CTO | mens |
>>> | Analog Innovations, Inc. | et |
>>> | Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
>>> | Phoenix, Arizona 85048 Skype: Contacts Only | |
>>> | Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
>>> | E-mail Icon at http://www.analog-innovations.com | 1962 |
>>>
>>> I can see November from my house :-)
>>
>> Hello Jim,
>>
>> I haven't needed the CD4046 for myelf. I guess somebody
>> asked for it. My goal has been to use the highest possible
>> level of components to get it quickly done. Thus I tried
>> to avoid the transistor level as much as possible.
>>
>
> Helmut, do you have any idea why the LTSpice group might "forget"
> members? It shows up under "My Groups" but then a screen pops up to
> "Join Now". Weird.
>
> Any chance this group might be newsserver accessible some day? Most
> technical ones already are, via gmane. The Yahoo interface is IMHO a
> pain, inefficient and very slow.
>
> --
> Regards, Joerg
Hello Joerg,
"Join now" only menas you have to login with your password.
This happens after a every few weeks for safety reason.
Somebody from Yahoo had this bad idea to name this "Join now" instead of
"Login".
Type in your login and password.
In the next window, directly go to Messages.
Best regards,
Helmut
> "Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> schrieb
> im Newsbeitrag news:lus3b69srmui4h3mkea4e7q791vcpl4i7t@4ax.com...
>> On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"
>> <helmutsennewald@t-online.de> wrote:
>>
>>> Hello,
>>>
>>> I have written sometimes ago a CD4046 model for LTspice.
>>> You can download it from the LTspice Yahoo group.
>>>
>>> http://tech.groups.yahoo.com/group/LTspice/
>>> Files > Lib > CD4046
>>>
>>> Best regards,
>>> Helmut
>>>
>> [snip]
>>
>> Hi Helmut,
>>
>> Thanks for a clean hierarchical schematic!
>>
>> Amusing myself with how to make a full behavioral model...
>>
>> Do you have any ideas on how to characterize a CMOS inverter?
>>
>> I think you could characterize an inverter as an input capacitance
>> versus input voltage and the output as a resistance variable with
>> input voltage and also with a capacitance likewise related.
>>
>> ...Jim Thompson
>> --
>> | James E.Thompson, CTO | mens |
>> | Analog Innovations, Inc. | et |
>> | Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
>> | Phoenix, Arizona 85048 Skype: Contacts Only | |
>> | Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
>> | E-mail Icon at http://www.analog-innovations.com | 1962 |
>>
>> I can see November from my house :-)
>
> Hello Jim,
>
> I haven't needed the CD4046 for myelf. I guess somebody
> asked for it. My goal has been to use the highest possible
> level of components to get it quickly done. Thus I tried
> to avoid the transistor level as much as possible.
>
Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.
Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.
--
Regards, Joerg
http://www.analogconsultants.com/
"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
Reply by Helmut Sennewald●October 10, 20102010-10-10
"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> schrieb
im Newsbeitrag news:lus3b69srmui4h3mkea4e7q791vcpl4i7t@4ax.com...
> On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"
> <helmutsennewald@t-online.de> wrote:
>
>>Hello,
>>
>>I have written sometimes ago a CD4046 model for LTspice.
>>You can download it from the LTspice Yahoo group.
>>
>>http://tech.groups.yahoo.com/group/LTspice/
>>Files > Lib > CD4046
>>
>>Best regards,
>>Helmut
>>
> [snip]
>
> Hi Helmut,
>
> Thanks for a clean hierarchical schematic!
>
> Amusing myself with how to make a full behavioral model...
>
> Do you have any ideas on how to characterize a CMOS inverter?
>
> I think you could characterize an inverter as an input capacitance
> versus input voltage and the output as a resistance variable with
> input voltage and also with a capacitance likewise related.
>
> ...Jim Thompson
> --
> | James E.Thompson, CTO | mens |
> | Analog Innovations, Inc. | et |
> | Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
> | Phoenix, Arizona 85048 Skype: Contacts Only | |
> | Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
> | E-mail Icon at http://www.analog-innovations.com | 1962 |
>
> I can see November from my house :-)
Hello Jim,
I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.
Best regards,
Helmut
Reply by Muzaffer Kal●October 10, 20102010-10-10
On Sun, 10 Oct 2010 10:25:34 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:
>Do you have any ideas on how to characterize a CMOS inverter?
One usually uses input transition rate and output load as parameters
to characterize the behavior of an inverter (or any other gate) ie you
make tables of delays which give you output delay and transition given
input transition and output load (usually only in terms of
capacitance) for a specific corner of pvt.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
Reply by Jim Thompson●October 10, 20102010-10-10
On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"
<helmutsennewald@t-online.de> wrote:
>Hello,
>
>I have written sometimes ago a CD4046 model for LTspice.
>You can download it from the LTspice Yahoo group.
>
>http://tech.groups.yahoo.com/group/LTspice/
>Files > Lib > CD4046
>
>Best regards,
>Helmut
>
[snip]
Hi Helmut,
Thanks for a clean hierarchical schematic!
Amusing myself with how to make a full behavioral model...
Do you have any ideas on how to characterize a CMOS inverter?
I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
Reply by Helmut Sennewald●October 10, 20102010-10-10
Hello,
I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.
http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046
Best regards,
Helmut
"volkerk" <volkerkible@n_o_s_p_a_m.n_o_s_p_a_m.gmx.net> schrieb im
Newsbeitrag news:65adncxqVvmzXzDRnZ2dnUVZ_smdnZ2d@giganews.com...
> Thanx,
>
> Unluckily the missing dots were not the problem, as they are at the right
> places in my file - they must have gotten lost somewhere while posting the
> file contents to this thread.
>
> I looked up in the netlist of my test file, and the "instantiation" is as
> follows:
> "XU1 N003 N004 NC_01 N005 N001 N009 N008 NC_02 N006 N007 N001 NC_03 0
> NC_04
> N010 0 CD4046
> " (number of connections: 16)
> Are there no not connected nodes (NC_xx) allowed?
>
> For reference: The model's "portlist" is as follows:
> ".subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin
> + r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
> + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
> + PARAMS: MNTYMXDLY=0 IO_LEVEL=0
> + Rin=1Meg S1=1 S2=0.5 M1=0.5 M2=1.0 Vx=10
> + Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10
> " (number of ports: 16 if i count right???)
>
> And there are 16 pins defined in the Symbol.
> I also tried to make two more pins in case the "OPTIONAL:" field in the
> model's "header" also counts as ports (what i think is not the case) - i
> got the same error message.
>
> Can it be something else? I'm really a bit lost.
>
> ---------------------------------------
> Posted through http://www.Electronics-Related.com
Reply by Fred Abse●October 8, 20102010-10-08
On Thu, 07 Oct 2010 09:04:59 -0700, Jim Thompson wrote:
> On Thu, 07 Oct 2010 07:50:54 -0500, "volkerk"
> <volkerkible@n_o_s_p_a_m.n_o_s_p_a_m.gmx.net> wrote:
>
>>Thanx,
>>
>>Unluckily the missing dots were not the problem, as they are at the right
>>places in my file - they must have gotten lost somewhere while posting the
>>file contents to this thread.
>>
>>I looked up in the netlist of my test file, and the "instantiation" is as
>>follows:
>>"XU1 N003 N004 NC_01 N005 N001 N009 N008 NC_02 N006 N007 N001 NC_03 0 NC_04
>>N010 0 CD4046
>>" (number of connections: 16)
>>Are there no not connected nodes (NC_xx) allowed?
>>
>>For reference: The model's "portlist" is as follows:
>>".subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin
>>+ r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
>>+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
>>+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
>>+ Rin=1Meg S1=1 S2=0.5 M1=0.5 M2=1.0 Vx=10
>>+ Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10
>>" (number of ports: 16 if i count right???)
>>
>>And there are 16 pins defined in the Symbol.
>>I also tried to make two more pins in case the "OPTIONAL:" field in the
>>model's "header" also counts as ports (what i think is not the case) - i
>>got the same error message.
>>
>>Can it be something else? I'm really a bit lost.
>>
>
> The pin/node count matches. Comment out the "OPTIONAL:" line and see
> what happens.
>
It appears that it is necessary to include the whole Orcad mix_misc
library, plus other libraries which mix_misc references.
I don't like libraries that require other libraries. Stinks of
programmers' methods. Change one thing and break lots of others.
Also, the Orcad libraries include syntax that LTSpice doesn't understand.
Major rewrite necessary.
--
"For a successful technology, reality must take precedence
over public relations, for nature cannot be fooled."
(Richard Feynman)