Reply by Tom Del Rosso April 28, 20162016-04-28
Jim Thompson wrote:
> > Did you notice you're replying to a YEAR OLD post ?:-)
On the phone app it wasn't so obvious. I don't use it much but it was updated a month ago so I don't know why this thread was near the top.
Reply by Jim Thompson April 27, 20162016-04-27
On Wed, 27 Apr 2016 15:19:18 -0400 (EDT), Tom Del Rosso
<fizzbintuesday@THAT.GOOGLE.EMAIL.DOMAIN.COM> wrote:

>Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> > Wrote in message: >> On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>>On Wed, 01 Apr 2015 13:27:06 -0500, John Fields >>><jfields@austininstruments.com> wrote: >>> >>>>On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> >>>>>For a simulation situation I need a random number generator with a >>>>>twist... >>>>> >>>>>What I need to simulate is a "random" selection of one-of-16 outputs. >>>>> >>>>>Clock "speed" is 12.5kHz ;-) >>>>> >>>>>Built of 74HCxx parts is preferred... I have a full ensemble of those >>>>>device in my PSpice library. >>>>> >>>>>Thanks in advance. >>>>> >>>>> ...Jim Thompson >>>> >>>>--- >>>>If you use something like an HC154 with an LFSR driving its address >>>>inputs to generate random one-hots on its outputs, will that work >>>>for you? >>> >>>John, >>> >>>What are you saying... take the outputs of the LFSR broadside to drive >>>the address lines of the 'HC154? >>> >>>I think that would do it. >>> >>>Thanks also to Lasse for the same suggestion. >>> >>> ...Jim Thompson >> >> I was puzzling over how to get 0000, but then it dawned... just use an >> 8-bit LFSR and use the last 4-bits. > >It would be less than random because 0000 is still less likely. > Better to use a fast counter and latch it before the > 154. > >Because it's not physical maybe you'd have to jiggle the fast > clock with a large resistor to one of the bits, if Spice would > have a tendency to make one clock an exact multiple of the other. >
Did you notice you're replying to a YEAR OLD post ?:-) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The touchstone of liberalism is intolerance
Reply by Tom Del Rosso April 27, 20162016-04-27
Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com>
 Wrote in message:
> On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson > <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>On Wed, 01 Apr 2015 13:27:06 -0500, John Fields >><jfields@austininstruments.com> wrote: >> >>>On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> >>>>For a simulation situation I need a random number generator with a >>>>twist... >>>> >>>>What I need to simulate is a "random" selection of one-of-16 outputs. >>>> >>>>Clock "speed" is 12.5kHz ;-) >>>> >>>>Built of 74HCxx parts is preferred... I have a full ensemble of those >>>>device in my PSpice library. >>>> >>>>Thanks in advance. >>>> >>>> ...Jim Thompson >>> >>>--- >>>If you use something like an HC154 with an LFSR driving its address >>>inputs to generate random one-hots on its outputs, will that work >>>for you? >> >>John, >> >>What are you saying... take the outputs of the LFSR broadside to drive >>the address lines of the 'HC154? >> >>I think that would do it. >> >>Thanks also to Lasse for the same suggestion. >> >> ...Jim Thompson > > I was puzzling over how to get 0000, but then it dawned... just use an > 8-bit LFSR and use the last 4-bits.
It would be less than random because 0000 is still less likely. Better to use a fast counter and latch it before the 154. Because it's not physical maybe you'd have to jiggle the fast clock with a large resistor to one of the bits, if Spice would have a tendency to make one clock an exact multiple of the other. --
Reply by John Fields May 7, 20152015-05-07
On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
<eather@tpg.com.au> wrote:


>A paraphrase: >"anyone who believes a deterministic circuit can produce true randomness >is in a state of sin"
--- Beautiful. John Fields
Reply by John Larkin April 29, 20152015-04-29
On Wed, 29 Apr 2015 02:16:52 -0500, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>Er, well.. surely an LFSR will be flat, not Gaussian, no?
Single bit digital noise has a PDF with two big impulses, about the worst approximation to Gaussian (or flat) imaginable. So you need to sum a LOT of them to get something sort of Gaussian... the Central Limit Theorem thing. Hence the 20 KHz filter. Higher-order filters work way better than single-pole ones. If you nab 16-bit words from the shift register, and not the single bit, you start with a basically flat histogram. Summing a modest number of them gets Gaussian pretty fast. That's harder to Spice.
> >Fortunately, there is an app\\\ transform for that: >http://www.design.caltech.edu/erik/Misc/Gaussian.html >shouldn't be too bad to implement on FPGA. Log can be very crudely >obtained as the highest active ('1') bit position, and can be improved >iteratively (by repeated squarings and bit-shifts, or Taylor series >polynomial approximation methods). > >Obviously, to shoot it out of a DAC, the bounds must be strictly limited, >so part of your spec will be how many sigma of Gaussian it's good for >(usually 3 or so?).
We have a +-10 volt DAC range, and we figure that 1 volt RMS is a good number, and our 15-tap FIR filter will give us a crest factor of about 5.5. That sounds OK; I don't think our customers would want truly Gaussian noise with infinite voltage spikes.
> >Which, in turn, implies that the argument of the log can't be near zero >(which is what produces the peaky outliers), and certainly can't be zero >exactly (which would be undefined), so perhaps the LFSR's inherent bias >could be tuned to match the dynamic range of the desired output? Nah, >probably not, not for any reasonable sequence length. So you'll have to >do something ugly (and hopefully not badly behaved), like RND * scale + >offset. > >There are also methods for that -- ensuring that an output of truncated, >arbitrary range is calculated correctly from an even distribution in some >other range. > >The geometric form is interesting, too; a random time delay could trigger >a S&H of complementary (90 degree phase shifted) sine waves, and the other >random number could feed a suitable arrangement of matched diode junctions >or OTAs which computes the sqrt(ln(x)) function, and simultaneously >controls the gain on the S&H buffers. > >The "random" time delay has a strictly bounded range, so it could be >triggered on a fixed clock, 'computed', then 'registered' with a second >S&H on the following clock pulse, to give regularly sampled outputs (same >as you'd use extra D-flops to neaten up the transitions in a digital logic >circuit). Who even needs a DAC? ;) > >Or you could randomly sample a sin/cos table and vary the VREF into an >MDAC, or...
A tapped analog delay line is easy to Spice. If you poke in random values and evenly sum the taps, that amounts to summing a sucession of samples, so it does the Central Limit thing for you. And it's also a finite-impulse-response filter. Everything turns out the be the same thing, just looked at from different angles. I really need a histogram back end for LT Spice. Snarl, snap, I guess I'll have to make one. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by Bob Masta April 29, 20152015-04-29
On Tue, 28 Apr 2015 21:38:58 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>For a simulation situation I need a random number generator with a >>twist... >> >>What I need to simulate is a "random" selection of one-of-16 outputs. >> >>Clock "speed" is 12.5kHz ;-) >> >>Built of 74HCxx parts is preferred... I have a full ensemble of those >>device in my PSpice library. >> >>Thanks in advance. >> >> ...Jim Thompson > >Only vaguely on-topic, here is a noise generator experiment. The mess >on the left makes 1-bit digital noise clocked at 1 MHz, like a linear >shift register, just easier to draw. The issue at hand is what kind of >lowpass filter to use to get approximately Gaussian noise. > >The 200 KHz filter is right out of AoE3 p 559. It looks fine in the >audio frequency domain, but it's nothing like Gaussian. > >The 3-pole filter is a lot nicer. > >We're actually going to use a LFSR in an FPGA and do the serious >filtering digitally, and drive a DAC with a little analog filtering >afterwards.
I have a Daqarta "mini-app" for converting a uniform to an arbitrary distribution. I use Gaussian as the example. The Help page is at <http://www.daqarta.com/dw_0oaa.htm>. It includes a "Theory" section, plus the complete macro script (it's in Daqarta's own macro language, but I've added lots of comments). The basic method uses the inverse Cumulative Distribution Function (iCDF) with a lookup table. The trick is to create the proper table. Best regards, Bob Masta DAQARTA v7.60 Data AcQuisition And Real-Time Analysis www.daqarta.com Scope, Spectrum, Spectrogram, Sound Level Meter Frequency Counter, Pitch Track, Pitch-to-MIDI FREE Signal Generator, DaqMusiq generator Science with your sound card!
Reply by Jasen Betts April 29, 20152015-04-29
On 2015-04-29, David Eather <eather@tpg.com.au> wrote:
> On Tue, 28 Apr 2015 17:15:27 +1000, Jasen Betts <jasen@xnet.co.nz> wrote: > >> On 2015-04-27, Bob Masta <N0Spam@daqarta.com> wrote: >>> On Sun, 26 Apr 2015 09:32:00 -0400, rickman >>> <gnuarm@gmail.com> wrote: >>> >>> <snip> >>> >>>> Really? There are many ways of generating PRS. There are trade-offs >>>> with each one. If you don't need the speed or small size an LFSR has >>>> disadvantages compared to many others. >>> >>> I hesitate to get into this, err, "discussion", but in >>> software at least, an LFSR has one nifty advantage over the >>> simpler and more-common linear congruential approach: You >>> can run it backwards! >> >> You can run a linear congruential backwards it's just a matter of >> using different factor and addend constants. >> > > I've never seen that. I would like to.
#include <stdio.h> unsigned int seed=1; /* a common LC random */ unsigned int rand(void){ seed= ((long long) seed*1103515245 + 12345 ) &0xfffffffful; return seed; } /* the inverse */ unsigned int unrand(void){ seed=((long long) seed *4005161829 + 4235699843) &0xfffffffful ; return seed; } /* 4005161829 above is the reciprocal of 1103515245 mod 2^32 knowing that multiplication by 1103515245 would have a period of 2^32 in mod 2^32 I asked wolfram alpha "1103515245 ^4294967295 mod 4294967296" 4235699843 above is the additive inverse of 12345 * 4005161829 mod 2^32 I asked wolfram alpha "4294967296 - (( 12345 * 4005161829 ) mod 4294967296 )" modular arithmetic is crazy stuff... */ main(){ int x; printf("%10u ",seed); printf("> %10u\n", rand()); printf("%10u ",seed); printf("> %10u\n", rand()); printf("%10u ",seed); printf("> %10u\n", rand()); printf("%10u ",seed); printf("> %10u\n", rand()); printf("%10u ",seed); printf("> %10u\n", rand()); printf("%10u ",seed); printf("> %10u\n", rand()); printf("--------------------\n"); printf("%10u ",seed); printf("< %10u\n", unrand()); printf("%10u ",seed); printf("< %10u\n", unrand()); printf("%10u ",seed); printf("< %10u\n", unrand()); printf("%10u ",seed); printf("< %10u\n", unrand()); printf("%10u ",seed); printf("< %10u\n", unrand()); printf("%10u ",seed); printf("< %10u\n", unrand()); printf("--------------------\n"); seed=8008135; printf("%10u >>>",seed); for( x=1; x< 10000000; ++x ) rand(); printf("%10u\n",seed); printf("%10u <<<",seed); for( x=1; x< 10000000; ++x ) unrand(); printf("%10u\n",seed); return 0; } -- umop apisdn
Reply by Tim Williams April 29, 20152015-04-29
Er, well.. surely an LFSR will be flat, not Gaussian, no?

Fortunately, there is an app\\\ transform for that:
http://www.design.caltech.edu/erik/Misc/Gaussian.html
shouldn't be too bad to implement on FPGA.  Log can be very crudely 
obtained as the highest active ('1') bit position, and can be improved 
iteratively (by repeated squarings and bit-shifts, or Taylor series 
polynomial approximation methods).

Obviously, to shoot it out of a DAC, the bounds must be strictly limited, 
so part of your spec will be how many sigma of Gaussian it's good for 
(usually 3 or so?).

Which, in turn, implies that the argument of the log can't be near zero 
(which is what produces the peaky outliers), and certainly can't be zero 
exactly (which would be undefined), so perhaps the LFSR's inherent bias 
could be tuned to match the dynamic range of the desired output?  Nah, 
probably not, not for any reasonable sequence length.  So you'll have to 
do something ugly (and hopefully not badly behaved), like RND * scale + 
offset.

There are also methods for that -- ensuring that an output of truncated, 
arbitrary range is calculated correctly from an even distribution in some 
other range.

The geometric form is interesting, too; a random time delay could trigger 
a S&H of complementary (90 degree phase shifted) sine waves, and the other 
random number could feed a suitable arrangement of matched diode junctions 
or OTAs which computes the sqrt(ln(x)) function, and simultaneously 
controls the gain on the S&H buffers.

The "random" time delay has a strictly bounded range, so it could be 
triggered on a fixed clock, 'computed', then 'registered' with a second 
S&H on the following clock pulse, to give regularly sampled outputs (same 
as you'd use extra D-flops to neaten up the transitions in a digital logic 
circuit).  Who even needs a DAC? ;)

Or you could randomly sample a sin/cos table and vary the VREF into an 
MDAC, or...

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

"John Larkin" <jlarkin@highlandtechnology.com> wrote in message 
news:2fn0kahdail5e4u0ddh460mmfnnm2pd7rh@4ax.com...
> On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson > <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>For a simulation situation I need a random number generator with a >>twist... >> >>What I need to simulate is a "random" selection of one-of-16 outputs. >> >>Clock "speed" is 12.5kHz ;-) >> >>Built of 74HCxx parts is preferred... I have a full ensemble of those >>device in my PSpice library. >> >>Thanks in advance. >> >> ...Jim Thompson > > Only vaguely on-topic, here is a noise generator experiment. The mess > on the left makes 1-bit digital noise clocked at 1 MHz, like a linear > shift register, just easier to draw. The issue at hand is what kind of > lowpass filter to use to get approximately Gaussian noise. > > The 200 KHz filter is right out of AoE3 p 559. It looks fine in the > audio frequency domain, but it's nothing like Gaussian. > > The 3-pole filter is a lot nicer. > > We're actually going to use a LFSR in an FPGA and do the serious > filtering digitally, and drive a DAC with a little analog filtering > afterwards. > > > Version 4 > SHEET 1 1316 680 > WIRE 912 -64 848 -64 > WIRE 1056 -64 912 -64 > WIRE 1200 -64 1136 -64 > WIRE 1248 -64 1200 -64 > WIRE 1312 -64 1248 -64 > WIRE 1200 -16 1200 -64 > WIRE 368 64 208 64 > WIRE 480 64 368 64 > WIRE 208 96 208 64 > WIRE 1200 96 1200 48 > WIRE 720 112 656 112 > WIRE 752 112 720 112 > WIRE 432 128 400 128 > WIRE 480 128 432 128 > WIRE 208 208 208 176 > WIRE 848 208 848 -64 > WIRE 912 208 848 208 > WIRE 1056 208 992 208 > WIRE 1200 208 1136 208 > WIRE 1248 208 1200 208 > WIRE 1312 208 1248 208 > WIRE 848 240 848 208 > WIRE 400 256 400 128 > WIRE 1200 256 1200 208 > WIRE 400 368 400 336 > WIRE 848 368 848 320 > WIRE 1200 368 1200 320 > FLAG 208 208 0 > FLAG 368 64 NOISE > FLAG 400 368 0 > FLAG 720 112 SH > FLAG 848 368 0 > FLAG 912 -64 COMP > FLAG 1200 368 0 > FLAG 1248 208 LPF2 > FLAG 432 128 CLK > FLAG 1200 96 0 > FLAG 1248 -64 LPF1 > SYMBOL bv 208 80 R0 > WINDOW 0 -63 105 Left 2 > WINDOW 3 -131 174 Left 2 > SYMATTR InstName B1 > SYMATTR Value V=random(1.83e7*time) - 0.5 > SYMBOL SpecialFunctions\\sample 560 96 R0 > SYMATTR InstName A1 > SYMBOL voltage 400 240 R0 > WINDOW 0 -85 76 Left 2 > WINDOW 3 -323 114 Left 2 > WINDOW 123 0 0 Left 2 > WINDOW 39 0 0 Left 2 > SYMATTR InstName V1 > SYMATTR Value PULSE(0 1 0 0 0 500n 1u) > SYMBOL bv 848 224 R0 > WINDOW 0 -120 42 Left 2 > WINDOW 3 -187 87 Left 2 > SYMATTR InstName B2 > SYMATTR Value V=sgn(v(sh)) > SYMBOL res 1152 192 R90 > WINDOW 0 69 58 VBottom 2 > WINDOW 3 75 56 VTop 2 > SYMATTR InstName R2 > SYMATTR Value 1K > SYMBOL cap 1184 256 R0 > WINDOW 0 51 15 Left 2 > WINDOW 3 50 51 Left 2 > SYMATTR InstName C1 > SYMATTR Value 5n > SYMBOL res 1152 -80 R90 > WINDOW 0 69 58 VBottom 2 > WINDOW 3 75 56 VTop 2 > SYMATTR InstName R1 > SYMATTR Value 5K > SYMBOL cap 1184 -16 R0 > WINDOW 0 51 15 Left 2 > WINDOW 3 50 51 Left 2 > SYMATTR InstName C2 > SYMATTR Value 150p > SYMBOL ind 896 224 R270 > WINDOW 0 -33 54 VTop 2 > WINDOW 3 -39 51 VBottom 2 > SYMATTR InstName L1 > SYMATTR Value 17m > TEXT 552 -48 Left 2 !.tran 25m > TEXT 216 -72 Left 2 ;Noise Generator Test > TEXT 208 -32 Left 2 ;J Larkin April 28, 2015 > TEXT 432 240 Left 2 ;1 MHz CLOCK > TEXT 640 352 Left 2 ;COMPARATOR > TEXT 1056 48 Left 2 ;200 KHz > TEXT 1056 312 Left 2 ;20 KHz > TEXT 864 56 Left 2 ;DIGITAL > TEXT 864 88 Left 2 ;NOISE > > > > -- > > John Larkin Highland Technology, Inc > picosecond timing laser drivers and controllers > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.com >
Reply by John Larkin April 29, 20152015-04-29
On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>For a simulation situation I need a random number generator with a >twist... > >What I need to simulate is a "random" selection of one-of-16 outputs. > >Clock "speed" is 12.5kHz ;-) > >Built of 74HCxx parts is preferred... I have a full ensemble of those >device in my PSpice library. > >Thanks in advance. > > ...Jim Thompson
Only vaguely on-topic, here is a noise generator experiment. The mess on the left makes 1-bit digital noise clocked at 1 MHz, like a linear shift register, just easier to draw. The issue at hand is what kind of lowpass filter to use to get approximately Gaussian noise. The 200 KHz filter is right out of AoE3 p 559. It looks fine in the audio frequency domain, but it's nothing like Gaussian. The 3-pole filter is a lot nicer. We're actually going to use a LFSR in an FPGA and do the serious filtering digitally, and drive a DAC with a little analog filtering afterwards. Version 4 SHEET 1 1316 680 WIRE 912 -64 848 -64 WIRE 1056 -64 912 -64 WIRE 1200 -64 1136 -64 WIRE 1248 -64 1200 -64 WIRE 1312 -64 1248 -64 WIRE 1200 -16 1200 -64 WIRE 368 64 208 64 WIRE 480 64 368 64 WIRE 208 96 208 64 WIRE 1200 96 1200 48 WIRE 720 112 656 112 WIRE 752 112 720 112 WIRE 432 128 400 128 WIRE 480 128 432 128 WIRE 208 208 208 176 WIRE 848 208 848 -64 WIRE 912 208 848 208 WIRE 1056 208 992 208 WIRE 1200 208 1136 208 WIRE 1248 208 1200 208 WIRE 1312 208 1248 208 WIRE 848 240 848 208 WIRE 400 256 400 128 WIRE 1200 256 1200 208 WIRE 400 368 400 336 WIRE 848 368 848 320 WIRE 1200 368 1200 320 FLAG 208 208 0 FLAG 368 64 NOISE FLAG 400 368 0 FLAG 720 112 SH FLAG 848 368 0 FLAG 912 -64 COMP FLAG 1200 368 0 FLAG 1248 208 LPF2 FLAG 432 128 CLK FLAG 1200 96 0 FLAG 1248 -64 LPF1 SYMBOL bv 208 80 R0 WINDOW 0 -63 105 Left 2 WINDOW 3 -131 174 Left 2 SYMATTR InstName B1 SYMATTR Value V=random(1.83e7*time) - 0.5 SYMBOL SpecialFunctions\\sample 560 96 R0 SYMATTR InstName A1 SYMBOL voltage 400 240 R0 WINDOW 0 -85 76 Left 2 WINDOW 3 -323 114 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 0 0 500n 1u) SYMBOL bv 848 224 R0 WINDOW 0 -120 42 Left 2 WINDOW 3 -187 87 Left 2 SYMATTR InstName B2 SYMATTR Value V=sgn(v(sh)) SYMBOL res 1152 192 R90 WINDOW 0 69 58 VBottom 2 WINDOW 3 75 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 1K SYMBOL cap 1184 256 R0 WINDOW 0 51 15 Left 2 WINDOW 3 50 51 Left 2 SYMATTR InstName C1 SYMATTR Value 5n SYMBOL res 1152 -80 R90 WINDOW 0 69 58 VBottom 2 WINDOW 3 75 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 5K SYMBOL cap 1184 -16 R0 WINDOW 0 51 15 Left 2 WINDOW 3 50 51 Left 2 SYMATTR InstName C2 SYMATTR Value 150p SYMBOL ind 896 224 R270 WINDOW 0 -33 54 VTop 2 WINDOW 3 -39 51 VBottom 2 SYMATTR InstName L1 SYMATTR Value 17m TEXT 552 -48 Left 2 !.tran 25m TEXT 216 -72 Left 2 ;Noise Generator Test TEXT 208 -32 Left 2 ;J Larkin April 28, 2015 TEXT 432 240 Left 2 ;1 MHz CLOCK TEXT 640 352 Left 2 ;COMPARATOR TEXT 1056 48 Left 2 ;200 KHz TEXT 1056 312 Left 2 ;20 KHz TEXT 864 56 Left 2 ;DIGITAL TEXT 864 88 Left 2 ;NOISE -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by David Eather April 28, 20152015-04-28
On Tue, 28 Apr 2015 17:15:27 +1000, Jasen Betts <jasen@xnet.co.nz> wrote:

> On 2015-04-27, Bob Masta <N0Spam@daqarta.com> wrote: >> On Sun, 26 Apr 2015 09:32:00 -0400, rickman >> <gnuarm@gmail.com> wrote: >> >> <snip> >> >>> Really? There are many ways of generating PRS. There are trade-offs >>> with each one. If you don't need the speed or small size an LFSR has >>> disadvantages compared to many others. >> >> I hesitate to get into this, err, "discussion", but in >> software at least, an LFSR has one nifty advantage over the >> simpler and more-common linear congruential approach: You >> can run it backwards! > > You can run a linear congruential backwards it's just a matter of > using different factor and addend constants. > >
I've never seen that. I would like to.